Search results for "Virtex"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
8	Christopher C. Doss, Robert L. Riley Jr.	FPGA-based implementation of single-precision exponential unit.	FPGA	2004	DBLP DOI BibTeX RDF
8	Paul Berube, José Nelson Amaral, Mike H. MacGregor	An FPGA prototype for the experimental evaluation of a multizone network cache.	FPGA	2004	DBLP DOI BibTeX RDF
8	Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller 0006	Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 trigger.	FPGA	2004	DBLP DOI BibTeX RDF
8	Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers	A quantitative analysis of the speedup factors of FPGAs over processors.	FPGA	2004	DBLP DOI BibTeX RDF	performance, FPGA, analysis, VHDL, reconfigurable computing
8	Suleyman Malki, Lambert Spaanenburg	On the Packet-Switched Implementation of a Discrete-Time CNN.	DSD	2004	DBLP DOI BibTeX RDF	FPGA, Image Processing, Packet Switching, Cellular Neural Network
8	Maik Boden, Manfred Koegst, José Luis Tiburcio Badía, Steffen Rülke	Cost-Efficient Implementation of Adaptive Finite State Machines.	DSD	2004	DBLP DOI BibTeX RDF
8	Dimitris G. Bariamis, Dimitrios K. Iakovidis, Dimitrios E. Maroulis, S. A. Karkanis	An FPGA-Based Architecture for Real Time Image Feature Extraction.	ICPR (1)	2004	DBLP DOI BibTeX RDF
8	Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis	The PowerPC Backend Molen Compiler.	FPL	2004	DBLP DOI BibTeX RDF
8	Joseph M. Palmer, Brent E. Nelson	A Parallel FFT Architecture for FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
8	Herbert Walder, Marco Platzner	A Runtime Environment for Reconfigurable Hardware Operating Systems.	FPL	2004	DBLP DOI BibTeX RDF
8	Guerric Meurice de Dormale, Philippe Bulens, Jean-Jacques Quisquater	Efficient Modular Division Implementation: ECC over GF(p) Affine Coordinates Application.	FPL	2004	DBLP DOI BibTeX RDF
8	Jesús Lázaro 0001, Armando Astarloa, Jagoba Arias, Unai Bidarte, Carlos Cuadrado	High Throughput Serpent Encryption Implementation.	FPL	2004	DBLP DOI BibTeX RDF
8	Abilio Parreira, João Paulo Teixeira 0001, Marcelino B. Santos	FPGAs BIST Evaluation.	FPL	2004	DBLP DOI BibTeX RDF
8	Jonathan Noel Tombs, Miguel Angel Aguirre Echánove, Fernando Muñoz 0001, Vicente Baena Lecuyer, Antonio Jesús Torralba Silgado, A. Fernandez-León, Francisco Tortosa	The Implementation of a FPGA Hardware Debugger System with Minimal System Overhead.	FPL	2004	DBLP DOI BibTeX RDF
8	Norbert Pramstaller, Johannes Wolkerstorfer	A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays.	FPL	2004	DBLP DOI BibTeX RDF
8	Michael Ullmann, Michael Hübner 0001, Björn Grimm, Jürgen Becker 0001	On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities.	FPL	2004	DBLP DOI BibTeX RDF
8	Eduardo Picatoste-Olloqui, Francisco Cardells-Tormo, Jordi Sempere-Agulló, Atilà Herms-Berenguer	Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA.	FPL	2004	DBLP DOI BibTeX RDF
8	Daniel Denning, James Irvine 0001, Malachy Devlin	A Key Agile 17.4 Gbit/sec Camellia Implementation.	FPL	2004	DBLP DOI BibTeX RDF
8	Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer	FPGA Custom DSP for ECG Signal Analysis and Compression.	FPL	2004	DBLP DOI BibTeX RDF
8	Chris Clarke, Lin Qiang, Herbert Peremans, Álvaro Hernández	FPGA Implementation of a Neuromimetic Cochlea for a Bionic Bat Head.	FPL	2004	DBLP DOI BibTeX RDF
8	Alexandra Poetter, Jesse Hunter, Cameron D. Patterson, Peter M. Athanas, Brent E. Nelson, Neil Steiner	JHDLBits: The Merging of Two Worlds.	FPL	2004	DBLP DOI BibTeX RDF
8	Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides	Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation.	FPL	2004	DBLP DOI BibTeX RDF
8	David B. Thomas, Wayne Luk	Implementing Graphics Shaders Using FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
8	Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller 0006	Using of FPGA Coprocessor for Improving the Execution Speed of the Pattern Recognition Algorithm for ATLAS - High Energy Physics Experiment.	FPL	2004	DBLP DOI BibTeX RDF
8	Emre Özer 0001, Andy Nisbet, David Gregg	Automatic Customization of Embedded Applications for Enhanced Performance and Reduced Power Using Optimizing Compiler Techniques.	Euro-Par	2004	DBLP DOI BibTeX RDF
8	Paulo Sérgio B. do Nascimento, Paulo Romero Martins Maciel, Manoel Eusébio de Lima, Remy Eskinazi Sant'Anna, Abel Guilhermino Silva-Filho	A partial reconfigurable architecture for controllers based on Petri nets.	SBCCI	2004	DBLP DOI BibTeX RDF	virtual hardware, FPGAs, Petri nets, partial reconfiguration, programmable logic controller (PLC)
8	Heiko Kalte, Mario Porrmann, Ulrich Rückert 0001	System-on-Programmable-Chip Approach Enabling Online Fine-Grained 1D-Placement.	IPDPS	2004	DBLP DOI BibTeX RDF
8	Jianchun Li, Christos A. Papachristou, Raj Shekhar	A Reconfigurable SoC Architecture and Caching Scheme for 3D Medical Image Processing.	FCCM	2004	DBLP DOI BibTeX RDF
8	Dong-U Lee, Wayne Luk, Connie Wang, Christopher R. Jones 0001, Michael Smith 0020, John D. Villasenor	A Flexible Hardware Encoder for Low-Density Parity-Check Codes.	FCCM	2004	DBLP DOI BibTeX RDF
8	Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis	The MOLEN Processor Prototype.	FCCM	2004	DBLP DOI BibTeX RDF
8	Emre Özer 0001, Andy Nisbet, David Gregg	Fine-Tuning Loop-Level Parallelism for Increasing Performance of DSP Applications on FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
8	David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee	Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
8	Lev Kirischian, Irina Terterian, Pil Woo Chun, Vadim Geurkov	Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-Architecture.	PARELEC	2004	DBLP DOI BibTeX RDF
8	Erik Chmelar	Minimizing the number of test configurations for FPGAs.	ICCAD	2004	DBLP DOI BibTeX RDF
8	Greg Knowles, Paul Gardner-Stephen	A New Hardware Architecture for Genomic and Proteomic Sequence Alignment.	CSB	2004	DBLP DOI BibTeX RDF
8	Miguel Morales-Sandoval, Claudia Feregrino Uribe	On the Hardware Design of an Elliptic Curve Cryptosystem.	ENC	2004	DBLP DOI BibTeX RDF
8	Gaël Rouvroy, François-Xavier Standaert, Frédéric Lefèbvre, Jean-Jacques Quisquater, Benoît Macq, Jean-Didier Legat	Reconfigurable hardware solutions for the digital rights management of digital cinema.	Digital Rights Management Workshop	2004	DBLP DOI BibTeX RDF	FPGA, watermarking, AES, DRM, JPEG 2000, digital cinema
8	Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs.	IOLTS	2004	DBLP DOI BibTeX RDF
8	David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee	Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	scheduling, optimizations, FPGAs, compilers, binary translation, chaining, hardware synthesis
8	Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat	Compact and Efficient Encryption/Decryption Module for FPGA Implementation of the AES Rijndael Very Well Suited for Small Embedded Applications.	ITCC (2)	2004	DBLP DOI BibTeX RDF	compact encryption/decryption implementation, FPGA, Cryptography, AES, DES
8	Kaijie Wu 0001, Ramesh Karri, Grigori Kuznetsov, Michael Gössel	Low Cost Concurrent Error Detection for the Advanced Encryption Standard.	ITC	2004	DBLP DOI BibTeX RDF
8	Yang Zhang, Stephen L. Smith 0002, Andy M. Tyrrell	Digital Circuit Design using Intrinsic Evolvable Hardware.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
8	Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee	Automatic translation of software binaries onto FPGAs.	DAC	2004	DBLP DOI BibTeX RDF	compiler, reconfigurable computing, binary translation, hardware-software co-design, decompilation
8	Richard Canham, Andrew M. Tyrrell	A Hardware Artificial Immune System and Embryonic Array for Fault Tolerant Systems.	Genet. Program. Evolvable Mach.	2003	DBLP DOI BibTeX RDF	embryonic array, fault tolerance, artificial immune system
8	Massimo Ravasi, Marco Mattavelli, Paul R. Schumacher, Robert D. Turney	High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder.	PATMOS	2003	DBLP DOI BibTeX RDF
8	Alex K. Jones, Prithviraj Banerjee	An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF
8	Sébastien Bilavarn, Guy Gogniat, Jean Luc Philippe	An estimation and exploration methodology from system-level specifications: application to FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF
8	Khaled Benkrid, S. Sukhsawas, Danny Crookes, Samir Belkacemi	A single-FPGA implementation of image connected component labelling.	FPGA	2003	DBLP DOI BibTeX RDF
8	Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat	Design strategies and modified descriptions to optimize cipher FPGA implementations: fast and compact results for DES and triple-DES.	FPGA	2003	DBLP DOI BibTeX RDF
8	Wai-Kei Mak	I/O placement for FPGAs with multiple I/O standards.	FPGA	2003	DBLP DOI BibTeX RDF	I/O placement, I/O standards, field-programmable gate array, placement
8	Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose	Automatic transistor and physical design of FPGA tiles from an architectural specification.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA, programmable logic, PLD, automatic layout
8	Khaled Benkrid, Samir Belkacemi, Danny Crookes	A logic based approach to hardware abstraction.	FPGA	2003	DBLP DOI BibTeX RDF
8	Abdsamad Benkrid, Danny Crookes, Khaled Benkrid	Design framework for the implementation of the 2-D orthogonal discrete wavelet transform on FPGA.	FPGA	2003	DBLP DOI BibTeX RDF
8	Matjaz Verderber, Andrej Zemva, Damjan Lampret	HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder.	DATE	2003	DBLP DOI BibTeX RDF
8	Brandon Blodget, Scott McMillan, Patrick Lysaght	A Lightweight Approach for Embedded Reconfiguration of FPGAs.	DATE	2003	DBLP DOI BibTeX RDF
8	Filip Traugott, Kim Andersson, Andreas Löfgren, Lennart Lindh	Successful Prototyping of a Real-Time Hardware Based Terrain Navigation Correlator Algorithm.	DSD	2003	DBLP DOI BibTeX RDF
8	Richard H. Turner, Roger F. Woods	Design Flow for Efficient FPGA Reconfiguration.	FPL	2003	DBLP DOI BibTeX RDF
8	Francisco Cardells-Tormo, Javier Valls-Coquillat, Vicenc Almenar-Terre	Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S.	FPL	2003	DBLP DOI BibTeX RDF
8	John W. Lockwood, Christopher E. Neely, Christopher K. Zuver, James Moscola, Sarang Dharmapurikar, David Lim	An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall.	FPL	2003	DBLP DOI BibTeX RDF
8	Khaled Benkrid, S. Sukhsawas, Danny Crookes, Abdsamad Benkrid	An FPGA-Based Image Connected Component Labeller.	FPL	2003	DBLP DOI BibTeX RDF
8	Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat	Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES.	FPL	2003	DBLP DOI BibTeX RDF	FPGA, cryptography, design methodology, DES, efficient implementations
8	Pasquale Corsonello, Stefania Perri, Maria Antonia Iachino, Giuseppe Cocorullo	Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems.	FPL	2003	DBLP DOI BibTeX RDF
8	Ioannis Sourdis, Dionisios N. Pnevmatikatos	Fast, Large-Scale String Match for a 10Gbps FPGA-Based Network Intrusion Detection System.	FPL	2003	DBLP DOI BibTeX RDF
8	Chi Wai Yu, K. H. Kwong, Kin-Hong Lee, Philip Heng Wai Leong	A Smith-Waterman Systolic Cell.	FPL	2003	DBLP DOI BibTeX RDF
8	Damian Dalton, Vivian Bessler, Jeffrey Griffiths, Andrew McCarthy, Abhay Vadher, Rory O'Kane, Rob Quigley, Declan O'Connor	APPLES: A Full Gate-Timing FPGA-Based Hardware Simulator.	FPL	2003	DBLP DOI BibTeX RDF
8	Iván González, Sergio López-Buedo, Francisco J. Gómez, Javier Martínez	Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm.	FPL	2003	DBLP DOI BibTeX RDF
8	Giacinto Paolo Saggese, Antonino Mazzeo, Nicola Mazzocca, Antonio G. M. Strollo	An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm.	FPL	2003	DBLP DOI BibTeX RDF
8	Seonil Choi, Viktor K. Prasanna	Time and Energy Efficient Matrix Factorization Using FPGAs.	FPL	2003	DBLP DOI BibTeX RDF
8	Toshihito Fujiwara, Kenji Fujimoto, Tsutomu Maruyama	A Real-Time Visualization System for PIV.	FPL	2003	DBLP DOI BibTeX RDF
8	Henry Styles, Wayne Luk	Branch Optimisation Techniques for Hardware Compilation.	FPL	2003	DBLP DOI BibTeX RDF
8	Sumit Mohanty, Viktor K. Prasanna	An Algorithm Designer's Workbench for Platform FPGA's.	FPL	2003	DBLP DOI BibTeX RDF
8	Máire McLoone, John V. McCanny	Very High Speed 17 Gbps SHACAL Encryption Architecture.	FPL	2003	DBLP DOI BibTeX RDF	SHACAL, NESSIE
8	Régis Leveugle, Lörinc Antoni, Béla Fehér	Dependability Analysis: A New Application for Run-Time Reconfiguration.	IPDPS	2003	DBLP DOI BibTeX RDF	hardware emulation, fault injection, dependability analysis, Digital circuits, run-time reconfiguration
8	Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West	Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture.	IPDPS	2003	DBLP DOI BibTeX RDF
8	Matjaz Verderber, Andrej Zemva, Andrej Trost	HW/SW Codesign of the MPEG-2 Video Decoder.	IPDPS	2003	DBLP DOI BibTeX RDF
8	Richard Canham, Andrew M. Tyrrell	A Learning, Multi-layered, Hardware Artificial Immune System Implemented upon an Embryonic Array.	ICES	2003	DBLP DOI BibTeX RDF
8	Weifeng Xu, Ramshankar Ramanarayanan, Russell Tessier	Adaptive Fault Recovery for Networked Reconfigurable Systems.	FCCM	2003	DBLP DOI BibTeX RDF
8	Janette Frigo, David Palmer 0006, Maya B. Gokhale, Marc Popkin-Paine	Gamma-Ray Pulsar Detection using Reconfigurable Computing Hardware.	FCCM	2003	DBLP DOI BibTeX RDF
8	Abdsamad Benkrid, Khaled Benkrid, Danny Crookes	Design and Implementation of a Generic 2-D Orthogonal Discrete Wavelet Transform on FPGA.	FCCM	2003	DBLP DOI BibTeX RDF
8	B. R. Lee, Neil Burgess	Improved Small Multiplier Based Multiplication, Squaring and Division.	FCCM	2003	DBLP DOI BibTeX RDF
8	George A. Constantinides	Perturbation Analysis for Word-length Optimization.	FCCM	2003	DBLP DOI BibTeX RDF
8	James Moscola, John W. Lockwood, Ronald Prescott Loui, Michael Pachos	Implementation of a Content-Scanning Module for an Internet Firewall.	FCCM	2003	DBLP DOI BibTeX RDF
8	Jingzhao Ou, Seonil Choi, Viktor K. Prasanna	Performance Modeling of Reconfigurable SoC Architectures and Energy-Efficient Mapping of a Class of Applications.	FCCM	2003	DBLP DOI BibTeX RDF
8	Preston A. Jackson, Brad L. Hutchings, Justin L. Tripp	Simulation and Synthesis of CSP-based Interprocess Communication.	FCCM	2003	DBLP DOI BibTeX RDF
8	Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung	A Hardware Gaussian Noise Generator for Channel Code Evaluation.	FCCM	2003	DBLP DOI BibTeX RDF
8	Jingfei Jiang, Xiaoqiang Ni, Minxuan Zhang	Reconfigurable Cipher Processing Framework and Implementation.	APPT	2003	DBLP DOI BibTeX RDF
8	Terrence S. T. Mak, Kai-Pui Lam	High Speed GAML-based Phylogenetic Tree Reconstruction Using HW/SW Codesign.	CSB	2003	DBLP DOI BibTeX RDF
8	Ryan J. Fong, Scott J. Harper, Peter M. Athanas	A Versatile Framework for FPGA Field Updates: An Application of Partial Self-Reconfiguation.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
8	Sanat Kamal Bahl	Design and Prototyping a Fast Hadamard Transformer for WCDMA.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
8	Sébastien Bilavarn, Guy Gogniat, Jean Luc Philippe, Lilian Bossuet	Fast prototyping of reconfigurable architectures from a C program.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
8	Shibu Menon, Chip-Hong Chang, Rui Xiao	FPGA implementation of a frequency adaptive learning SOFM for digital color still imaging.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
8	Hoda S. Abdel-Aty-Zohdy, Jacob N. Allen, Robert L. Ewing	Plastic NNs for biochemical detection.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
8	Theerayod Wiangtong, Chun Te Ewe, Peter Y. K. Cheung	SONICmole: a debugging environment for the UltraSONIC reconfigurable computer.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
8	Süleyman Sirri Demirsoy, Robert Beck, Andrew G. Dempster, Izzet Kale	Reconfigurable implementation of recursive DCT kernels for reduced quantization noise.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
8	Yiqun Zhu, Mohammed Benaissa	Reconfigurable Viterbi Decoding Using a New ACS Pipelining Technique.	ASAP	2003	DBLP DOI BibTeX RDF
8	John Marty Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani	An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals.	DFT	2003	DBLP DOI BibTeX RDF
8	John Marty Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani	A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits.	DFT	2003	DBLP DOI BibTeX RDF
8	Mehdi Baradaran Tahoori, Subhasish Mitra	Automatic Configuration Generation for FPGA Interconnect Testing.	VTS	2003	DBLP DOI BibTeX RDF
8	Dereck A. Fernandes, Ian G. Harris	Application of Built in Self-Test for Interconnect Testing of FPGAs.	ITC	2003	DBLP DOI BibTeX RDF
8	Alexander H. Jackson, Richard Canham, Andrew M. Tyrrell	Robot Fault-Tolerance Using an Embryonic Array.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF