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Found 3248 publication records. Showing 3248 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
12 | Jooeun Bang, Jaeho Kim, Seohee Jung, Suneui Park, Jaehyouk Choi |
A $47\text{fs}_{\text{rms}}$-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth. |
ISSCC |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Luca Lanzoni, Michele Resson, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino |
A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. |
ISSCC |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Ke Jiang, Jialu Hu, Chuxing Fang, Hongjing Li |
Adaptive Anti-jitter Optimization for Immersive Streaming in Metaverse Scenarios. |
HP3C |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Xuhong Lil, Jianghu Hong, Chunqi Shi, Leilei Huang, Boxiao Liu, Hao Deng 0003, Jinghong Chen, Runxi Zhang |
A 3.84 GHz 32 fs RMS Jitter Over-Sampling PLL with High-Gain Cross-Switching Phase Detector. |
ISCAS |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Hsi-Hao Huang, Chun-Hsien Liu, Tzu-Yun Huang, Sheng-Di Lin, Chen-Yi Lee |
Self-Restoring and Low-Jitter Circuits for High Timing-Resolution SPAD Sensing Applications. |
ISCAS |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Ding-Hao Wang, Jieh-Tsorng Wu |
A Digital Jitter Compensation Technique for Analog-to-Digital Converters. |
ISCAS |
2023 |
DBLP DOI BibTeX RDF |
|
12 | David C. Keezer, Dany Minier, Hongjie Li |
Experimental Evaluation of Jitter Reduction Methods for Multi-Gigahertz Test. |
ITC-Asia |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Yi-Hsuan Lee, Wei-Hao Chen, Shi-Yu Huang |
Self-Sufficient Clock Jitter Measurement Methodology Using Dithering-Based Calibration. |
ITC-Asia |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Mohamed Shehata, Ke Wang 0007, Julian L. Webber, Masayuki Fujita, Tadao Nagatsuma, Withawat Withayachumnankul |
Mitigating the Timing-Jitter in Terahertz Communications via Nyquist Pulse Shaping. |
OFC |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Guillaume Soudais, Tarik Graba, Yves Mathieu, Sébastien Bigo |
Jitter Compensation Mechanism for Dynamic Deterministic Networks. |
OFC |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán |
Special Session: On-chip jitter BIST with sub-picosecond resolution at GHz frequencies. |
LATS |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Jin Sun, Jiahao Hu, Ziqi Song, Qing Li, Dian He, Hujun Jia |
A Low Jitter Current-Mode Multiplying Delay-Locked Loop Applied to High-Precision TDC. |
ASICON |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Paul Miqueu, Fabrice Belvèze, Jean-Marc Brossier, Laurent Ros |
Bit error probability of a very high data rate, amplitude modulated, communication system affected by timing jitter. |
ICSPCS |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Amir Mahdi Ajoodani, Mohammadreza Ghafari, Emma Dennis-Knieriem |
SDGC: Software Defined Game Clustering for Jitter Optimization. |
CSICC |
2023 |
DBLP DOI BibTeX RDF |
|
12 | J. L. Shreya, Anu Saini |
Delay Analysis in Programmable Data Plane Using Jitter Calculations. |
IC3 |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Chi-An Tsai, Pei-Jun Lee, Trong-An Bui, Guo-Cheng Xu, Meng-Lieh Sheu |
Moving Object Detection for Remote Sensing Video with Satellite Jitter. |
ICCE |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Panagiotis J. Gripeos, Hector E. Nistazakis, Efstratios C. Kapotis, E. V. Chatzikontis, Athanassios Katsis, Vasilis Christofilakis |
Numerical Validation of Analytical Results for FSO Links with Chromatic Dispersion and Normally Distributed Time Jitter. |
MOCAST |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Simone Mattia Dartizio |
Design of small-footprint, high-spectral purity and low-jitter digitally-intensive frequency synthetizers |
|
2023 |
RDF |
|
12 | Suneui Park, Seojin Choi, Seyeon Yoo, Yoonseo Cho, Jaehyouk Choi |
An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector. |
IEEE J. Solid State Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Hyojun Kim, Woosong Jung, Kwandong Kim, Sungwoo Kim, Woo-Seok Choi, Deog-Kyoon Jeong |
A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation. |
IEEE J. Solid State Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Chanwoong Hwang, Hangi Park, Yongsun Lee, Taeho Seong, Jaehyouk Choi |
A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM. |
IEEE J. Solid State Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Hangi Park, Chanwoong Hwang, Taeho Seong, Jaehyouk Choi |
A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. |
IEEE J. Solid State Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Ahmed Elmallah, Junheng Zhu, Amr Khashaba, Karim M. Megawer, Ahmed Elkholy, Pavan Kumar Hanumolu |
A 3.2-GHz 405 fsrms Jitter -237.2 dB FoMJIT Ring-Based Fractional-N Synthesizer. |
IEEE J. Solid State Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Mario Mercandelli, Alessio Santiccioli, Angelo Parisi, Luca Bertulessi, Dmytro Cherniak, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino |
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter. |
IEEE J. Solid State Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino |
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. |
IEEE J. Solid State Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Guanrong Hou, Behzad Razavi |
A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance. |
IEEE J. Solid State Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Younghyun Lim, Juyeop Kim, Yongwoo Jo, Jooeun Bang, Jaehyouk Choi |
A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop. |
IEEE J. Solid State Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Jiang Gong, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie |
A Low-Jitter and Low-Spur Charge-Sampling PLL. |
IEEE J. Solid State Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Yue Chen, Jiang Gong, Robert Bogdan Staszewski, Masoud Babaie |
A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and pp Supply Ripple. |
IEEE J. Solid State Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Shijie Liu, Han Zhang, Xiaohua Tong, Zhen Ye, Huan Xie, Feng Lin |
Effect of the Matching Window Size and TDI Stage Number on Image-Based Satellite Jitter Detection. |
IEEE Geosci. Remote. Sens. Lett. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Ping Yang, Lili Dong, He Xu, Hao Dai, Wenhai Xu |
Robust Infrared Maritime Target Detection via Anti-Jitter Spatial-Temporal Trajectory Consistency. |
IEEE Geosci. Remote. Sens. Lett. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Ying Zhu 0002, Tingting Yang, Mi Wang, Hanyu Hong, Yaozong Zhang, Lei Wang 0068, Qilong Rao |
Jitter Detection Method Based on Sequence CMOS Images Captured by Rolling Shutter Mode for High-Resolution Remote Sensing Satellite. |
Remote. Sens. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Dongdong Ma, Lili Dong, Wenhai Xu |
Detecting Maritime Infrared Targets in Harsh Environment by Improved Visual Attention Model Preselector and Anti-Jitter Spatiotemporal Filter Discriminator. |
Remote. Sens. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Eli Pale-Ramon, Jorge Ortega-Contreras, Karen Uribe-Murcia, Yuriy S. Shmaliy |
Effect of sampling time jitter on robust H2 filtering estimates. |
Signal Process. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Woorham Bae |
Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures. |
IEEE Access |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Dara Ron, Jung-Ryun Lee |
Reinforcement Learning-Based Power-Saving Algorithm for Video Traffics Considering Network Delay Jitter. |
IEEE Access |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Dong-Hyun Yoon, Dong-Kyu Jung, Kiho Seong, Jae-Soub Han, Keun-Yong Chung, Ju Eon Kim, Tony Tae-Hyoung Kim, Kwang-Hyun Baek |
A 3.2-GHz 178-fsrms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier. |
IEEE Trans. Very Large Scale Integr. Syst. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Jinhai Xiao, Ning Liang, Bingwen Chen, Maliang Liu |
An 8.55-17.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fsrms Jitter and Fast Frequency Hopping. |
IEEE Trans. Very Large Scale Integr. Syst. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Tailong Xu, Shenke Zhong, Jun Yin 0001, Pui-In Mak, Rui Paulo Martins |
A 6-to-7.5-GHz 54-fsrms Jitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Yueduo Liu, Rongxin Bao, Zihao Zhu, Shiheng Yang, Xiong Zhou, Jun Yin 0001, Pui-In Mak, Qiang Li 0021 |
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Mohammad Oveisi, Payam Heydari |
A Study of BER and EVM Degradation in Digital Modulation Schemes Due to PLL Jitter and Communication-Link Noise. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Yuan Cheng Qian, Yen-Yu Chao, Shen-Iuan Liu |
A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL. |
IEEE Trans. Circuits Syst. II Express Briefs |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Lalit Mohan Dani, Neeraj Mishra, Bulusu Anand |
A Variation Aware Jitter Estimation Methodology in ROs Considering Over/Undershoots in NTV Regime. |
IEEE Trans. Circuits Syst. II Express Briefs |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Jaya Deepthi Bandarupalli, Saurabh Saxena |
A 2.5-5.0-GHz Clock Multiplier With 3.2-4.5-mUIrms Jitter and 0.98-1.06 mW/GHz in 65-nm CMOS. |
IEEE Trans. Circuits Syst. II Express Briefs |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Wei-Ming Chen, Yun-Sheng Yao, Shen-Iuan Liu |
A 20-Gb/s Jitter-Tolerance-Enhanced Digital CDR With One-Tap DFE. |
IEEE Trans. Circuits Syst. II Express Briefs |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski |
Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial. |
IEEE Trans. Circuits Syst. II Express Briefs |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Jing Wang, Jiachen Qian, Jue Wang 0006, Ruifeng Gao, Yingdong Hu, Ye Li 0004, Wei Feng 0001 |
UAV Jitter May Have Merit: A Fading Analysis in Air-to-Sea Two Ray Channels. |
IEEE Wirel. Commun. Lett. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Theodore T. Kapsis, Athanasios D. Panagopoulos |
Robust Power Allocation in Optical Satellite MIMO Links With Pointing Jitter. |
IEEE Wirel. Commun. Lett. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Eulalia Balestrieri, Luca De Vito, Francesco Lamonaca, Francesco Picariello, Sergio Rapuano, Ioan Tudosa |
The Jitter Measurement Ways: The Instrumentation. |
IEEE Instrum. Meas. Mag. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Hao Yu 0013, Tarik Taleb, Jiawei Zhang 0004 |
Deterministic Latency/Jitter-Aware Service Function Chaining Over Beyond 5G Edge Fabric. |
IEEE Trans. Netw. Serv. Manag. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Shuxiang Song, Zefa Liu, Mingcan Cen, Chaobo Cai |
A 9.8-12.5 Gb/s Low-Jitter Reference-Less Clock and Data Recovery Circuit. |
J. Circuits Syst. Comput. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Jyoti Sharma, Gaurav Kumar Sharma, Tarun Varma, Dharmendar Boolchandani |
A High Speed Phase Detection Circuit with No Dead Zone Suitable for Minimal Jitter and Low Power Applications. |
J. Circuits Syst. Comput. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal |
A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator. |
Int. J. Circuit Theory Appl. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Mohammad Bagheri, Xun Li |
An ultra-low power and low jitter frequency synthesizer for 5G wireless communication and IoE applications. |
Int. J. Circuit Theory Appl. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Tianxiang Wu, Xi Wang, Yong Chen 0005, Junyan Ren, Shunli Ma |
A 10-MHz to 50-GHz low-jitter multiphase clock generator for high-speed oscilloscope in 0.15-μm GaAs technology. |
Int. J. Circuit Theory Appl. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Christopher Hidey, Fei Liu, Rahul Goel |
Reducing Model Jitter: Stable Re-training of Semantic Parsers in Production Environments. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Jithin Kallukalam Sojan, K. Haribabu 0001 |
Monitoring Jitter in Software Defined Networks. |
CoRR |
2022 |
DBLP BibTeX RDF |
|
12 | Ruicong Liu, Yiwei Bao, Mingjie Xu, Haofei Wang, Yunfei Liu, Feng Lu 0005 |
Jitter Does Matter: Adapting Gaze Estimation to New Domains. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Simone Zini, Marco Buzzelli, Bartlomiej Twardowski, Joost van de Weijer 0001 |
Planckian jitter: enhancing the color quality of self-supervised visual representations. |
CoRR |
2022 |
DBLP BibTeX RDF |
|
12 | Armando Malanda, Daniel W. Stashuk, Javier Navallas-Irujo, Javier Rodríguez-Falces, Ignacio Rodríguez-Carreño, César Valle, Oscar Garnés-Camarena |
Automatic jitter measurement in needle-detected motor unit potential trains. |
Comput. Biol. Medicine |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Adriaan Peetermans, Ingrid Verbauwhede |
An energy and area efficient, all digital entropy source compatible with modern standards based on jitter pipelining. |
IACR Trans. Cryptogr. Hardw. Embed. Syst. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | David S. Citrin |
Photonic Sampling Analog-to-Digital Conversion With Read-In Timing Jitter. |
IEEE Trans. Commun. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Wei-Hao Chen, Shi-Yu Huang |
On-Chip Jitter Learning for PLL. |
IEEE Des. Test |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Malek Souilem, Rui Melício, Wael Dghais, Belgacem Hamdi, Eduardo Rodrigues 0001 |
Analysis of Pre-Driver and Last-Stage Power - Ground-Induced Jitter at Different PVT Corners. |
Sensors |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Liang Guo, Guohao Ju, Boqian Xu, Xiaoquan Bai, Qingyu Meng, Fengyi Jiang, Shuyan Xu |
Jitter-Robust Phase Retrieval Wavefront Sensing Algorithms. |
Sensors |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Jiyun Tong, Sha Wang, Shuang Zhang, Mengdi Zhang, Ye Zhao, Fazhan Zhao |
A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC. |
Sensors |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Megha Sahu, Sri Pramodh Rachuri, Ahtisham Ali Ansari, Arzad Alam Kherani |
Traffic splitting for delay jitter control in multi-access systems. |
Telecommun. Syst. |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Chengxian Pan, Chunqi Shi, Guoliang Zhao, Boxiao Liu, Leilei Huang, Runxi Zhang |
A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO. |
IEICE Electron. Express |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Sheng Xie, Chengkui Jia, Luhong Mao, Gaolei Zhou, Naibo Zhang, Ruiliang Song |
Low jitter design for quarter-rate CDR of 100Gb/s PAM4 optical receiver. |
IEICE Electron. Express |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Esteban Carisimo, Ricky K. P. Mok, David D. Clark, Kimberly C. Claffy |
Jitterbug: A New Framework for Jitter-Based Congestion Inference. |
PAM |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Daniel Bujosa, Mohammad Ashjaei, Alessandro V. Papadopoulos, Thomas Nolte, Julián Proenza |
HERMES: Heuristic Multi-queue Scheduler for TSN Time-Triggered Traffic with Zero Reception Jitter Capabilities. |
RTNS |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán |
A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology. |
VLSI-SoC |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Alexej Grigorjew, Florian Metzger, Tobias Hoßfeld, Johannes Specht, Franz-Josef Götz, Feng Chen 0012, Jürgen Schmitt |
Constant Delay Switching: Asynchronous Traffic Shaping with Jitter Control. |
IFIP Networking |
2022 |
DBLP DOI BibTeX RDF |
|
12 | James P. Wilmott, Ian M. Erkelens, T. Scott Murdison, Kevin W. Rio |
Perceptibility of Jitter in Augmented Reality Head-Mounted Displays. |
ISMAR |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Licinius Benea, M. Carmona, Florian Pebay-Peyroula, R. Wacquez |
On the Characterization of Jitter in Ring Oscillators using Allan variance for True Random Number Generator Applications. |
DSD |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Arturo Mollinedo Garay, Florent Bernard, Viktor Fischer, Patrick Haddad, Ugo Mureddu |
An Evaluation Procedure for Comparing Clock Jitter Measurement Methods. |
CARDIS |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Zerong Ren, Wei Cheng, Yong Li 0036, Xiang Gao |
The Effect of Clock Jitter on Azimuth of DVOR and the Compensation Method. |
ICCT |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Yushi Koyasako, Tomoya Hatano, Takashi Yamada, Tatsuya Shimada, Tomoaki Yoshida |
Demonstration of Real-Time Jitter Buffered Architecture for Motion Control in All-Photonics Network. |
GLOBECOM |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Wenbo Guo 0001, Haotian Hu, Yimin He, Mu Yan, Hongzhi Zhao, Shihai Shao |
Impacts of Clock Jitter on Cooperative Jamming Cancellation. |
GLOBECOM |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Anan Sawabe, Yusuke Shinohara, Takanori Iwai |
Delay Jitter Modeling for Low-Latency Wireless Communications in Mobility Scenarios. |
GLOBECOM |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Jiahao Hu, Zhongxian Huang, Baoxing Duan, Qing Li, Ziqi Song, Dian He |
A Multiplying Delay-Locked Loop design with low jitter and high linearity. |
ICTA |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Jin Woong Kwak, Dongsheng Brian Ma |
An Automotive-Use Dual-fsw-Zone Hybrid Switching Power Converter with Vo-Jitter-Immune Spread-Spectrum Modulation. |
ESSCIRC |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Staffan Ek, Patrik Karlsson, Andreas Kämpe, Roland Strandberg, Aravind Tharayil Narayanan, Martin Anderson, Hind Dafallah, Mesrop Daghbashyan, Tayebeh Ghanavati Nejad, Robert Hägglund, Nikola Ivanisevic, Robert Nilsson, Peter Nygren, Mattias Palm, Erik Säll, Sha Tao, My-Chien Yee, Lars Sundström |
A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET Technology. |
ESSCIRC |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Haopeng Wang, Shuixing Pan, Dilong Li, Yueqiang Zhang, Linyu Huang, Hongxi Guo, Xiaolin Liu, Qifeng Yu |
JFT: A Robust Visual Tracker Based on Jitter Factor and Global Registration. |
PRCV (4) |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Jialun Liu, Wenhui Li 0002, Yifan Sun 0003 |
Memory-Based Jitter: Improving Visual Recognition on Long-Tailed Data with Diversity in Memory. |
AAAI |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Lukas Wüsteney, David Hellmanns, Markus Schramm, Lukas Osswald, René Hummen, Michael Menth, Tobias Heer |
Analyzing and modeling the latency and jitter behavior of mixed industrial TSN and DetNet networks. |
CoNEXT |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka |
A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter. |
VLSI Technology and Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Wei-Jhih Jian, Wei-Zen Chen |
A Reference-Free Phase Noise Measurement Circuit Achieving 24.2 fs Periodic Jitter Sensitivity and 275 fsrms Resolution with Background Self-Calibration. |
VLSI Technology and Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Masayuki Makino, Yuta Kaihori, Tsuyoshi Konishi |
Timing jitter suppression below 100 fs in photonic frequency band migration from MHz to GHz for Millimeter-wave Band Arbitrary Waveform Generation. |
OECC/PSC |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Kenji Miyamoto, Yoshihito Sakai, Tatsuya Shimada, Tomoaki Yoshida |
Mobile Backhaul Uplink Jitter Reduction Techniques with Optical-Wireless Cooperative Control. |
OECC/PSC |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Andrea Bevilacqua, Luca Bertulessi, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino |
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. |
CICC |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Yuanming Zhu, Julian Camilo Gomez Diaz, Srujan Kumar Kaile, II-Min Yi, Tong Liu, Sebastian Hoyos, Samuel Palermo |
A Jitter-Robust 40Gb/s ADC-Based Multicarrier Receiver Front End in 22nm FinFET. |
CICC |
2022 |
DBLP DOI BibTeX RDF |
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12 | Mingzhu Yin, Wei Wang 0213, Dongdong Zou, Limin Rong, Fan Li 0011, Xingwen Yi, Zhaohui Li |
High-speed Signal Transmission Using Low-resolution DAC with Jitter-aware Noise Shaping Technique. |
ICCC |
2022 |
DBLP DOI BibTeX RDF |
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12 | Alexandre Berthier, Anthony Ghiotto, Eric Kerherve, Lionel Vogt |
60 GHz SIW Filter with 1.7 dB of Insertion Loss and 7 ps Added Jitter on OOK Modulated Signal. |
RWS |
2022 |
DBLP DOI BibTeX RDF |
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12 | Xinlin Geng, Yibo Tian, Yao Xiao, Zonglin Ye, Qian Xie, Zheng Wang 0050 |
A 25.8GHz Integer-N PLL With Time-Amplifying Phase-Frequency Detector Achieving 60fsrms Jitter, -252.8dB FoMJ, and Robust Lock Acquisition Performance. |
ISSCC |
2022 |
DBLP DOI BibTeX RDF |
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12 | Wei-Hao Sun, Shih-Hsiung Chien, Tai-Haur Kuo |
A 121dB DR, 0.0017% THD+N, 8× Jitter-Effect Reduction Digital-Input Class-D Audio Amplifier with Supply-Voltage-Scaling Volume Control and Series-Connected DSM. |
ISSCC |
2022 |
DBLP DOI BibTeX RDF |
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12 | Yu Zhao, Onur Memioglu, Behzad Razavi |
A 56GHz 23mW Fractional-N PLL with 110fs Jitter. |
ISSCC |
2022 |
DBLP DOI BibTeX RDF |
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12 | Yeonwook Jung, Seongseop Lee, Hyojun Kim, SeongHwan Cho |
A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter. |
ISSCC |
2022 |
DBLP DOI BibTeX RDF |
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12 | Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu, Ya-Tin Chang, Chih-Hsien Chang, Robert Bogdan Staszewski |
A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur. |
ISSCC |
2022 |
DBLP DOI BibTeX RDF |
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12 | Suneui Park, Seyeon Yoo, Yuhwan Shin, Jeonghyun Lee, Jaehyouk Choi |
A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator. |
ISSCC |
2022 |
DBLP DOI BibTeX RDF |
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