Search results for "processor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Robert Simon Sherratt, Kai Zhang, Owen J. Wilkes	Improving CS-4 User Data Rate in GPRS Enabled Devices by Using a BLER Co-processor.	Int. J. Wirel. Inf. Networks	2006	DBLP DOI BibTeX RDF	Application data rate, IP transport, FPGA, GPRS, co-processor
18	Li Zhao 0002, Yan Luo, Laxmi N. Bhuyan, Ravi R. Iyer 0001	A Network Processor-Based, Content-Aware Switch.	IEEE Micro	2006	DBLP DOI BibTeX RDF	content-aware switch, ENP2611, Intel IXP 2400, network processor
18	Sem C. Borst, Rudesindo Núñez-Queija, Bert Zwart	Sojourn time asymptotics in processor-sharing queues.	Queueing Syst. Theory Appl.	2006	DBLP DOI BibTeX RDF	Bandwidth-sharing networks, Reduced service rate approximation, Light-tailed distributions, Large deviations, Processor sharing, Heavy-tailed distributions, Tail asymptotics
18	Krzysztof Debicki, Miranda van Uitert	Large buffer asymptotics for generalized processor sharing queues with Gaussian inputs.	Queueing Syst. Theory Appl.	2006	DBLP DOI BibTeX RDF	Large-buffer asymptotics, Gaussian traffic, Communication networks, Differentiated services, Generalized processor sharing
18	Lisa Higham, Jalal Kawash	Tight Bounds for Critical Sections in Processor Consistent Platforms.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	processor consistency, multiwriter/single-writer variables, mutual exclusion, Memory consistency models
18	Alexey L. Lastovetsky, Ravi Reddy, Robert Higgins	Building the functional performance model of a processor.	SAC	2006	DBLP DOI BibTeX RDF	grid computing, parallel computing, distributed computing, performance modeling, memory hierarchy, heterogeneous computing, processor performance
18	Nan Wu 0003, Mei Wen, Ju Ren 0002, Yi He 0008, Chunyuan Zhang	Register Allocation on Stream Processor with Local Register File.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	local register file, spilling, register allocation, VLIW, stream processor
18	Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi, Li Jing	High-level synthesis challenges and solutions for a dynamically reconfigurable processor.	ICCAD	2006	DBLP DOI BibTeX RDF	high-level synthesis, dynamic reconfiguration, reconfigurable processor
18	Cheng Xu 0001, Fei Yu 0001, Zhenghui Dai, Guangxue Yue, Renfa Li	Data Distribution Algorithm of High-Speed Intrusion Detection system Based on Network Processor.	SKG	2006	DBLP DOI BibTeX RDF	Data Distribution Algorithm, Intrusion Detection, Network Processor, Protocol analysis
18	Samuel Williams 0001, John Shalf, Leonid Oliker, Shoaib Kamil 0001, Parry Husbands, Katherine A. Yelick	The potential of the cell processor for scientific computing.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	GEMM, SpMV, three level memory, FFT, sparse matrix, cell processor, stencil
18	Xianghui Hu, Xinan Tang, Bei Hua	High-performance IPv6 forwarding algorithm for multi-core and multithreaded network processor.	PPoPP	2006	DBLP DOI BibTeX RDF	IPv6 forwarding, parallel programming, pipelining, multithreading, network processor, table lookup, thread-level parallelism
18	Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee	A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy.	DAC	2006	DBLP DOI BibTeX RDF	processor-memory, VLSI, performance modeling, three dimensional, 3D ICs, vertical integration, thermal analysis
18	Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro	VIRTUS: a new processor virtualization architecture for security-oriented next-generation mobile terminals.	DAC	2006	DBLP DOI BibTeX RDF	processor virtualization, multiprocessor
18	Kanna Shimizu, Sanjay Gupta, Tatsuya Koyama, Takashi Omizo, Jamee Abdulhafiz, Larry McConville, Todd Swanson	Verification of the cell broadband engineTM processor.	DAC	2006	DBLP DOI BibTeX RDF	directed random verification, processor reference model, trace-based verification, hierarchical verification
18	Daniel L. Stasiak, Rajat Chaudhry, Dennis Cox, Stephen D. Posluszny, James D. Warnock, Steve Weitzel, Dieter F. Wendel, Michael Wang 0001	Cell Processor Low-Power Design Methodology.	IEEE Micro	2005	DBLP DOI BibTeX RDF	VLSI, design methodology, Cell processor, low power consumption
18	Masahiro Sowa, Ben A. Abderazek, Tsutomu Yoshinaga	Parallel Queue Processor Architecture Based on Produced Order Computation Model.	J. Supercomput.	2005	DBLP DOI BibTeX RDF	produced order, queue processor, circular queue-registers, design, high performance
18	Bruno Sericola, Fabrice Guillemin, Jacqueline Boyer	Sojourn Times in the M/PH/1 Processor Sharing Queue.	Queueing Syst. Theory Appl.	2005	DBLP DOI BibTeX RDF	processor sharing discipline, asymptotic estimates, sojourn time, phase type distribution
18	Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown	Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	optimization, Code generation, low-power design, graph partitioning, embedded processor, retargetable compilers, spill code, instruction encoding, register window
18	Chu Chao, Qin Zhang, Yingke Xie, Chengde Han	Design of a high performance FFT processor based on FPGA.	ASP-DAC	2005	DBLP DOI BibTeX RDF	FFT processor, overflow control, FPGA, address generation
18	Suman Mamidi, Emily R. Blem, Michael J. Schulte, C. John Glossner, Daniel Iancu, Andrei Iancu, Mayan Moudgill, Sanjay Jinturkar	Instruction set extensions for software defined radio on a multithreaded processor.	CASES	2005	DBLP DOI BibTeX RDF	convolutional encoding, multithreading, forward error correction, software defined radio, Reed-Solomon coding, instruction set extensions, digital signal processor, Viterbi decoding, turbo decoding
18	Marco Lanuzza, Martin Margala, Pasquale Corsonello	Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications.	ISLPED	2005	DBLP DOI BibTeX RDF	reconfigurable computing, datapath, processor-in-memory
18	Kevin K. Leung, Du Zhang	Animation of Linux Processor Scheduling Algorithm.	ISM	2005	DBLP DOI BibTeX RDF	Linux processor scheduling, animation of scheduling algorithm, /proc pseudo file system
18	Oliver Sinnen, Leonel Sousa	Task Scheduling: Considering the Processor Involvement in Communication.	ISPDC/HeteroPar	2004	DBLP DOI BibTeX RDF	processor involvement, Parallel programming, task scheduling, contention, system models
18	A. S. Nepomniaschaya, Zbigniew Kokosinski	Associative Graph Processor and Its Properties.	PARELEC	2004	DBLP DOI BibTeX RDF	associative parallel processor, bit-parallel processing, associative graph processing, multiple-search
18	Daniel J. Deleganes, Micah Barany, George L. Geannopoulos, Kurt Kreitzer, Anant P. Singh, Sapumal B. Wijeratne	Low voltage swing logic circuits for a Pentium 4 processor integer core.	DAC	2004	DBLP DOI BibTeX RDF	LVS, Pentium® 4 processor, integer core, low voltage swing, sense-amp, microprocessor, rotator, adder
18	Michael L. Behm, John M. Ludden, Yossi Lichtenstein, Michal Rimon, Michael Vinov	Industrial experience with test generation languages for processor verification.	DAC	2004	DBLP DOI BibTeX RDF	test generation, functional verification, processor verification
18	Ravi Hosabettu, Ganesh Gopalakrishnan, Mandayam K. Srivas	Formal Verification of a Complex Pipelined Processor.	Formal Methods Syst. Des.	2003	DBLP DOI BibTeX RDF	completion functions, formal verification, PVS, processor verification
18	Sem C. Borst, Michel Mandjes, Miranda van Uitert	Generalized processor sharing with light-tailed and heavy-tailed input.	IEEE/ACM Trans. Netw.	2003	DBLP DOI BibTeX RDF	Markov fluid, heavy-tailed traffic, light-tailed traffic, weighted fair queueing, workload asymptotics, large deviations, Generalized processor sharing (GPS), regular variation
18	Ville Lappalainen, Antti Hallapuro, Timo D. Hämäläinen	Performance of H.26L Video Encoder on General-Purpose Processor.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	H.263+, H.26L, video encoder, H.263, general-purpose processor
18	Robert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David T. Blaauw	An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages.	ISVLSI	2003	DBLP DOI BibTeX RDF	ARM processor, Low power design, CVS, Dual-Vt
18	Sylvain Girbal, Gilles Mouchard, Albert Cohen 0001, Olivier Temam	DiST: a simple, reliable and scalable method to significantly reduce processor architecture simulation time.	SIGMETRICS	2003	DBLP DOI BibTeX RDF	distributed simulation, processor architecture
18	Wei Ming Lim, Mohammed Benaissa	Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and cryptography.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	GF(2m) arithmetic, forward error control coding, galois field processor, cryptography, advanced encryption standard, elliptic curve cryptography, design space exploration, Reed-Solomon code, hardware-software co-design, BCH code
18	Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown	Increasing the number of effective registers in a low-power processor using a windowed register file.	CASES	2003	DBLP DOI BibTeX RDF	window assignment, low-power, graph partitioning, embedded processor, instruction encoding, register window
18	Vadali Srinivasa Murty, P. C. Reghu Raj, S. Raman 0001	Design of a high speed string matching co-processor for NLP.	VLSI Design	2003	DBLP DOI BibTeX RDF	Memory interleaving, NLP co-processor, Perfect match, Approximate match
18	Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama	High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph.	ISVLSI	2002	DBLP DOI BibTeX RDF	FPGA, Reconfigurable processor, Two-dimensional array, Bit-serial architecture
18	Eckhard Grass, Bodhisatya Sarker, Koushik Maharatna	A Dual-Mode Synchronous/Asynchronous CORDIC Processor.	ASYNC	2002	DBLP DOI BibTeX RDF	CORDIC processor, dual-mode, synchronous, asynchronous, self-timed
18	Sanjay V. Rajopadhye, Steven Derrien	Energy/Power Estimation of Regular Processor Arrays.	ISSS	2002	DBLP DOI BibTeX RDF	processor array partitioning, design space exploration, power estimation, programmable logic
18	Sungbae Hwang, Jacob A. Abraham	Selective-run built-in self-test using an embedded processor.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	processor-based testing, built-in self-test, design for testability, SOC testing, pseudo-random number generator
18	Victor Varshavsky, Vyacheslav Marakhovsky	GALA Approach in Design of Asynchronous Control for Counterflow Pipeline Processor.	DELTA	2002	DBLP DOI BibTeX RDF	GALA - Globally Asynchronous Locally Arbitrary, Counterflow Pipeline Processor, Synchronous Prototype, Arbitration, Asynchronous Design
18	Kevin T. Pedretti, Ron Brightwell, Joshua Williams	Cplant? Runtime System Support for Multi-Processor and Heterogeneous Compute Nodes.	CLUSTER	2002	DBLP DOI BibTeX RDF	heterogeneous computing, runtime system, multi-processor, commodity cluster
18	Randal E. Bryant, Steven M. German, Miroslav N. Velev	Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic.	ACM Trans. Comput. Log.	2001	DBLP DOI BibTeX RDF	processor verfication, decision procedures, uninterpreted functions
18	Yomin Hou, Chien-Min Wang, Chiu-Yu Ku, Lih-Hsing Hsu	Optimal Processor Mapping for Linear-Complement Communication on Hypercubes.	IEEE Trans. Parallel Distributed Syst.	2001	DBLP DOI BibTeX RDF	linear-complement communication, channel contention, Hypercubes, wormhole routing, processor mapping
18	David R. Martinez, Tyler J. Moeller, Ken Teitelbaum	Application of Reconfigurable Computing to a High Performance Front-End Radar Signal Processor.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	VLSI rader signal processor, front end high performance filtering, digital filtering mapped to reconfigurable computing, commercial FPGA hardware, reconfigurable hardware
18	Chunho Lee, Johnson Kin, Miodrag Potkonjak, William H. Mangione-Smith	Exploring Hypermedia Processor Design Space.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	hypermedia processor, synthesis framework, instruction-level parallelism, workload characterization
18	Eric Schnarr, Mark D. Hill, James R. Larus	Facile: A Language and Compiler for High-Performance Processor Simulators.	PLDI	2001	DBLP DOI BibTeX RDF	micro-architecture simulation, out-of-order processor simulation, partial evaluation, memoization
18	Mark N. Yankelevsky, Constantine D. Polychronopoulos	alpha-coral: a multigrain, multithreaded processor architecture.	ICS	2001	DBLP DOI BibTeX RDF	processor archietecture, multithreaded, parallelizing compiler
18	Bruce Greer, John Harrison 0001, Greg Henry, Wei Wayne Li, Ping Tak Peter Tang	Scientific computing on the Itanium processor.	SC	2001	DBLP DOI BibTeX RDF	fused multiply-add, itanium (TM) processor, linear algebra, Intel, EPIC, transcendental functions
18	Guoping Liu 0004, Kyungsook Y. Lee, Harry F. Jordan	n-Dimensional Processor Arrays with Optical dBuses.	J. Supercomput.	2000	DBLP DOI BibTeX RDF	de Bruijn digraph, wavelength division multiplexing, optical interconnections, processor array, time division multiplexing
18	Po-Jen Chuang, Chih-Ming Wu	An Efficient Recognition-Complete Processor Allocation Strategy for k-ary n-cube Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	Full subcube recognition, internal and external fragmentation, k-ary n-cube multiprocessors, performance evaluation, time complexity, processor allocation
18	Hyunseung Choo, Seong-Moo Yoo, Hee Yong Youn	Processor Scheduling and Allocation for 3D Torus Multicomputer Systems.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	Best-fit and first-fit approach, processor scheduling and allocation, 3D torus, multicomputer
18	Tadayoshi Horita, Itsuo Takanami	Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions.	ISPAN	1999	DBLP DOI BibTeX RDF	The 1 1/2-track switch model, wefer scale integration, reconfiguration, yield enhancement, mesh-connected processor arrays
18	Zhi-Li Zhang	Large deviations and the generalized processor sharing scheduling for a multiple-queue system.	Queueing Syst. Theory Appl.	1998	DBLP DOI BibTeX RDF	asymptotic decay rate, queue length tail distributions, generalized processor sharing, large deviation principles
18	Paul Dupuis, Kavita Ramanan	A Skorokhod Problem formulation and large deviation analysis of a processor sharing model.	Queueing Syst. Theory Appl.	1998	DBLP DOI BibTeX RDF	Skorokhod Problem, large deviation estimates, processor sharing
18	Eric Schnarr, James R. Larus	Fast Out-Of-Order Processor Simulation Using Memoization.	ASPLOS	1998	DBLP DOI BibTeX RDF	out-of-order processor simulation, memoization, direct-execution
18	Hong Chen, Offer Kella, Gideon Weiss	Fluid approximations for a processor-sharing queue.	Queueing Syst. Theory Appl.	1997	DBLP DOI BibTeX RDF	processor-sharing discipline, fluid approximation, functional strong law of large numbers, GI/G/1 queue
18	Kelvin K. Yue, David J. Lilja	An Effective Processor Allocation Strategy for Multiprogrammed Shared-Memory Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	Parallel loop scheduling, operating system, shared-memory multiprocessors, multiprogramming, processor allocation
18	Andrew Wolfe, Jason Fritts, Santanu Dutta, Edil S. T. Fernandes	Datapath Design for a VLIW Video Signal Processor.	HPCA	1997	DBLP DOI BibTeX RDF	datapath design, VLIW video signal processor, very long instruction word, high parallelism, high-level language programmability, high-bandwidth interconnect, high-connectivity register files, parameterizable versions, VLSI, video signal processing, VLIW architectures, compiler design
18	Juha Plosila, Kaisa Sere	Action Systems in Pipelined Processor Design.	ASYNC	1997	DBLP DOI BibTeX RDF	pipelined processor design, asynchronous pipelined microprocessors, hazard situations, verifying refinement steps, circuit implementation, speed-independent techniques, refinement calculus, refinement calculus, action systems
18	Zahari M. Darus, Iftekhar Ahmed 0003, Liakot Ali	A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	test processor chip, multiple polynomial linear feedback shift register, ASIC chip, scan-path testing, external IC tester, simulation, fault coverage, shift registers, pattern generator, multiple seed
18	Michiko Inoue, Sen Moriya, Toshimitsu Masuzawa, Hideo Fujiwara	Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System.	WDAG	1997	DBLP DOI BibTeX RDF	shared-memory multi-processor system, napping fault, fault-tolerance, clock-synchronization, wait-freedom
18	Hea-Sook Park, Sung-Jin Moon, Man-Sik Park, Boseob Kwon, Kwang-Suk Song	Design of inter processor communication controller using ATM switch and analysis of its optimal message length considering retransmission.	RTCSA	1997	DBLP DOI BibTeX RDF	inter processor communication controller, optimal message length, distributed large-scale multiprocessors, ATM adaptation layer, message error rate, message retransmission rate, asynchronous transfer mode, ATM switch, asynchronous transfer mode switches
18	Fabio Ancona, Rodolfo Zunino	Optimal data allocation for processor-tree architectures.	EUROMICRO	1997	DBLP DOI BibTeX RDF	optimal data allocation, processor-tree architectures, slice-based data-allocation strategy, data-distribution procedure, high-dimensional data processing, noise-like coding model, resource allocation, associative memory, neural network modeling, theoretical analysis
18	Hercule Kwan, Edward J. Powers, Earl E. Swartzlander Jr.	Realization of a nonlinear digital filter on a DSP array processor.	ASAP	1997	DBLP DOI BibTeX RDF	nonlinear digital filter, third-order Volterra digital filtering algorithm, AT&T DSP-3 parallel processor, nonlinear communication channel equalization, 64-QAM signal constellation, performance evaluation, digital signal processing chips, time-skewing
18	Po-Jen Chuang, Chih-Ming Wu	Processor Allocation in k-ary n-cube Multiprocessors.	ISPAN	1997	DBLP DOI BibTeX RDF	Full subcube recognition, internal and external fragmentations, k-ary n-cube multiprocessors, performance evaluation, processor allocation
18	Josep Lluís Larriba-Pey, Daniel Jiménez-González, Juan J. Navarro	An Analysis of Superscalar Sorting Algorithms on an R8000 Processor.	SCCC	1997	DBLP DOI BibTeX RDF	superscalar sorting algorithms, R8000 processor, in-memory sorting algorithms, Quick sort, Heap sort, Multiway merge, parallel algorithms, locality, superscalar architectures, Radix sort, Bucket sort
18	Hee Yong Youn, Jae Young Lee	An Efficient Dictionary Machine Using Hexagonal Processor Arrays.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	edge disjoint embedding, update and query, processor array, hexagonal mesh, Dictionary machine
18	Winfried Grünewald, Theo Ungerer	Towards Extremely Fast Context Switching in a Block-Multithreaded Processor.	EUROMICRO	1996	DBLP DOI BibTeX RDF	extremely fast context switching, block-multithreaded processor, fast context switch, Rhamma, off-chip cache, workstation environment, memory cycle time, latencies, synchronisation, memory accesses, functional unit, synchronization operations
18	Hylke W. van Dijk, Gerben J. Hekstra, Ed F. Deprettere	Jacobi-Specific Processor Arrays.	ASAP	1996	DBLP DOI BibTeX RDF	Jacobi-specific processor arrays, Jacobi algorithms, array implementations prototyping, adaptive matrix QR decomposition, compiler, program compilers, software prototyping, Jacobian matrices
18	Jürgen Teich, Lothar Thiele, Li Zhang 0036	Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources.	ASAP	1996	DBLP DOI BibTeX RDF	Scheduling, Partitioning, Processor Arrays
18	Jens Braband	Waiting time distributions for closed M/M/N processor sharing queues.	Queueing Syst. Theory Appl.	1995	DBLP DOI BibTeX RDF	multiple server queues, central server model, numerical inversion, Processor sharing, Laplace transforms, waiting time distributions
18	Stefan Tschöke, Reinhard Lüling, Burkhard Monien	Solving the traveling salesman problem with a distributed branch-and-bound algorithm on a 1024 processor network.	IPPS	1995	DBLP DOI BibTeX RDF	distributed branch-and-bound algorithm, 1024 processor network, 1-tree relaxation, direct-neighbor dynamic load-balancing strategy, parallel algorithms, parallelization, travelling salesman problems, travelling salesman problem, massively parallel computer, sequential algorithm
18	Yasuhiro Kokusho, Norihisa Doi	Scheduling hard-realtime parallel tasks onto the processor network with wrapped mesh topology.	RTCSA	1995	DBLP DOI BibTeX RDF	realtime parallel tasks, wrapped mesh topology, load-distribution mechanism, Double-Layered Load-Distribution, DLLD, scheduling, real-time systems, parallel processing, parallel computing, resource allocation, multiprocessing systems, multiprocessor systems, processor scheduling
18	Young-Joon Kim, Seong-Whan Lee, Myung-Won Kim	Parallel hardware implementation of handwritten character recognition system on wavefront array processor architecture.	ICDAR	1995	DBLP DOI BibTeX RDF	character recognition equipment, parallel hardware, wavefront array processor, unconstrained handwritten numerals, parallel architectures, character recognition, handwriting recognition, image classification, neural nets, clock skew, handwritten character recognition, neural network classifier
18	Phill-Kyu Rhee, T. Fujisaki	Intelligent document assistant processor for pen-based computing systems.	ICDAR	1995	DBLP DOI BibTeX RDF	pen-based computing systems, IDAP, Intelligent Document Assistant Processor, roughly drawn documents, neat documents, H-COS, intelligent user interface, document handling
18	Alok N. Choudhary, Bhagirath Narahari, David M. Nicol, Rahul Simha	Optimal Processor Assignment for a Class of Pipelined Computations.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	multitasked parallel architectures, processor assignment problem, series-parallel partial order, parallel analysis, task structure, series-parallel task system, series analysis, computer vision, resource allocation, parallel architectures, data dependencies, pipeline processing, data sets, pipelined computations
18	Brian M. Carlson, Lawrence W. Dowdy	Static Processor Allocation in a Soft Real-Time Multiprocessor Environment.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	static processor allocation, soft real-time multiprocessor environment, parallelenvironment, static allocation policies, equal partitions, two partitions, 16-node iPSC/2hypercube, real-time systems, resource allocation, hypercube networks, multiprocessing programs
18	Zicheng Guo, Rami G. Melhem	Embedding Binary X-Trees and Pyramids in Processor Arrays with Spanning Buses.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	binaryX-trees, spanning buses, 2-D arrayarchitectures, routing step, parallel architectures, multiprocessor interconnection networks, embedding, network routing, binary trees, processor arrays, pyramids, network embeddings
18	M. Yu. Kitaev	The M/G/1 processor-sharing model: transient behavior.	Queueing Syst. Theory Appl.	1993	DBLP DOI BibTeX RDF	virtual sojourn time distribution, marked point process, random measure, predictable projection, random time change, Processor-sharing, time-sharing, branching process, transient behavior
18	John A. Morrison	Head of the line processor sharing for many symmetric queues with finite capacity.	Queueing Syst. Theory Appl.	1993	DBLP DOI BibTeX RDF	head of the line processor sharing, many queues, loss probability, Asymptotics
18	Xiaoming Tan, Yongzhi (Peter) Yang, Charles Knessl	The conditional sojourn time distribution in the GI/M/1 processor-sharing queue in heavy traffic.	Queueing Syst. Theory Appl.	1993	DBLP DOI BibTeX RDF	processor-sharing, heavy traffic, sojourn time, Asymptotics
18	Myung Hoon Sunwoo, J. K. Aggarwal	A Sliding Memory Plane Array Processor.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	sliding memory, plane array processor, mesh-connected, single-input multiple-data, SliM, image processing, image processing, parallel architectures
18	Qing Yang 0001, Hong Wang 0003	A New Graph Approach to Minimizing Processor Fragmentation in Hypercube Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	graph approach, minimizing processor fragmentation, primecube graph, simulation, performance evaluation, multiprocessing systems, hypercube networks, digital simulation, hypercube multiprocessors
18	Charles Knessl	On the Sojourn Time Distribution in a Finite Capacity Processor Shared Queue.	J. ACM	1993	DBLP DOI BibTeX RDF	processor-sharing, sojourn times, asymptotics
18	Lionel C. Waring, Maurice Clint	Computation of the Eigenvalues of Real Symmetric Matrices Using a Processor Farm.	CONPAR	1992	DBLP DOI BibTeX RDF	orthogonalisation, processor farm, matrix multiplication, Linear algebra, Transputers, ring topology
18	Jong Kim 0001, Chita R. Das, Woei Lin	A Top-Down Processor Allocation Scheme for Hypercube Computers.	IEEE Trans. Parallel Distributed Syst.	1991	DBLP DOI BibTeX RDF	top-down processor allocation scheme, free list, bottom-upapproach, buddy allocation, timecomplexity, noncubic allocation, inclusion/exclusion allocation, parallel processing, hypercube networks, parallel implementation, gray code, average delay, hypercube computers, system utilization
18	Lorenz A. Schmitt, Stephen S. Wilson	The AIS-5000 Parallel Processor.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	AIS-5000, parallel memory organization, image-based algorithms, computer vision, computer vision, parallel architecture, parallel architectures, computerised picture processing, computerised picture processing, microprocessor chips, parallel processor, SIMD architecture
18	Olin H. Bray, Sperry Univac	Data Usage And The Data Base Processor.	ACM Annual Conference (1)	1978	DBLP DOI BibTeX RDF	Data base processor, Data base usage, Data management applications, Data base management systems
16	Chieh-Feng Chiang, Jimmy J. M. Tan	Using Node Diagnosability to Determine t-Diagnosability under the Comparison Diagnosis Model.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
16	Doruk Bozdag, Füsun Özgüner, Ümit V. Çatalyürek	Compaction of Schedules and a Two-Stage Approach for Duplication-Based DAG Scheduling.	IEEE Trans. Parallel Distributed Syst.	2009	DBLP DOI BibTeX RDF
16	Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig B. Zilles	Blueshift: Designing processors for timing speculation from the ground up.	HPCA	2009	DBLP DOI BibTeX RDF
16	Tak Wah Lam, Lap-Kei Lee, Hing-Fung Ting, Isaac Kar-Keung To, Prudence W. H. Wong	Sleep with Guilt and Work Faster to Minimize Flow Plus Energy.	ICALP (1)	2009	DBLP DOI BibTeX RDF
16	Subhash Saini, Andrey Naraikin, Rupak Biswas, David Barkai, Timothy Sandstrom	Early performance evaluation of a "Nehalem" cluster using scientific and engineering applications.	SC	2009	DBLP DOI BibTeX RDF
16	Zusong Li, Dandan Huan, Weiwu Hu, Zhimin Tang	Chip Multithreaded Consistency Model.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	Godson-2, computer architecture, multithreading, memory consistency model, event ordering
16	Dimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, Michail Maniatakos, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi 0001	Systematic Software-Based Self-Test for Pipelined Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
16	Roman L. Lysecky	Scalability and Parallel Execution of Warp Processing: Dynamic Hardware/Software Partitioning.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	Warp processing, Embedded systems, Hardware/software partitioning, Dynamically adaptable systems
16	Joonhyuk Yoo, Manoj Franklin	Hierarchical Verification for Increasing Performance in Reliable Processors.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Active verification management, Filter checker, Correctness non-critically, Fault tolerance, Performance, Hierarchical verification
16	Jian-Jia Chen, Chia-Mei Hung, Tei-Wei Kuo	On the Minimization fo the Instantaneous Temperature for Periodic Real-Time Tasks.	IEEE Real-Time and Embedded Technology and Applications Symposium	2007	DBLP DOI BibTeX RDF	Temperature-aware scheduling, Real-time systems, Dynamic voltage scaling
16	Gokhan Memik, William H. Mangione-Smith	Evaluating Network Processors using NetBench.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Embedded systems, benchmarking, network processors
16	P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil	A Predictive Performance Model for Superscalar Processors.	MICRO	2006	DBLP DOI BibTeX RDF
16	Arata Shinozaki, Masatoshi Shima 0002, Minyi Guo, Mitsunori Kubo	A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF