Search results for "reconfigurable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
22	Per Haglund, Oskar Mencer, Wayne Luk, Benjamin Tai	PyHDL: Hardware Scripting with Python.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Tien-Lung Lee, Neil W. Bergmann	An Interface Methodology for Retargettable FPGA Peripherals.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Timothy F. Oliver, Douglas L. Maskell	Towards Run-Time Re-Configurable Techniques for Real-Time Embedded Applications.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Stephen Charlwood, Steven F. Quigley	The Impact of Routing Architecture on Reconfiguration Overheads.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Cameron Patterson	A Dynamic Module Server for Embedded Platform FPGAs.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	William D. Smith, Austars R. Schnore	Towards an RCC-Based Accelerator for Computational Fluid Dynamics Applications.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Kendra M. L. Cooper, Jia Zhou, Hui Ma 0006, I-Ling Yen, Farokh B. Bastani	Code Parameterization for Satisfaction of QoS Requirements in Embedded Software.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Seong Yong Ohm, Ki-Yeol Ryu, Kang Yi	Lower Bound Estimation on the Numbers of LUT Blocks and Micro-Registers for Time-Mulitplexed FPGA Synthesis.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	A. P. Shanthi, Balaji Vijayan, Manivel Rajendran, Senthilkumar Veluswami, Ranjani Parthasarathi	JBits Based Fault Tolerant Framework for Evolvable Hardware.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Maryam S. Mirian, Majid Nili Ahmadabadi, Babak Nadjar Araabi	A Fault Tolerant Multi-Agent System with Non-Deterministic Decision-Making for Task Allocation.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Paul M. Heysters, Gerard J. M. Smit, Egbert Molenkamp	Montium - Balancing between Energy-Efficiency, Flexibility and Performance.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Jong-Ru Guo, Chao You, Michael Chu, Kuan Zhou, Young Uk Yim, Robert W. Heikaus, Russell P. Kraft, John F. McDonald 0001	A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Klaus Danne, Christophe Bobda, Heiko Kalte	Increasing Efficiency by Partial Hardware Reconfiguration: Case Study of a Multi-Controller System.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Ronald Scrofano, Ju-wook Jang, Viktor K. Prasanna	Energy-Efficient Discrete Cosine Transform on FPGAs.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Jing Ma, Peter Athanas	A JBits-Based Incremental Design Environment with Non-Preemptive Refinement for Multi-Million Gate FPGAs.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Zhihong Zhao, Miriam Leeser	Precision Modeling of Floating-Point Applications for Variable Bitwidth Computing.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Seong-Yong Ahn, Yo-Seop Hwang, Jae-Hong Shim, Jeong-A Lee	Producer and Consumer: Roles of a Microprocessor and a Configurable Logic in a Configurable SoC.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	S. Murat Bicer, Frank Pilhofer, Graham Bardouleau, Jeffrey Smith	Next Generation Architecture for Heterogeneous Embedded Systems.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Oswaldo Cadenas, Graham M. Megson, Toomas P. Plaks	FPGA Circuits for a Monte-Carlo Based Matrix Inversion Architecture.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Jonathan M. Gentle, Iyad A. Ajwa	Draak: A Mulitlanguage Macro Compiler.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Jacir Luiz Bordim, Yasuaki Ito, Koji Nakano	Instance-Specific Solutions to Accelerate the CKY Parsing.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Razak Mohammedali	Altera FPGA Technology Provides Innovative Solutions for Evolving Market Needs.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
22	Jürgen Becker 0001, Martin Vorbach	PACT XPP Architecture in Adaptive System-on-Chip Integration.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
21	Mingjie Lin, Ilia A. Lebedev, John Wawrzynek	High-throughput bayesian computing machine with reconfigurable hardware.	FPGA	2010	DBLP DOI BibTeX RDF	reconfigurable hardware, bayesian computing
21	Neil Gershenfeld, David Dalrymple, Kailiang Chen, Ara N. Knaian, Forrest Green, Erik D. Demaine, Scott Greenwald, Peter Schmidt-Nielsen	Reconfigurable asynchronous logic automata: (RALA).	POPL	2010	DBLP DOI BibTeX RDF	reconfigurable, logic, asynchronous, automata
21	Shahin Golshan, Eli Bozorgzadeh, Benjamin Carrión Schäfer, Kazutoshi Wakabayashi, Houman Homayoun, Alexander V. Veidenbaum	Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems.	ISLPED	2010	DBLP DOI BibTeX RDF	computer aided design, placement, dynamic reconfiguration, temperature, reconfigurable systems
21	Ananth Nallamuthu, Melissa C. Smith, Scott S. Hampton, Pratul K. Agarwal, Sadaf R. Alam	Energy efficient biomolecular simulations with FPGA-based reconfigurable computing.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	biomolecular simulations, lammps, fpga, reconfigurable computing, molecular dynamics
21	Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis	Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays.	J. Supercomput.	2009	DBLP DOI BibTeX RDF	Coarse-grained reconfigurable arrays, High productivity tools, Modulo scheduling, Architectural exploration, Compiler techniques
21	Kazuteru Namba, Yoshikazu Matsui, Hideo Ito	Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding.	J. Electron. Test.	2009	DBLP DOI BibTeX RDF	IP core testing, Fixing-flipping coding, Fixing-shifting-flipping coding, Test compression, Reconfigurable network
21	Taewook Oh, Bernhard Egger 0002, Hyunchul Park 0001, Scott A. Mahlke	Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures.	LCTES	2009	DBLP DOI BibTeX RDF	software pipelining, placement and routing, coarse-grained reconfigurable architectures
21	Walid A. Najjar, Jason R. Villarreal	Reconfigurable Computing in the New Age of Parallelism.	SAMOS	2009	DBLP DOI BibTeX RDF	FPGAs, Reconfigurable computing
21	Yanteng Sun, Peng Li 0031, Guochang Gu, Yuan Wen, Yuan Liu, Dong Liu	HMMer acceleration using systolic array based reconfigurable architecture.	FPGA	2009	DBLP DOI BibTeX RDF	reconfigurable., systolic array, acceleration, hmmer
21	Viviane Lucy Santos de Souza, Victor Wanderley Costa de Medeiros, Manoel Eusébio de Lima	Architecture for dense matrix multiplication on a high-performance reconfigurable system.	SBCCI	2009	DBLP DOI BibTeX RDF	BRAMs (RAM blocks), MAC (multiplier unit), RASC (reconfigurable application-specific computing), performance, FPGA (field programmable gate array), parallelism, matrix multiplication, data reuse
21	Caroline Concatto, Debora Matos, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Érika F. Cota, Márcio Eduardo Kreutz	Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router.	SBCCI	2009	DBLP DOI BibTeX RDF	reconfigurable router, fault tolerance, reliability, network-on-chip, NoC
21	Jie Li 0004, Haibo He, Hong Man, Sachi Desai	A General-Purpose FPGA-Based Reconfigurable Platform for Video and Image Processing.	ISNN (3)	2009	DBLP DOI BibTeX RDF	video and image processing, edge detection, Reconfigurable system, FPGA design, image scaling
21	Jonathan Hook, Stuart Taylor, Alex Butler, Nicolas Villar, Shahram Izadi	A reconfigurable ferromagnetic input device.	UIST	2009	DBLP DOI BibTeX RDF	ferromagnetic sensing, malleable surface, reconfigurable input device, tangibles, multi-touch
21	Horng-Ren Tsai	Parallel Algorithms for the Weighted Distance Transform on Linear Arrays with a Reconfigurable Pipelined Bus System.	ICA3PP	2009	DBLP DOI BibTeX RDF	linear array with a reconfigurable pipelined bus system, parallel algorithms, image processing, Distance transform
21	Shinya Kubota, Minoru Watanabe	A nine-context programmable optically reconfigurable gate array with semiconductor lasers.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	holographic memory, optically reconfigurable gate arrays, field programmable gate arrays
21	Henrique Cota de Freitas, Philippe Olivier Alexandre Navaux	On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routers.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	adaptable topologies, programmable NoC routers, networks-on-chip, reconfigurable computing, crossbar switch
21	Yiqing Huang 0002, Qin Liu 0002, Satoshi Goto, Takeshi Ikenaga	Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	reconfigurable architecture, h.264, vlsi
21	Yoonjin Kim, Rabi N. Mahapatra	Dynamic context management for low power coarse-grained reconfigurable architecture.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	context word, embedded systems, system-on-chip (soc), digital signal processing, coarse-grained reconfigurable architecture, configuration cache
21	Xin Li 0020, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja	A reconfigurable stochastic architecture for highly reliable computing.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	stochastic logic, reconfigurable architecture, reliable computing
21	Zhiguo Ge, Tulika Mitra, Weng-Fai Wong	A DVS-based pipelined reconfigurable instruction memory.	DAC	2009	DBLP DOI BibTeX RDF	reconfigurable memory, low power, instruction cache
21	Roger D. Chamberlain, Narayan Ganesan	Sorting on architecturally diverse computer systems.	HPRCTA@SC	2009	DBLP DOI BibTeX RDF	architecturally diverse systems, field-programmable gate arrays, sorting, reconfigurable hardware
21	Jin Hwan Park, H. K. Dai 0001	Reconfigurable hardware solution to parallel prefix computation.	J. Supercomput.	2008	DBLP DOI BibTeX RDF	Parallel prefix computation, Field-programmable gate arrays, Pipeline, Dataflow, Reconfigurable hardware
21	Jie Tao 0001, Marcel Kunze, Fabian Nowak, Rainer Buchty, Wolfgang Karl	Performance Advantage of Reconfigurable Cache Design on Multicore Processor Systems.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	Simulation, Reconfigurable architecture, Multicore processor, Cache performance
21	Tarek A. El-Ghazawi, Esam El-Araby, Miaoqing Huang, Kris Gaj, Volodymyr V. Kindratenko, Duncan A. Buell	The Promise of High-Performance Reconfigurable Computing.	Computer	2008	DBLP DOI BibTeX RDF	HPRC systems, field-programmable gate arrays, high-performance computing, reconfigurable computing
21	Hayden Kwok-Hay So, Robert W. Brodersen	A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	BORPH, hardware process, FPGA, reconfigurable computers, UNIX
21	Nan Guan, Qingxu Deng, Zonghua Gu 0001, Wenyao Xu, Ge Yu 0001	Schedulability analysis of preemptive and nonpreemptive EDF on partial runtime-reconfigurable FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	reconfigurable devices, FPGA, Real-time scheduling
21	Andreas Raabe, Philipp A. Hartmann, Joachim K. Anlauf	ReChannel: Describing and simulating reconfigurable hardware in systemC.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	hardware description, simulation, refinement, dynamic reconfiguration, SystemC, Reconfigurable hardware
21	Ioannis Sourdis, João Bispo, João M. P. Cardoso, Stamatis Vassiliadis	Regular Expression Matching in Reconfigurable Hardware.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	network security, pattern matching, regular expression, reconfigurable hardware
21	Ricardo Galán	Hybrid Heuristic Approaches for Scheduling in Reconfigurable Manufacturing Systems.	Metaheuristics for Scheduling in Industrial and Manufacturing Applications	2008	DBLP DOI BibTeX RDF	Reconfigurable Manufacturing Systems, Scheduling, Ant Colony Optimization, Tabu Search, Meta-heuristics
21	Bjorn De Sutter, Paul Coene, Tom Vander Aa, Bingfeng Mei	Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays.	LCTES	2008	DBLP DOI BibTeX RDF	register allocation, placement and routing, coarse-grained, reconfigurable arrays
21	Hyunchul Park 0001, Kevin Fan, Scott A. Mahlke, Taewook Oh, Heeseok Kim, Hong-Seok Kim	Edge-centric modulo scheduling for coarse-grained reconfigurable architectures.	PACT	2008	DBLP DOI BibTeX RDF	operand routing, programmable accelerator, software pipelining, coarse-grained reconfigurable architecture
21	Monica Magalhães Pereira, Sílvio R. F. de Araújo, Bruno Cruz de Oliveira, Ivan Saraiva Silva	Using traditional loop unrolling to fit application on a new hybrid reconfigurable architecture.	SAC	2008	DBLP DOI BibTeX RDF	stream-based, optimization, performance, reconfigurable architecture
21	Gianmarco Baldini, Raimondo Giuliani, Dimitrios Symeonidis	Reconfigurable Radio Systems for Public Safety Based on Low-Cost Platforms.	EuroISI	2008	DBLP DOI BibTeX RDF	reconfigurable radio systems, security, SDR, public safety
21	Didier Keymeulen, Adrian Stoica, Ricardo Salem Zebulum, Srinivas Katkoori, Pradeep Fernando, Hariharan Sankaran, Mohammad M. Mojarradi, Taher Daud	Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core.	ICES	2008	DBLP DOI BibTeX RDF	Self-Healing and Compensation, Self-reconfigurable, Field Programmable Analog Array
21	Emilia Sipos, Lelia Festila, Gabriel Oltean	Towards Reconfigurable Circuits Based on Ternary Controlled Analog Multiplexers/Demultiplexers.	KES (3)	2008	DBLP DOI BibTeX RDF	Analog multiplexer, reconfigurable circuit, transmission gate, CMOS transistors, SUS-LOC
21	Ming Zhong, Mantian Li, Li-Ning Sun	Tanbot: A Self-reconfigurable Robot Enhanced with Mobility.	ICIRA (1)	2008	DBLP DOI BibTeX RDF	mobility, modularity, docking, Self-reconfigurable robot
21	Ambrose Chu, Scott Miller, Mihai Sima	Reconfigurable solutions for very-long arithmetic with applications in cryptography.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	field-programmable gate arrays, embedded systems, cryptography, reconfigurable computing
21	Tzung-Rung Jung, Lan-Da Van, Wai-Chi Fang, Teng-Yao Sheu	Reconfigurable Depth Buffer Compression Design for 3D Graphics System.	MUE	2008	DBLP DOI BibTeX RDF	depth buffer compression, Reconfigurable, 3D graphics
21	Hans G. Kerkhoff, Jarkko J. M. Huijts	Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications.	DELTA	2008	DBLP DOI BibTeX RDF	reconfigurable multi-processor-cores SoC, embedded system test, dependable SoCs, ATPG, Design-for-Test, self-repair
21	Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis 0001	ARISE Machines: Extending Processors with Hybrid Accelerators.	ARC	2008	DBLP DOI BibTeX RDF	reconfigurable instruction set processor, custom unit, FPGA, coprocessor
21	Yang Cao, Hoda A. ElMaraghy, Ahmed Azab	Reconfigurable Control Structure for Robots in Assembly.	J. Intell. Robotic Syst.	2007	DBLP DOI BibTeX RDF	Reconfigurable control, Supervisory Control Switching System, Robotic system
21	Iván González 0004, Estanislao Aguayo, Sergio López-Buedo	Self-Reconfigurable Embedded Systems on Low-Cost FPGAs.	IEEE Micro	2007	DBLP DOI BibTeX RDF	reconfigurable hardware, real-time and embedded systems, special-purpose and application-based systems, algorithms implemented in hardware
21	Nicholas Moore, Albert Conti, Miriam Leeser, Laurie A. Smith King	Vforce: An Extensible Framework for Reconfigurable Supercomputing.	Computer	2007	DBLP DOI BibTeX RDF	Vforce framework, reconfigurable computing, Supercomputing
21	Duncan A. Buell, Tarek A. El-Ghazawi, Kris Gaj, Volodymyr V. Kindratenko	Guest Editors' Introduction: High-Performance Reconfigurable Computing.	Computer	2007	DBLP DOI BibTeX RDF	HPRCs, FPGAs, reconfigurable computing
21	Gerald R. Morris, Viktor K. Prasanna	Sparse Matrix Computations on Reconfigurable Hardware.	Computer	2007	DBLP DOI BibTeX RDF	Jacobi method, FPGAs, reconfigurable computing, Conjugate gradient method
21	Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, Soon-Jyh Chang	Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Reconfigurable oscillator, Sinusoidal signal generator, Sigma-delta modulator
21	Euripides Sotiriades, Apostolos Dollas	A General Reconfigurable Architecture for the BLAST Algorithm.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	FPGA BLAST, reconfigurable BLAST architecture, FPGA BLAST architecture, bioinformatic hardware, bioinformatic FPGA
21	Angela L. Chiu, Gagan L. Choudhury, Robert D. Doverspike, Guangzhi Li	Restoration Design in IP over Reconfigurable All-Optical Networks.	NPC	2007	DBLP DOI BibTeX RDF	IP-over-Optical, ULH, ROADM, reconfigurable all-optical network, wavelength service, shared mesh restoration, restoration overbuild, traffic engineering, fast reroute, IP service
21	Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara	Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors.	ETS	2007	DBLP DOI BibTeX RDF	Dynamically reconfigurable processors, optimal contexts, test frames, self-test, test application time
21	Afshin Niktash, Hooman Parizi, Nader Bagherzadeh	A Reconfigurable Processor for Forward Error Correction.	ARCS	2007	DBLP DOI BibTeX RDF	Turbo, Forward Error Correction, Processing Element, Reconfigurable Processor, Viterbi
21	Minoru Watanabe, Fuminori Kobayashi	A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.35 micron, zero-overhead dynamic optically reconfigurable gate array VLSI, ZO-DORGA-VLSI, junction capacitance, photodiodes, load capacitance, configuration memory, CMOS process chip
21	Christoforos Kachris, Stamatis Vassiliadis	A reconfigurable platform for multi-service edge routers.	SBCCI	2007	DBLP DOI BibTeX RDF	edge routers, FPGA, reconfigurable logic
21	Pao-Ann Hsiung, Pin-Hsien Lu, Chih-Wen Liu	Energy efficient co-scheduling in dynamically reconfigurable systems.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	energy efficient, reconfigurable systems
21	Pierre Peterlongo, Laurent Noé, Dominique Lavenier, Gilles Georges, Julien Jacques, Gregory Kucherov, Mathieu Giraud	Protein Similarity Search with Subset Seeds on a Dedicated Reconfigurable Hardware.	PPAM	2007	DBLP DOI BibTeX RDF	subset seeds, FPGA, indexing, similarity search, reconfigurable architecture, sequence, dedicated hardware, spaced seeds
21	Avinash Karanth Kodi, Ahmed Louri	Performance adaptive power-aware reconfigurable optical interconnects for high-performance computing (HPC) systems.	SC	2007	DBLP DOI BibTeX RDF	high-performance computing (HPC), reconfigurable optical interconnects, performance modeling, power-aware
21	Mehdi Baradaran Tahoori	Application-independent defect tolerance of reconfigurable nanoarchitectures.	ACM J. Emerg. Technol. Comput. Syst.	2006	DBLP DOI BibTeX RDF	reconfigurable architectures, nanotechnology, Defect tolerance
21	José Luis Imaña, Juan Manuel Sánchez	Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF(2m) Generated by AOPs.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	Galois field GF(2m), canonical basis, reconfigurable hardware, normal basis, bit-parallel multiplier
21	Ahmad Darabiha, W. James MacLean, Jonathan Rose	Reconfigurable hardware implementation of a phase-correlation stereoalgorithm.	Mach. Vis. Appl.	2006	DBLP DOI BibTeX RDF	Stereo disparity estimation, Frame rate implementation, Reconfigurable hardware implementation, Field Programmable Gate Arrays (FPGAs), Phase correlation
21	Katarina Paulsson, Michael Hübner 0001, Markus Jung, Jürgen Becker 0001	Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs.	ISVLSI	2006	DBLP DOI BibTeX RDF	Fault Tolerance, FPGA, Reconfigurable Architectures, Automotive, Organic Computing
21	Lotfi Mhamdi, Christopher Kachris, Stamatis Vassiliadis	A reconfigurable hardware based embedded scheduler for buffered crossbar switches.	FPGA	2006	DBLP DOI BibTeX RDF	buffered crossbar fabric, scheduling, reconfigurable hardware
21	Kentaroh Katoh, Hideo Ito	Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices.	ETS	2006	DBLP DOI BibTeX RDF	Coarse Grained Dynamically Reconfigurable Devices, DRP, BIST(Built-In Self Test), PE, DFT
21	Woo Hyong Lee, Jung Han Kim	H.264 Implementation with Embedded Reconfigurable Architecture.	CIT	2006	DBLP DOI BibTeX RDF	Parallelized Processing, Configurability, H.264, Reconfigurable Array
21	Hayden Kwok-Hay So, Artem Tkachenko, Robert W. Brodersen	A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	hardware process, reconfigurable computers
21	Hyunchul Park 0001, Kevin Fan, Manjunath Kudlur, Scott A. Mahlke	Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures.	CASES	2006	DBLP DOI BibTeX RDF	graph embedding, modulo scheduling, coarse-grained reconfigurable architecture
21	C. Greg Plaxton, Yu Sun 0012, Mitul Tiwari, Harrick M. Vin	Reconfigurable resource scheduling.	SPAA	2006	DBLP DOI BibTeX RDF	reconfigurable resource scheduling, online computation
21	Christoforos Kachris, Stamatis Vassiliadis	Design of a web switch in a reconfigurable platform.	ANCS	2006	DBLP DOI BibTeX RDF	web switch, reconfigurable logic
21	Shobana Padmanabhan, Phillip H. Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger D. Chamberlain, Ron Cytron, Jason E. Fritts, John W. Lockwood	Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures.	Int. J. Parallel Program.	2005	DBLP DOI BibTeX RDF	cycle-accurate hardware profiling, performance, architecture, Reconfigurable
21	Yuh-Rau Wang, Shi-Jinn Horng, Chin-Hsiung Wu	Efficient Algorithms for the All Nearest Neighbor and Closest Pair Problems on the Linear Array with a Reconfigurable Pipelined Bus System.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	LARPBS, reconfigurable bus model, Parallel algorithm, closest pair, all nearest neighbors
21	Cid C. de Souza, André M. Lima, Guido Araujo, Nahri Moreano	The datapath merging problem in reconfigurable systems: Complexity, dual bounds and heuristic evaluation.	ACM J. Exp. Algorithmics	2005	DBLP DOI BibTeX RDF	Data path merging, heuristics, lower bounds, reconfigurable systems
21	Antonio Carlos Schneider Beck, Victor F. Gomes, Luigi Carro	Exploiting Java through binary translation for low power embedded reconfigurable systems.	SBCCI	2005	DBLP DOI BibTeX RDF	java, power consumption, binary translation, reconfigurable processors
21	Sharareh Babvey, Anu G. Bourgeois, José Alberto Fernández-Zepeda, Steven W. McLaughlin	A Parallel Implementation of the Message-Passing Decoder of LDPC Codes Using a Reconfigurable Optical Model.	SNPD	2005	DBLP DOI BibTeX RDF	optical buses, message-passing decoder, Reconfigurable architectures, LDPC codes
21	Marco Lanuzza, Martin Margala, Pasquale Corsonello	Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications.	ISLPED	2005	DBLP DOI BibTeX RDF	reconfigurable computing, datapath, processor-in-memory
21	Mihai Udrescu, Lucian Prodan, Mircea Vladutiu	Improving quantum circuit dependability with reconfigurable quantum gate arrays.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	accuracy threshold, reconfigurable quantum gate arrays, coding
21	Lu Yan, Zheng Liang	Reconfigurable Computing in Ubiquitous Computers: A Roadmap.	PDCAT	2005	DBLP DOI BibTeX RDF	Reconfigurable, Embedded, Ubiquitous, Codesign, Roadmap
21	Hamid Fadishei, Morteza Saheb Zamani, Masoud Sabaei	A novel reconfigurable hardware architecture for IP address lookup.	ANCS	2005	DBLP DOI BibTeX RDF	field-programmable gate array (FPGA), application specific integrated circuit (ASIC), hashing, reconfigurable hardware, longest prefix matching, IP address lookup
21	Amitava Datta	Multiple Addition and Prefix Sum on a Linear Array with a Reconfigurable Pipelined Bus System.	J. Supercomput.	2004	DBLP DOI BibTeX RDF	pipelined bus, reconfigurable bus, matrix multiplication, addition, optical computing, prefix sum
21	Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen	Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices.	FPL	2004	DBLP DOI BibTeX RDF	field-programable gate array (FPGA), occupied space manager (OSM), routing-conscious placement, Manhattan metric, line sweep technique, optimal running time, lower bounds, Reconfigurable computing, module placement