Search results for "timing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Xiaocong Zhou, Jianping Chen, Tiejun Huang 0001	A Scene Representation Application Implementing LASeR Using Object-Based Timing Model.	PCM	2008	DBLP DOI BibTeX RDF	object-based timing model, LASeR, rich-media, scene description
21	Jürgen Schnerr, Oliver Bringmann 0001, Alexander Viehl, Wolfgang Rosenstiel	High-performance timing simulation of embedded software.	DAC	2008	DBLP DOI BibTeX RDF	software timing, virtual prototypes, simulation acceleration
21	Noel Menezes, Chandramouli V. Kashyap, Chirayu S. Amin	A "true" electrical cell model for timing, noise, and power grid verification.	DAC	2008	DBLP DOI BibTeX RDF	static timing analysis, current source models, cell models
21	Kenneth Eguro, Scott Hauck	Enhancing timing-driven FPGA placement for pipelined netlists.	DAC	2008	DBLP DOI BibTeX RDF	timing-driven, FPGA, simulated annealing, pipelined, placement
21	Vadim I. Arkin, Alexander Slastnikov	The effect of depreciation allowances on the timing of investment and government tax revenue.	Ann. Oper. Res.	2007	DBLP DOI BibTeX RDF	Corporate taxation, Depreciation policy, Stochastic cash flows, Investment timing, Tax revenue, Net present value
21	Naoki Masuda, Hiroshi Kori	Formation of feedforward networks and frequency synchrony by spike-timing-dependent plasticity.	J. Comput. Neurosci.	2007	DBLP DOI BibTeX RDF	Synchronization, Complex networks, Spike-timing-dependent plasticity, Feedforward networks
21	Jan Reineke 0001, Daniel Grund, Christoph Berg, Reinhard Wilhelm	Timing predictability of cache replacement policies.	Real Time Syst.	2007	DBLP DOI BibTeX RDF	Predictability, Timing analysis, Hard real-time systems, Cache replacement policies, Cache analysis
21	Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra 0001, Xu Cheng 0001	A Retargetable Software Timing Analyzer Using Architecture Description Language.	ASP-DAC	2007	DBLP DOI BibTeX RDF	retargetable software timing analyzer, static WCET analysis, program path analysis, microarchitecture modeling, graph-based execution models, pipeline model, real-time systems, architecture description language, worst case execution time, embedded processors, branch prediction, schedulability analysis
21	Shi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-Hong Tsai	DFM/DFY practices during physical designs for timing, signal integrity, and power.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, DFY, dynamic IR drop, process variation, physical designs, DFM, design for manufacturability, signal integrity, timing integrity, yield analysis, design for yield
21	Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl	Robust wiring networks for DfY considering timing constraints.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	redundant wiring, timing constraint aware, open defects, design for yield
21	Yue Zhuo, Hao Li, Qiang Zhou 0001, Yici Cai, Xianlong Hong	New timing and routability driven placement algorithms for FPGA synthesis.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	congestion driven placement, physical synthesis, timing driven placement, net weight
21	Naoaki Ohkubo, Kimiyoshi Usami	Delay modeling and static timing analysis for MTCMOS circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF	interpolation., selective-MT, delay, leakage power, static timing analysis, MTCMOS
21	Jaskirat Singh, Sachin S. Sapatnekar	Statistical timing analysis with correlated non-gaussian parameters using independent component analysis.	DAC	2006	DBLP DOI BibTeX RDF	non-Gaussian, independent component analysis, statistical timing, moment matching
21	Amitava Majumdar 0002, Wei-Yu Chen, Jun Guo	Hold time validation on silicon and the relevance of hazards in timing analysis.	DAC	2006	DBLP DOI BibTeX RDF	hold time validation, ATPG, timing analysis, delay test
21	Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, Chandu Visweswariah	Criticality computation in parameterized statistical timing.	DAC	2006	DBLP DOI BibTeX RDF	criticality probability, parametric variation, statistical timing
21	Hai Lin, Yu Wang 0002, Rong Luo, Huazhong Yang, Hui Wang 0004	IR-drop Reduction Through Combinational Circuit Partitioning.	PATMOS	2006	DBLP DOI BibTeX RDF	Static Timing Analysis, IR-drop, circuit partitioning
21	Yiping Cheng, Da-Zhong Zheng	Min-Max Inequalities and the Timing Verification Problem with Max and Linear Constraints.	Discret. Event Dyn. Syst.	2005	DBLP DOI BibTeX RDF	min-max inequalities, min-max functions, timing analysis and verification, discrete event systems
21	Gang Chen 0020, Jason Cong	Simultaneous timing-driven placement and duplication.	FPGA	2005	DBLP DOI BibTeX RDF	logic duplication, FPGA, legalization, timing-driven placement, redundancy removal
21	Sotirios Matakias, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis	A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	soft and timing errors, monitoring circuits, concurrent testing, time redundancy
21	Aloysius K. Mok, Prabhudev Konana, Guangtian Liu, Chan-Gun Lee, Honguk Woo	Specifying Timing Constraints and Composite Events: An Application in the Design of Electronic Brokerages.	IEEE Trans. Software Eng.	2004	DBLP DOI BibTeX RDF	electronic brokerages, event specification, timing constraints, Active databases, real-time databases
21	Shamik Das, Anantha P. Chandrakasan, Rafael Reif	Timing, energy, and thermal performance of three-dimensional integrated circuits.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	thermal optimization, timing, energy, 3-D IC, 3-D integration
21	Aman Kokrady, C. P. Ravikumar	Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures.	VLSI Design	2004	DBLP DOI BibTeX RDF	Timing Failure, Test Validation, Crosstalk, At Speed Testing, IR Drop
21	Bernd Obermeier, Frank M. Johannes	Quadratic placement using an improved timing model.	DAC	2004	DBLP DOI BibTeX RDF	Steiner tree net model, optimization potential, sensitivity, Quadratic placement, timing driven placement
21	Fan Mo, Robert K. Brayton	A timing-driven module-based chip design flow.	DAC	2004	DBLP DOI BibTeX RDF	timing constraints, design flow, physical synthesis
21	Xiaohua Kong, Radu Negulescu, Larry Weidong Ying	Refinement-based formal verification with heterogeneous timing.	Int. J. Softw. Tools Technol. Transf.	2003	DBLP DOI BibTeX RDF	Communication refinement, Refinement-based verification, Relative timing, globally asynchronous locally synchronous, Process space
21	Jörg E. Vollrath	Output Timing Measurement Using an Idd Method.	MTDT	2003	DBLP DOI BibTeX RDF	DDR, timing, DRAM
21	Werner Schindler, Colin D. Walter	More Detail for a Combined Timing and Power Attack against Implementations of RSA.	IMACC	2003	DBLP DOI BibTeX RDF	statistical decision problem, power analysis, exponentiation, timing attack, RSA cryptosystem, side channel leakage, Montgomery modular multiplication
21	Ingmar Neumann, Kolja Sulimma, Wolfgang Kunz	Accelerating Retiming Under the Coupled-Edge Timing Model.	ISVLSI	2002	DBLP DOI BibTeX RDF	retiming, timing optimization
21	Ali Dasdan	A strongly polynomial-time algorithm for over-constraint resolution: efficient debugging of timing constraint violations.	CODES	2002	DBLP DOI BibTeX RDF	scheduling, high-level synthesis, constraint satisfaction, timing constraints, behavioral synthesis, rate analysis
21	Ajay J. Daga, Loa Mize, Subramanyam Sripada, Chris Wolff, Qiuyang Wu	Automated timing model generation.	DAC	2002	DBLP DOI BibTeX RDF	EDA, static timing analysis, model generation
21	Katsuyuki Okeya, Kouichi Sakurai	Power Analysis Breaks Elliptic Curve Cryptosystems even Secure against the Timing Attack.	INDOCRYPT	2000	DBLP DOI BibTeX RDF	Montgomery-form, Scalar Multiplication Algorithm, Elliptic Curve Cryptosystem, Power Analysis, Timing Attack, Efficient Implementation
21	Eugene Goldberg, Alexander Saldanha	Timing Analysis with Implicitly Specified False Paths.	VLSI Design	2000	DBLP DOI BibTeX RDF	known false paths, implicit false path representation, timing analysis, breadth-first search
21	Anastasio Molano, Kanaka Juvva, Ragunathan Rajkumar	Real-time filesystems - Guaranteeing timing constraints for disk accesses in RT-Mach.	RTSS	1997	DBLP DOI BibTeX RDF	real-time file systems, RT-Mach, real-time database applications, real-time disk scheduling algorithm, earliest deadline scheduling, just-in-time scheduling, aperiodic servers, disk throughput, admission control policies, microkernel-based system, real-time shell, resource reservation paradigm, disk scheduling algorithms, performance, usability, real-time systems, multimedia systems, timing constraint, disks, disk access, concurrent applications
21	Sijing Zhang, Alan Burns 0001	Timing Properties of the Timed Token MAC Protocol.	ICCCN	1997	DBLP DOI BibTeX RDF	timed token MAC protocol, synchronous bandwidth, real-time communications, FDDI networks, Timing properties
21	James C. Corbett	Timing Analysis of Ada Tasking Programs.	IEEE Trans. Software Eng.	1996	DBLP DOI BibTeX RDF	real-time systems, program verification, hybrid systems, Timing analysis, Ada tasking
21	Kyeonghoon Koo, Wook Hyun Kwon	Worst-case timing prediction of relay ladder logic by constraint analysis.	RTCSA	1996	DBLP DOI BibTeX RDF	worst-case timing prediction, relay ladder logic, boolean logic equations, logic equations, complexity, logic programming, logic programming, application programs, constraint analysis
21	Namyun Kim	A scheduling technique for real-time systems with end-to-end timing constraints.	RTCSA	1996	DBLP DOI BibTeX RDF	end-to-end timing constraints, shared tasks, overload situations, real-time systems, real-time systems, scheduling technique
21	David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah	Timing verification of sequential domino circuits.	ICCAD	1996	DBLP DOI BibTeX RDF	domino gates, sequential domino circuits, static timing verification, logic testing, input signals
21	B. Antal, György Csertán, István Majzik, Andrea Bondavalli, Luca Simoncini	Reachability and Timing Analysis in Data Flow Networks: A Case Study.	EUROMICRO	1996	DBLP DOI BibTeX RDF	data flow networks, computer control systems, performance, safety, timing analysis, reachability analysis, reachability analysis
21	Richard Gerber 0001, Seongsoo Hong	Compiling Real-Time Programs With Timing Constraint Refinement and Structural Code Motion.	IEEE Trans. Software Eng.	1995	DBLP DOI BibTeX RDF	gated single assignment, Real-time, programming languages, compiler optimization, timing analysis, code motion, static single assignment, trace scheduling, code scheduling
21	Michael González Harbour, Mark H. Klein, John P. Lehoczky	Timing Analysis for Fixed-Priority Scheduling of Hard Real-Time Systems.	IEEE Trans. Software Eng.	1994	DBLP DOI BibTeX RDF	periodic task set, fixed-priority methods, serially executed subtasks, complex priority structure, nonpreemptible sections, scheduling, schedulability, real-time systems, robots, robotics, message passing, interrupts, interrupts, timing analysis, execution time, hard real-time systems, fixed-priority scheduling, precedence constraints, periodic tasks, message-passing systems, synchronization protocols, uniprocessor
21	Jia Xu, David Lorge Parnas	On Satisfying Timing Constraints in Hard-Real-Time Systems.	IEEE Trans. Software Eng.	1993	DBLP DOI BibTeX RDF	pre-run-time scheduling, mathematical scheduling problems, scheduling, real-time systems, timing constraints, operating systems (computers), hard-real-time systems
21	Nancy A. Lynch, Frits W. Vaandrager	Forward and Backward Simulations for Timing-Based Systems.	REX Workshop	1991	DBLP DOI BibTeX RDF	timing-based systems, backward simulations, forward-backward simulations, backward-forward simulations, history variables, prophecy variables, history relations, prophecy relations, Simulations, real-time, timed automata, refinement mappings, forward simulations
20	Xiu-Hong Wang, Xingpeng Mao, Hui-Xiao Ma, Gongliang Liu, Ping Wu	An interleaver acquisition scheme in asynchronous IDMA systems.	IWCMC	2010	DBLP DOI BibTeX RDF	interleaver acquisition, sliding correlation, timing synchronization IDMA
20	Myungsu Choi, Minsu Choi	Scalability of Globally Asynchronous QCA (Quantum-Dot Cellular Automata) Adder Design.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	QCA (quantum-dot cellular automata), Asynchronous architecture, Layout timing problem, Scalability, Robustness
20	Elif Alpaslan, Yu Huang 0005, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak	Reducing Scan Shift Power at RTL.	VTS	2008	DBLP DOI BibTeX RDF	Test Power Reduction, Power-Sensitive Scan Cell, RTL DFT, Timing Closure, Scan Based Test
20	Vishal Khandelwal, Ankur Srivastava 0001	Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation.	ISPD	2007	DBLP DOI BibTeX RDF	post-silicon tunability, variability, stochastic optimization, timing optimization, gate sizing
20	Rajesh Sundaresan, Sergio Verdú	Capacity of queues via point-process channels.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF	channels with feedback, direct-detection photon channel, poisson channel, queue, nonlinear filtering, point process, rate, intensity, timing channel
20	Jameleddine Hassine, Juergen Rilling, Rachida Dssouli	Timed Use Case Maps.	SAM	2006	DBLP DOI BibTeX RDF	timing aspects, timed UCM, Clocked Transition Systems, performance, User Requirements Notation, Use Case Maps
20	Hosung (Leo) Kim, John Lillis, Milos Hrkic	Techniques for improved placement-coupled logic replication.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	placement, timing optimization, programmable logic, logic replication
20	Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout	A multi-port current source model for multiple-input switching effects in CMOS library cells.	DAC	2006	DBLP DOI BibTeX RDF	MCSM, cell library characterization, multiple input switching, timing analysis, current source model, cell model
20	Roberto Giacobazzi, Isabella Mastroeni	Timed Abstract Non-interference.	FORMATS	2005	DBLP DOI BibTeX RDF	security, Abstract interpretation, non-interference, timing channels
20	Milos Hrkic, John Lillis, Giancarlo Beraudo	An approach to placement-coupled logic replication.	DAC	2004	DBLP DOI BibTeX RDF	placement, timing optimization, programmable logic, logic replication
20	Kristian Sandström, Christer Norström	Managing Complex Temporal Requirements in Real-Time Control Systems.	ECBS	2002	DBLP DOI BibTeX RDF	assigning priorities, assigning offsets, relative timing constraints, scheduling, Real-time systems, control systems
20	Werner Schindler, François Koeune, Jean-Jacques Quisquater	Improving Divide and Conquer Attacks against Cryptosystems by Better Error Detection / Correction Strategies.	IMACC	2001	DBLP DOI BibTeX RDF	Error detection, error correction, timing attack, power attack
20	Jeffrey E. Boyd, James J. Little	Phase in Model-Free Perception of Gait.	Workshop on Human Motion	2000	DBLP DOI BibTeX RDF	model-free perception, periodic systems, model-free shape-of-motion phase analysis, phasor representation, limb pendulum-like motion, image sequences, image sequences, timing, biology computing, gait analysis, image motion analysis, human gait
20	Christopher A. Healy, Robert D. Arnold, Frank Mueller 0001, David B. Whalley, Marion G. Harmon	Bounding Pipeline and Instruction Cache Performance.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	best case execution time, Real-time systems, pipelining, timing analysis, worst case execution time, instruction cache
20	Stefan M. Petters, Annette Muth, Thomas Kolloch, Thomas Hopfner, Franz Fischer, Georg Färber	The REAR Framework for Emulation and Analysis of Embedded Hard Real-Time Systems .	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	rapid prototyping, timing constraints, schedulability analysis, SDL, design automation, hard real-time, WCET-analysis
20	Tarik Ono-Tesfaye, Christoph Kern, Mark R. Greenstreet	Verifying a Self-Timed Divider.	ASYNC	1998	DBLP DOI BibTeX RDF	model checking, refinement, asynchronous, hardware verification, timing verification, self-timed, speed-independence
20	Radu Negulescu, Ad M. G. Peeters	Verification of Speed-Dependences in Single-Rail Handshake Circuits.	ASYNC	1998	DBLP DOI BibTeX RDF	single-rail, isochronic forks, verification, timing, asynchronous circuits, progress, speed-independent circuits, process spaces, handshake circuits
20	Anirudh Devgan	Efficient coupled noise estimation for on-chip interconnects.	ICCAD	1997	DBLP DOI BibTeX RDF	coupled noise estimation, dynamic logic circuit families, noise criticality pruning, physical design based noise avoidance, circuit simulation, on-chip interconnects, Elmore delay, noise analysis, timing simulation, integrated circuit noise, deep submicron design
20	Kenneth L. Shepard, Vinod Narayanan, Peter C. Elmendorf, Gutuan Zheng	Global harmony: coupled noise analysis for full-chip RC interconnect networks.	ICCAD	1997	DBLP DOI BibTeX RDF	interconnect, noise, static timing analysis
20	H. Rebecca Callison	A Time-Sensitive Object Model for Real-Time Systems.	ACM Trans. Softw. Eng. Methodol.	1995	DBLP DOI BibTeX RDF	programming techniques, real-time processing models, fault tolerance, concurrency, timing constraints, object models
20	Daniel I. Katcher, Hiroshi Arakawa, Jay K. Strosnider	Engineering and Analysis of Fixed Priority Schedulers.	IEEE Trans. Software Eng.	1993	DBLP DOI BibTeX RDF	timing correctness, validation process, blocking components, fixed priority scheduling algorithms, timer-driven scheduling, event-driven scheduling, optimal timer rate, schedulability, scheduling, real-time systems, real-time applications, operating systems (computers), fixed priority schedulers, operating system kernels, scheduling theory, hardware platforms
20	Nancy A. Lynch	Simulation Techniques for Proving Properties of Real-Time Systems.	REX School/Symposium	1993	DBLP DOI BibTeX RDF	timing-based system, untimed system, invariant assertion, progress function, execution correspondence, Simulation, real-time system, lower bound, invariant, mutual exclusion, upper bound, clock synchronization, leader election, time bound
20	Catherine Mongenet	Affine Timings for Systems of Affine Recurrence Equations.	PARLE (1)	1991	DBLP DOI BibTeX RDF	systems of affine recurrence equations, affine timing functions, mapping, systolic arrays, processor arrays
20	Leo Yuhsiang Liu, R. K. Shyamasundar	Static Analysis of Real-Time Distributed Systems.	IEEE Trans. Software Eng.	1990	DBLP DOI BibTeX RDF	maximal parallelism model, parallel actions, temporal errors, CSP programs, software engineering, real-time systems, parallel programming, static analysis, distributed processing, programs, programming languages, reasoning, deadlocks, terminations, failures, livelocks, timing properties, real-time distributed systems, temporal behaviors
20	Emanuele Sciagura, Paolo Zicari, Stefania Perri, Pasquale Corsonello	An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector.	DSD	2007	DBLP DOI BibTeX RDF
20	V. Migairou, Robin Wilson, Sylvain Engels, Nadine Azémard, Philippe Maurine	Statistical Characterization of Library Timing Performance.	PATMOS	2006	DBLP DOI BibTeX RDF
20	B. Chung, J. B. Kuo	Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique.	PATMOS	2006	DBLP DOI BibTeX RDF
20	Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija	A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers.	PATMOS	2005	DBLP DOI BibTeX RDF
20	Reinhard Wilhelm	Timing Analysis and Timing Predictability.	FMCO	2004	DBLP DOI BibTeX RDF
20	Tudor Murgan, Alberto García Ortiz, Clemens Schlachta, Heiko Zimmer, Mihail Petrov, Manfred Glesner	On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects.	PATMOS	2004	DBLP DOI BibTeX RDF
20	Ricardo Augusto da Luz Reis	Power and Timing Driven Physical Design Automation.	PATMOS	2003	DBLP DOI BibTeX RDF
19	Rupesh S. Shelar, Marek Patyra	Impact of local interconnects on timing and power in a high performance microprocessor.	ISPD	2010	DBLP DOI BibTeX RDF	CAD, delay, interconnects, power, microprocessor
19	Matthias Rohr, André van Hoorn, Wilhelm Hasselbring, Marco Lübcke, Sergej Alekseev	Workload-intensity-sensitive timing behavior analysis for distributed multi-user software systems.	WOSP/SIPEW	2010	DBLP DOI BibTeX RDF	response time distribution, workload intensity, performance, scalability, concurrency, monitoring, profiling, software performance
19	Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang	Pulsed-latch aware placement for timing-integrity optimization.	DAC	2010	DBLP DOI BibTeX RDF	pulsed latch, placement, physical design
19	Ming Ruan, Zhenning Shi, Mark C. Reed	Training symbol based coarse timing synchronization in OFDM systems.	IEEE Trans. Wirel. Commun.	2009	DBLP DOI BibTeX RDF
19	Tilde Fusco, Angelo Petrella, Mario Tanda	Data-aided symbol timing and CFO synchronization for filter bank multicarrier systems.	IEEE Trans. Wirel. Commun.	2009	DBLP DOI BibTeX RDF
19	Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski	Timing-Aware Multiple-Delay-Fault Diagnosis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
19	Meikang Qiu, Edwin Hsing-Mean Sha	Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Embedded Systems, real-time, high-level synthesis, heterogeneous
19	Jinpeng Zhao, Qiang Zhou 0001, Yici Cai	Fast congestion-aware timing-driven placement for island FPGA.	DDECS	2009	DBLP DOI BibTeX RDF
19	Sheng Li 0007, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi	McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures.	MICRO	2009	DBLP DOI BibTeX RDF
19	Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig B. Zilles	Blueshift: Designing processors for timing speculation from the ground up.	HPCA	2009	DBLP DOI BibTeX RDF
19	Lin Xie, Azadeh Davoodi	Bound-based identification of timing-violating paths under variability.	ASP-DAC	2009	DBLP DOI BibTeX RDF
19	Kwangok Jeong, Andrew B. Kahng	Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography.	ASP-DAC	2009	DBLP DOI BibTeX RDF
19	Nicholas Callegari, Pouria Bastani, Li-C. Wang, Sreejit Chakravarty, Alexander Tetelbaum	Path selection for monitoring unexpected systematic timing effects.	ASP-DAC	2009	DBLP DOI BibTeX RDF
19	Darrell Bethea, Michael K. Reiter	Data Structures with Unpredictable Timing.	ESORICS	2009	DBLP DOI BibTeX RDF
19	Yali Liu, Dipak Ghosal, Frederik Armknecht, Ahmad-Reza Sadeghi, Steffen Schulz 0001, Stefan Katzenbeisser 0001	Hide and Seek in Time - Robust Covert Timing Channels.	ESORICS	2009	DBLP DOI BibTeX RDF
19	Shuang Tian, Kusha Panta, Himal A. Suraweera, Brendon J. C. Schmidt, Steve McLaughlin 0001, Jean Armstrong	A novel timing synchronization method for ACO-OFDM-based optical wireless communications.	IEEE Trans. Wirel. Commun.	2008	DBLP DOI BibTeX RDF
19	Iulian Ober, Susanne Graf, Yuri Yushtein, Ileana Ober	Timing analysis and validation with UML: the case of the embedded MARS bus manager.	Innov. Syst. Softw. Eng.	2008	DBLP DOI BibTeX RDF
19	Jing Huang, Wei Zhang, Yansheng Lu, Qin Yang	Reflective Design for Component-Based Distributed Systems with Timing Constraints.	COMPSAC	2008	DBLP DOI BibTeX RDF
19	Xiayong Hu, Mark Lawford, Alan Wassyng	Formal Verification of the Implementability of Timing Requirements.	FMICS	2008	DBLP DOI BibTeX RDF
19	Jae-Seok Yang, David Z. Pan	Overlay aware interconnect and timing variation modeling for double patterning technology.	ICCAD	2008	DBLP DOI BibTeX RDF
19	Yifang Liu, Rupesh S. Shelar, Jiang Hu	Delay-optimal simultaneous technology mapping and placement with applications to timing optimization.	ICCAD	2008	DBLP DOI BibTeX RDF
19	Bo Zhang	Specifying and Verifying Timing Properties of a Time-triggered Protocol for In-vehicle Communication.	SNPD	2008	DBLP DOI BibTeX RDF
19	Hsin-Hsiung Huang, Shu-Ping Chang, Yu-Cheng Lin, Tsai-Ming Hsieh	Timing-driven X-architecture router among rectangular obstacles.	ISCAS	2008	DBLP DOI BibTeX RDF
19	Hsin-Hsiung Huang, Hui-Yu Huang, Yu-Cheng Lin, Tsai-Ming Hsieh	Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system.	ISCAS	2008	DBLP DOI BibTeX RDF
19	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Optimal sleep transistor synthesis under timing and area constraints.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
19	Lin Xie, Azadeh Davoodi	Robust Estimation of Timing Yield with Partial Statistical Information on Process Variations.	ISQED	2008	DBLP DOI BibTeX RDF