Search results for "wiring"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Thomas Eschbach, Wolfgang Günther 0001, Bernd Becker 0001	Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases.	VLSI Design	2005	DBLP DOI BibTeX RDF
9	Bernhard Huber, Philipp Peti, Roman Obermaisser, Christian El Salloum	Using RTAI/LXRT for Partitioning in a Prototype Implementation of the DECOS Architecture.	WISES	2005	DBLP DOI BibTeX RDF
9	David Hales	Choose Your Tribe! - Evolution at the Next Level in a Peer-to-Peer Network.	Engineering Self-Organising Systems	2005	DBLP DOI BibTeX RDF
9	Paul Frenger	Embed with Forth.	ACM SIGPLAN Notices	2004	DBLP DOI BibTeX RDF
9	Michael J. Wiener	The Full Cost of Cryptanalytic Attacks.	J. Cryptol.	2004	DBLP DOI BibTeX RDF	Parallel collision search, Double encryption, Triple encryption, Cryptanalysis, Factoring, Discrete logarithm, Number field sieve, Meet-in-the-middle attack, Hash collision
9	Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick	Repeater scaling and its impact on CAD.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
9	Masaru Takesue	DC-mesh: A Contracted High-Dimensional Mesh for Dynamic Clustering.	NPC	2004	DBLP DOI BibTeX RDF
9	Arianna Menciassi, Samuele Gorini, G. Pernorio, Paolo Dario	A SMA Actuated Artificial Earthworm.	ICRA	2004	DBLP DOI BibTeX RDF
9	Andrzej Kochut, Norman Bobroff, Kirk A. Beaty, Gautam Kar	Management issues in storage area networks: detection and isolation of performance problems.	NOMS (1)	2004	DBLP DOI BibTeX RDF
9	Hyosun Kim, Dieter W. Fellner	Interaction with Hand Gesture for a Back-Projection Wall.	Computer Graphics International	2004	DBLP DOI BibTeX RDF
9	Zhongsheng Hua, Liang Liang 0001	Heuristics to Scenario-Based Capacity Expansion Problem of PWB Assembly Systems.	CASDMKM	2004	DBLP DOI BibTeX RDF
9	Randolph Y. Wang, Sumeet Sobti, Nitin Garg, Elisha Ziskind, Junwen Lai, Arvind Krishnamurthy	Turning the postal system into a generic digital communication mechanism.	SIGCOMM	2004	DBLP DOI BibTeX RDF	postal network, storage devices, network architecture
9	Jaskirat Singh, Sachin S. Sapatnekar	Topology optimization of structured power/ground networks.	ISPD	2004	DBLP DOI BibTeX RDF	optimization, routing, power, ground
9	Desmond Kirkpatrick, Peter J. Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester	The great interconnect buffering debate: are you a chicken or an ostrich?	ISPD	2004	DBLP DOI BibTeX RDF
9	Rajeev Balasubramonian	Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures.	ICS	2004	DBLP DOI BibTeX RDF	communication-bound processors, effective address and memory dependence prediction, processor, data prefetch, distributed caches, clustered microarchitectures
9	Atsushi Iwashita, Makoto Shimojo	Development of a mixed signal LSI for tactile data processing.	SMC (5)	2004	DBLP DOI BibTeX RDF
9	Arjun Kapoor, Nikhil Jayakumar, Sunil P. Khatri	A novel clock distribution and dynamic de-skewing methodology.	ICCAD	2004	DBLP DOI BibTeX RDF
9	Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo	SILENT: serialized low energy transmission coding for on-chip interconnection networks.	ICCAD	2004	DBLP DOI BibTeX RDF
9	Reinaldo A. Bergamaschi	Early and accurate analysis of SoCs: oxymoron or real?	SLIP	2004	DBLP DOI BibTeX RDF	performance, power, design space exploration, floorplanning, design analysis
9	Puneet Gupta 0001, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester	Investigation of performance metrics for interconnect stack architectures.	SLIP	2004	DBLP DOI BibTeX RDF	back-end metrics, interconnect stacks, via blockage, throughput, energy, bandwidth
9	Sani R. Nassif	The impact of variability on power.	ISLPED	2004	DBLP DOI BibTeX RDF	power, variability, integrated circuit
9	Marc Garbey, Arcangelo Merla, Ioannis T. Pavlidis	Estimation of Blood Flow Speed and Vessel Location from Thermal Video.	CVPR (1)	2004	DBLP DOI BibTeX RDF
9	Srinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag	Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses.	ICCD	2004	DBLP DOI BibTeX RDF
9	Shalini Ghosh, F. Joel Ferguson	Estimating detection probability of interconnect opens using stuck-at tests.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	break fault, interconnect open, stuck-at test
9	Hans Eberle, Arvinderpal Wander, Nils Gura	Testing Systems Wirelessly.	VTS	2004	DBLP DOI BibTeX RDF
9	Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi	Routability and Fault Tolerance of FPGA Interconnect Architectures.	ITC	2004	DBLP DOI BibTeX RDF
9	Aman Kokrady, C. P. Ravikumar	Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures.	VLSI Design	2004	DBLP DOI BibTeX RDF	Timing Failure, Test Validation, Crosstalk, At Speed Testing, IR Drop
9	Marghoob Mohiyuddin, Amit Prakash, Adnan Aziz, Wayne H. Wolf	Synthesizing interconnect-efficient low density parity check codes.	DAC	2004	DBLP DOI BibTeX RDF	error correcting codes, low-density parity-check codes, routing congestion
9	Fan Mo, Robert K. Brayton	A timing-driven module-based chip design flow.	DAC	2004	DBLP DOI BibTeX RDF	timing constraints, design flow, physical synthesis
9	Raymond A. Wildman, Joshua I. Kramer, Daniel S. Weile, Phillip Christie	Multi-objective optimization of interconnect geometry.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
9	José Flich, Pedro López 0001, Manuel P. Malumbres, José Duato, Tomas Rokicki	Applying In-Transit Buffers to Boost the Performance of Networks with Source Routing.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Networks of workstations, wormhole switching, irregular topologies, source routing, minimal routing
9	Wing Seung Yuen, Evangeline F. Y. Young	Slicing floorplan with clustering constraint.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
9	Chin-Chih Chang, Jason Cong, David Zhigang Pan, Xin Yuan 0005	Multilevel global placement with congestion control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
9	Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas	Global and local congestion optimization in technology mapping.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
9	Prabhakar Kudva, Andrew Sullivan, William E. Dougherty	Measurements for structural logic synthesis optimizations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
9	Aviel D. Rubin	Introduction.	Commun. ACM	2003	DBLP DOI BibTeX RDF
9	Robert F. Bedoll	A Tail of Two Projects: How 'Agile' Methods Succeeded After 'Traditional' Methods Had Failed in a Critical System-Development Project.	XP/Agile Universe	2003	DBLP DOI BibTeX RDF
9	Bruce Randall Donald, Christopher G. Levey, Craig D. McGray, Daniela Rus, Mike Sinclair	UntetheredMicro-Actuators for Autonomous Micro-robot Locomotion: Design, Fabrication, Control, and Performance.	ISRR	2003	DBLP DOI BibTeX RDF
9	Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose	Automatic transistor and physical design of FPGA tiles from an architectural specification.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA, programmable logic, PLD, automatic layout
9	Rodolfo E. Haber, José R. Alique, Angel Alique, Ramón Uribe-Etxebarria, Javier Hernández	Embedded Fuzzy Control System in an Open Computerized Numerical Control; A Technology Transfer Case-Study.	IFSA	2003	DBLP DOI BibTeX RDF
9	Sandeep Kumar Goel, Erik Jan Marinissen	Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization.	DATE	2003	DBLP DOI BibTeX RDF
9	Bart Verheecke, María Agustina Cibrán, Viviane Jonckers	AOP for Dynamic Configuration and Management of Web Services.	ICWS-Europe	2003	DBLP DOI BibTeX RDF	Web Services, Aspect Oriented Programming, Dynamic Configuration, Web Services Management, Hot-Swapping
9	Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick	The scaling challenge: can correct-by-construction design help?	ISPD	2003	DBLP DOI BibTeX RDF	clocked repeaters, correct-by-construction design, design fabrics, post-RTL design, routing, interconnect, placement, logic synthesis, scaling, technology mapping, repeaters
9	Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao	The Y-Architecture for On-Chip Interconnect: Analysis and Methodology.	ICCAD	2003	DBLP DOI BibTeX RDF
9	Joachim Pistorius, Mike Hutton	Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation.	SLIP	2003	DBLP DOI BibTeX RDF	FPGA architecture, interconnect prediction, SLIP, rent
9	Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama	Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic.	ISMVL	2003	DBLP DOI BibTeX RDF
9	James R. Heath	A systems approach to molecular electronics.	ISLPED	2003	DBLP DOI BibTeX RDF
9	Ken Yamamoto, Minoru Fujishima, Koichiro Hoh	Optimization of shield structures in analog integrated circuits.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
9	Mohamed A. Elgamel, Kannan S. Tharmalingam, Magdy A. Bayoumi	Noise-constrained interconnect optimization for nanometer technologies.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
9	Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas	Bounding the efforts on congestion optimization for physical synthesis.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	optimization, logic synthesis, physical design, technology mapping, routing congestion
9	Javier Jaén Martínez, Isidro Ramos	A Conceptual Model for Context-Aware Dynamic Architectures.	ICDCS Workshops	2003	DBLP DOI BibTeX RDF
9	Mehdi Baradaran Tahoori, Subhasish Mitra	Automatic Configuration Generation for FPGA Interconnect Testing.	VTS	2003	DBLP DOI BibTeX RDF
9	Pete Docter	Cheating, deceit and sleight-of-hand: how to create good character animation.	SI3D	2003	DBLP DOI BibTeX RDF
9	Luigi Francesco Agnati, Letizia Santarossa, Susanna Genedani, Enric I. Canela, Giuseppina Leo, Rafael Franco, Amina Woods, Carmen Lluis, Sergi Ferré, Kjell Fuxe	On the Nested Hierarchical Organization of CNS: Basic Characteristics of Neuronal Molecular Networks.	Summer School on Neural Networks	2003	DBLP DOI BibTeX RDF
9	Willi Geiselmann, Rainer Steinwandt	Hardware to Solve Sparse Systems of Linear Equations over GF(2).	CHES	2003	DBLP DOI BibTeX RDF
9	Kiarash Mahdavi, Mark Harman, Robert M. Hierons	A Multiple Hill Climbing Approach to Software Module Clustering.	ICSM	2003	DBLP DOI BibTeX RDF	Module clustering, Hill climbing, Search based software engineering
9	Hrishikesh J. Goradia, José M. Vidal	Building Blocks for Agent Design.	AOSE	2003	DBLP DOI BibTeX RDF
9	Partha Pratim Pande, Cristian Grecu, André Ivanov	High-Throughput Switch-Based Interconnect for Future SoCs.	IWSOC	2003	DBLP DOI BibTeX RDF	SoC, Wormhole Routing, Virtual Channels, Interconnect Architecture
9	Baruch Awerbuch, Tripurari Singh	An Online Algorithm for the Dynamic Maximal Dense Tree Problem.	Algorithmica	2002	DBLP DOI BibTeX RDF	Dense tree, Multicast, Dynamic, Online algorithms
9	José Flich, Pedro López 0001, Manuel P. Malumbres, José Duato	Boosting the Performance of Myrinet Networks.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF
9	José Flich, Pedro López 0001, Manuel P. Malumbres, José Duato	Boosting the Performance of Myrinet Networks.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	performance evaluation, Networks of workstations, wormhole switching, source routing, minimal routing
9	Minghorng Lai, Martin D. F. Wong	Maze routing with buffer insertion and wiresizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
9	Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje	An analysis of the wire-load model uncertainty problem.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
9	Ki-Seok Chung, Rajesh K. Gupta 0001, Taewhan Kim, C. L. Liu 0001	Synthesis and Optimization of Combinational Interface Circuits.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	embedded systems, logic circuit, interface synthesis
9	Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama	High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph.	ISVLSI	2002	DBLP DOI BibTeX RDF	FPGA, Reconfigurable processor, Two-dimensional array, Bit-serial architecture
9	Steven Hsu, Shih-Lien Lu, Shih-Chang Lai, Ram Krishnamurthy 0001, Konrad Lai	Dynamic addressing memory arrays with physical locality.	MICRO	2002	DBLP DOI BibTeX RDF
9	Edwin H. L. Ho, Peter C. Y. Chen	Implementation of logical control for a robotic workcell.	ICARCV	2002	DBLP DOI BibTeX RDF
9	Chin-Chih Chang, Jason Cong, David Zhigang Pan	Physical hierarchy generation with routing congestion control.	ISPD	2002	DBLP DOI BibTeX RDF	routing, interconnect, placement, hierarchy, congestion, physical, deep sub-micron
9	Andrea Pacelli	A local circuit topology for inductive parasitics.	ICCAD	2002	DBLP DOI BibTeX RDF
9	Prabhakar Kudva, Andrew Sullivan, William E. Dougherty	Metrics for structural logic synthesis.	ICCAD	2002	DBLP DOI BibTeX RDF
9	Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou 0001	Track assignment: a desirable intermediate step between global routing and detailed routing.	ICCAD	2002	DBLP DOI BibTeX RDF
9	Muzammil Iqbal, Ahmed Sharkawy, Usman Hameed, Phillip Christie	Stochastic wire length sampling for cycle time estimation.	SLIP	2002	DBLP DOI BibTeX RDF	cycle time estimates, wire sampling, performance modeling, physical design
9	Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng	Physical Planning Of On-Chip Interconnect Architectures.	ICCD	2002	DBLP DOI BibTeX RDF
9	Chung-Seok (Andy) Seo, Abhijit Chatterjee	A CAD Tool for System-on-Chip Placement and Routing with Free-Space Optical Interconnect.	ICCD	2002	DBLP DOI BibTeX RDF
9	Tuomas Valtonen, Tero Nurmi, Jouni Isoaho, Hannu Tenhunen	Interconnection of autonomous error-tolerant cells.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
9	Shih-Hsu Huang, Chu-Liao Wang	An effective floorplan-based power distribution network design methodology under reliability constraints.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
9	Peter Kornerup	Reviewing 4-to-2 Adders for Multi-Operand Addition.	ASAP	2002	DBLP DOI BibTeX RDF
9	Himanshu Kaul, Dennis Sylvester	Transition Aware Global Signaling (TAGS).	ISQED	2002	DBLP DOI BibTeX RDF
9	Abby A. Ilumoka	Chip Level Signal Integrity Analysis & Crosstalk Prediction Using Artificial Neural Nets.	ISQED	2002	DBLP DOI BibTeX RDF
9	Nicholas J. Macias, Lisa J. K. Durbeck	Self-Assembling Circuits with Autonomous Fault Handling.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
9	Jingcao Hu, Yangdong Deng, Radu Marculescu	System-Level Point-to-Point Communication Synthesis using Floorplanning Information.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	System-leve design, low-power, floorplanning, Communication synthesis, point-to-point communication
9	Himanshu Kaul, Dennis Sylvester, David T. Blaauw	Active shielding of RLC global interconnects.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
9	Raguraman Venkatesan, Jeffrey A. Davis, James D. Meindl	A physical model for the transient response of capacitively loaded distributed rlc interconnects.	DAC	2002	DBLP DOI BibTeX RDF	distributed rlc lines, overshoot, interconnects, crosstalk, time delay, repeaters, transient response
9	H. Bernhard Pogge	The next chip challenge: effective methods for viable mixed technology SoCs.	DAC	2002	DBLP DOI BibTeX RDF	SoCs (System on a Chip), chip fabrication methods, chip subsector concepts, chip/packing integration
9	Phillip J. Restle, Albert E. Ruehli, Steven G. Walker, George Papadopoulos	Full-wave PEEC time-domain method for the modeling of on-chipinterconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
9	Ding-Ming Kwai, Behrooz Parhami	Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector Quantization.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	control scalability, data-driven control, pipelined implementation, image compression, systolic array, vector quantization, VLSI architecture
9	John Leaney, David Rowe, Tim O'Neill, Steve Hoye, Petros Gionis	Measuring the Effectiveness of Computer Based Systems: An Open System Measurement Example.	ECBS	2001	DBLP DOI BibTeX RDF
9	Joseph A. Paradiso, Mark Feldmeier	A Compact, Wireless, Self-Powered Pushbutton Controller.	UbiComp	2001	DBLP DOI BibTeX RDF
9	Paul M. B. Vitányi	The Quantum Computing Challenge.	Informatics	2001	DBLP DOI BibTeX RDF
9	Wing Seung Yuen, Fung Yu Young	Slicing floorplan with clustering constraints.	ASP-DAC	2001	DBLP DOI BibTeX RDF
9	Simon Knowles	A Family of Adders.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
9	Kenneth Mackenzie, Eric Hudson, Drew Maule, Sundaresan Jayaraman, Sungmee Park	A prototype network embedded in textile fabric.	CASES	2001	DBLP DOI BibTeX RDF
9	Hanspeter Schmid	The current-feedback OTA.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
9	Tsutomu Yamaoki, Satoshi Taoka, Toshimasa Watanabe	Extracting a planar spanning subgraph of a terminal-vertex graph by solving the independent set problem.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
9	Philip T. Cox, Baoming Song	A Formal Model for Component-Based Software.	HCC	2001	DBLP DOI BibTeX RDF
9	Paul Kartschoke, Shervin Hojat	Techniques that Improved the Timing Convergence of the Gekko PowerPC Microprocessor.	ISQED	2001	DBLP DOI BibTeX RDF
9	Michihiro Koibuchi, Akira Funahashi, Akiya Jouraku, Hideharu Amano	L-Turn Routing: An Adaptive Routing in Irregular Networks.	ICPP	2001	DBLP DOI BibTeX RDF
9	Christopher Metz 0001	On the Wire: IP-over-Satellite: Internet Connectivity Blasts Off.	IEEE Internet Comput.	2000	DBLP DOI BibTeX RDF
9	Qiang Chen, Jeffrey A. Davis, Payman Zarkesh-Ha, James D. Meindl	A compact physical via blockage model.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
9	Jae-dong Lee, Kenneth E. Batcher	Minimizing Communication in the Bitonic Sort.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	minimizing communication, parallel computing, sorting, sorting networks, omega networks, Bitonic sorting