Search results for "FPGA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
26	Devu Manikantan Shila, Vivek Venugopal	Design, implementation and security analysis of hardware trojan threats in FPGA (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
26	Monther Abusultan, Sunil P. Khatri	FPGA LUT design for wide-band dynamic voltage and frequency scaled operation (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
26	Yosi Ben-Asher, Jacob Gendel, Gadi Haber, Oren Segal, Yousef Shajrawi	1K manycore FPGA shared memory architecture for SOC (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
26	Wenyi Feng, Jonathan W. Greene, Kristofer Vorwerk, Val Pevzner, Arun Kundu	Rent's rule based FPGA packing for routability optimization.	FPGA	2014	DBLP DOI BibTeX RDF
26	Roshan Silwal, Mohammed Y. Niamat	Asynchronous physical unclonable function using FPGA-based self-timed ring oscillator (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
26	Jungwook Choi, Rob A. Rutenbar	Video-rate stereo matching using markov random field TRW-S inference on a hybrid CPU+FPGA computing platform.	FPGA	2013	DBLP DOI BibTeX RDF
26	Masakazu Hioki, Toshihiro Sekigawa, Tadashi Nakagawa, Hanpei Koike, Yohei Matsumoto, Takashi Kawanami, Toshiyuki Tsutsumi	Fully-functional FPGA prototype with fine-grain programmable body biasing.	FPGA	2013	DBLP DOI BibTeX RDF
26	Peng Chen 0004, Chao Wang 0003, Xi Li 0003, Xuehai Zhou	Acceleration of the long read mapping on a PC-FPGA architecture (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	Bruno da Silva 0001, An Braeken, Erik H. D'Hollander, Abdellah Touhafi, Jan G. Cornelis, Jan Lemeire	Performance and toolchain of a combined GPU/FPGA desktop (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	Jinsong Mao, Hao Zhou, Haijiang Ye, Jinmei Lai	FPGA bitstream compression and decompression using LZ and golomb coding (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	Hasan Baig, Jeong-A Lee	A novel run-time auto-reconfigurable FPGA architecture for fast fault recovery with backward compatibility (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	Eric S. Chung, Michael Papamichael, Gabriel Weisz, James C. Hoe	Cross-platform FPGA accelerator development using CoRAM and CONNECT.	FPGA	2013	DBLP DOI BibTeX RDF
26	Meng Yang 0013, Jiarong Tong, A. E. A. Almaini	Indirect connection aware attraction for FPGA clustering (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	Chia-Hsiang Chen, Shiming Song, Zhengya Zhang	An FPGA-based transient error simulator for evaluating resilient system designs (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	Yun Qu, Viktor K. Prasanna	Scalable high-throughput architecture for large balanced tree structures on FPGA (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	Chao Wang 0003, Xi Li 0003, Xuehai Zhou, Jim Martin 0001, Ray C. C. Cheung	Genome sequencing using mapreduce on FPGA with multiple hardware accelerators (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	Qian Zhao 0001, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi	A novel FPGA design framework with VLSI post-routing performance analysis (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	David Uliana, Krzysztof Kepa, Peter Athanas	FPGA-based HPC application design for non-experts (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	Seyyed Ahmad Razavi, Morteza Saheb Zamani	Improving bitstream compression by modifying FPGA architecture.	FPGA	2013	DBLP DOI BibTeX RDF
26	Andrew Love, Peter Athanas	FPGA meta-data management system for accelerating implementation time with incremental compilation (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	Yuxin Wang, Peng Li 0031, Peng Zhang 0007, Chen Zhang 0001, Jason Cong	Automatic multidimensional memory partitioning for FPGA-based accelerators (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	Sheng Wei 0001, Jason Xin Zheng, Miodrag Potkonjak	Low power FPGA design using post-silicon device aging (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	Christos Kyrkou, Christos-Savvas Bouganis, Theocharis Theocharides	FPGA-based acceleration of cascaded support vector machines for embedded applications (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	Michael J. Wirthlin, Joshua E. Jensen, Alex Wilson, William Howes, Shi-Jie Wen, Rick Wong	Placement of repair circuits for in-field FPGA repair.	FPGA	2013	DBLP DOI BibTeX RDF
26	Vivek Venugopal, Devu Manikantan Shila	Hardware acceleration of TEA and XTEA algorithms on FPGA, GPU and multi-core processors (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	Swapnil Haria, Viktor K. Prasanna	AutoMapper: an automated tool for optimal hardware resource allocation for networking applications on FPGA (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	Hao Wang, Jyh-Charn Liu	An FPGA based parallel architecture for music melody matching.	FPGA	2013	DBLP DOI BibTeX RDF
26	Jeremy Fowers, Greg Stitt	Dynafuse: dynamic dependence analysis for FPGA pipeline fusion and locality optimizations.	FPGA	2013	DBLP DOI BibTeX RDF
26	Zilong Wang, Sitao Huang, Lanjun Wang, Hao Li, Yu Wang 0002, Huazhong Yang	Accelerating subsequence similarity search based on dynamic time warping distance with FPGA.	FPGA	2013	DBLP DOI BibTeX RDF
26	Oluseyi A. Ayorinde, Benton H. Calhoun	Circuit optimizations to minimize energy in the global interconnect of a low-power-FPGA (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	Da Tong, Lu Sun, Kiran Kumar Matam, Viktor K. Prasanna	High throughput and programmable online trafficclassifier on FPGA.	FPGA	2013	DBLP DOI BibTeX RDF
26	Anh-Tuan Hoang, Takeshi Fujino	Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	Patrick Cooke, Jeremy Fowers, Lee Hunt, Greg Stitt	A high-performance, low-energy FPGA accelerator for correntropy-based feature tracking (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
26	Sai Rahul Chalamalasetti, Kevin T. Lim, Mitch Wright, Alvin AuYoung, Parthasarathy Ranganathan, Martin Margala	An FPGA memcached appliance.	FPGA	2013	DBLP DOI BibTeX RDF
26	Hui Yan Cheah, Suhaib A. Fahmy, Douglas L. Maskell, Chidamber Kulkarni	A lean FPGA soft processor built using a DSP block.	FPGA	2012	DBLP DOI BibTeX RDF
26	Minxi Jin, Tsutomu Maruyama	A real-time stereo vision system using a tree-structured dynamic programming on FPGA.	FPGA	2012	DBLP DOI BibTeX RDF
26	Scott Bailie, Miriam Leeser	Incremental clustering applied to radar deinterleaving: a parameterized FPGA implementation.	FPGA	2012	DBLP DOI BibTeX RDF
26	Matthias Hinkfoth, Enrico Heinrich, Sebastian Vorköper, Volker Kühn 0001, Ralf Salomon	X-ORCA: FPGA-based wireless localization in the sub-millimeter range.	FPGA	2012	DBLP DOI BibTeX RDF
26	Jason Xin Zheng, Miodrag Potkonjak	Securing netlist-level FPGA design through exploiting process variation and degradation.	FPGA	2012	DBLP DOI BibTeX RDF
26	Robert Kirchgessner, Greg Stitt, Alan D. George, Herman Lam	VirtualRC: a virtual FPGA platform for applications and tools portability.	FPGA	2012	DBLP DOI BibTeX RDF
26	Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer	Leveraging latency-insensitivity to ease multiple FPGA design.	FPGA	2012	DBLP DOI BibTeX RDF
26	Stefan Hadjis, Andrew Canis, Jason Helge Anderson, Jongsok Choi, Kevin Nam, Stephen Dean Brown, Tomasz S. Czajkowski	Impact of FPGA architecture on resource sharing in high-level synthesis.	FPGA	2012	DBLP DOI BibTeX RDF
26	Sameh W. Asaad, Ralph Bellofatto, Bernard Brezzo, Chuck Haymes, Mohit Kapur, Benjamin D. Parker, Thomas Roewer, Proshanta Saha, Todd Takken, José A. Tierno	A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation.	FPGA	2012	DBLP DOI BibTeX RDF
26	Yupeng Chen, Bertil Schmidt, Douglas L. Maskell	Accelerating short read mapping on an FPGA (abstract only).	FPGA	2012	DBLP DOI BibTeX RDF
26	Yong Fu, Chi Wang, Liguang Chen, Jinmei Lai	A novel full coverage test method for CLBs in FPGA (abstract only).	FPGA	2012	DBLP DOI BibTeX RDF
26	Yi-Hua E. Yang, Oguzhan Erdem, Viktor K. Prasanna	Scalable architecture for 135 GBPS IPv6 lookup on FPGA (abstract only).	FPGA	2012	DBLP DOI BibTeX RDF
26	Jesus Savage, Rodrigo Savage, Marco Morales-Aguirre, Ángel Fernando Kuri Morales	Adaptive FPGA-based robotics state machine architecture derived with genetic algorithms (abstract only).	FPGA	2012	DBLP DOI BibTeX RDF
26	Nathaniel H. Rollins, Michael J. Wirthlin	Reliability of a softcore processor in a commercial SRAM-based FPGA.	FPGA	2012	DBLP DOI BibTeX RDF
26	Haoran Li, Youn Sung Park, Zhengya Zhang	Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulation.	FPGA	2012	DBLP DOI BibTeX RDF
26	Warren Wai-Kit Shum, Jason Helge Anderson	Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power.	FPGA	2012	DBLP DOI BibTeX RDF
26	Chris C. Wang, Guy G. F. Lemieux	Parallel FPGA placement based on individual LUT placement (abstract only).	FPGA	2012	DBLP DOI BibTeX RDF
26	Charles Eric LaForest, John Gregory Steffan	OCTAVO: an FPGA-centric processor family.	FPGA	2012	DBLP DOI BibTeX RDF
26	Jianwen Chen, Jason Cong, Ming Yan 0006, Yi Zou	FPGA-accelerated 3D reconstruction using compressive sensing.	FPGA	2012	DBLP DOI BibTeX RDF
26	Samuel Bayliss, George A. Constantinides	Optimizing SDRAM bandwidth for custom FPGA loop accelerators.	FPGA	2012	DBLP DOI BibTeX RDF
26	Chih-Hsun Chou, Fong Pong, Nian-Feng Tzeng	Speedy FPGA-based packet classifiers with low on-chip memory requirements.	FPGA	2012	DBLP DOI BibTeX RDF
26	Anh-Tuan Hoang, Takeshi Fujino	Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA.	FPGA	2012	DBLP DOI BibTeX RDF
26	Sundaram Ananthanarayanan, Chirag Ravishankar, Siddharth Garg, Andrew A. Kennings	EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only).	FPGA	2012	DBLP DOI BibTeX RDF
26	Eric S. Chung, Michael Papamichael, Gabriel Weisz, James C. Hoe, Ken Mai	Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing.	FPGA	2012	DBLP DOI BibTeX RDF
26	Wei Ting Loke, Yajun Ha	Power-aware FPGA technology mapping for programmable-VT architectures (abstract only).	FPGA	2012	DBLP DOI BibTeX RDF
26	Jason Cong, Yi Zou	Resolving implicit barrier synchronizations in FPGA HLS (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
26	Lu Zhang 0018, Ke Zhang 0012, Tian Sheuan Chang, Gauthier Lafruit, Georgi Krasimirov Kuzmanov, Diederik Verkest	Real-time high-definition stereo matching on FPGA.	FPGA	2011	DBLP DOI BibTeX RDF
26	Haohuan Fu, Robert G. Clapp	Eliminating the memory bottleneck: an FPGA-based solution for 3d reverse time migration.	FPGA	2011	DBLP DOI BibTeX RDF
26	David Grant, Chris C. Wang, Guy G. Lemieux	A CAD framework for Malibu: an FPGA with time-multiplexed coarse-grained elements.	FPGA	2011	DBLP DOI BibTeX RDF
26	Juergen Ributzka, Yuhei Hayashi, Fei Chen, Guang R. Gao	DEEP: an iterative fpga-based many-core emulation system for chip verification and architecture research.	FPGA	2011	DBLP DOI BibTeX RDF
26	Mingjie Lin, Shaoyi Cheng, John Wawrzynek	Using many-core architectural templates for FPGA-based computing (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
26	Jonathan W. Greene, Sinan Kaptanoglu, Wenyi Feng, Volker Hecht, Joel Landry, Fei Li 0003, Anton Krouglyanskiy, Mihai Morosan, Val Pevzner	A 65nm flash-based FPGA fabric optimized for low cost and power.	FPGA	2011	DBLP DOI BibTeX RDF
26	Hossein Omidian Savarbaghi, Kia Bazargan	FPGA placement by graph isomorphism (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
26	Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan	An FPGA implementation of a sparse quadratic programming solver for constrained predictive control.	FPGA	2011	DBLP DOI BibTeX RDF
26	Hock Soon Low, Delong Shang, Fei Xia, Alexandre Yakovlev	Variation tolerant asynchronous FPGA (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
26	Scott Y. L. Chin, Steven J. E. Wilton	Towards scalable FPGA CAD through architecture.	FPGA	2011	DBLP DOI BibTeX RDF
26	Andrew W. Hill, Andrea Di Blas, Richard Hughey	FPGA-based fine-grain parallel computing (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
26	Hoang Le, Thilan Ganegedara, Viktor K. Prasanna	Memory-efficient and scalable virtual routers using FPGA.	FPGA	2011	DBLP DOI BibTeX RDF
26	Yu Cai 0001, Erich F. Haratsch, Mark P. McCartney, Mudit Bhargava, Ken Mai	FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
26	Andrei Hagiescu, Weng-Fai Wong	Co-synthesis of FPGA-based application-specific floating point simd accelerators.	FPGA	2011	DBLP DOI BibTeX RDF
26	Ji Sun, Ray Bittner, Ken Eguro	FPGA side-channel receivers.	FPGA	2011	DBLP DOI BibTeX RDF
26	Fadi Obeidat, Robert H. Klenke	Microblaze: an application-independent fpga-based profiler (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
26	Trung Hieu Bui, Tuan Duy Anh Nguyen, Ngoc Thinh Tran	BBFEX: a bloom-bloomier filter extension for long patterns in FPGA-based pattern matching system (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
26	Haile Yu, Qiang Xu 0001, Philip Heng Wai Leong	On timing yield improvement for FPGA designs using architectural symmetry (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
26	Jianfeng Zhu 0001, Dong Wu, Yaru Yan, Xiao Yu, Hu He 0001, Liyang Pan	A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
26	Srinidhi Kestur, Dharav Dantara, Vijaykrishnan Narayanan	A streaming FPGA implementation of a steerable filter for real-time applications (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
26	Charles Lo, Paul Chow	Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded MPI.	FPGA	2011	DBLP DOI BibTeX RDF
26	Christopher W. Fletcher, Ilia A. Lebedev, Narges Bani Asadi, Daniel Burke, John Wawrzynek	Bridging the GPGPU-FPGA efficiency gap.	FPGA	2011	DBLP DOI BibTeX RDF
26	Henry Wong, Vaughn Betz, Jonathan Rose	Comparing FPGA vs. custom cmos and the impact on processor microarchitecture.	FPGA	2011	DBLP DOI BibTeX RDF
26	Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski	LegUp: high-level synthesis for FPGA-based processor/accelerator systems.	FPGA	2011	DBLP DOI BibTeX RDF
26	Justin S. J. Wong, Peter Y. K. Cheung	Improved delay measurement method in FPGA based on transition probability.	FPGA	2011	DBLP DOI BibTeX RDF
26	Abhay Tavaragiri, Jacob Couch, Peter Athanas	Exploration of FPGA interconnect for the design of unconventional antennas.	FPGA	2011	DBLP DOI BibTeX RDF
26	Xun Chen, Jianwen Zhu	Regular fabric for regular FPGA (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
26	John Wawrzynek	Should the academic community launch an open-source FPGA device and tools effort?: evening panel.	FPGA	2011	DBLP DOI BibTeX RDF
26	Peter Grossmann, Miriam Leeser	A prototype FPGA for subthreshold-optimized CMOS (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
26	Steven Trimberger, Jason Moore, Weiguang Lu	Authenticated encryption for FPGA bitstreams.	FPGA	2011	DBLP DOI BibTeX RDF
26	Joydip Das, Steven J. E. Wilton	An analytical model relating FPGA architecture parameters to routability.	FPGA	2011	DBLP DOI BibTeX RDF
26	Eric S. Chung, James C. Hoe, Ken Mai	CoRAM: an in-fabric memory architecture for FPGA-based computing.	FPGA	2011	DBLP DOI BibTeX RDF
26	Jeffrey M. Carver, Richard Neil Pittman, Alessandro Forin	Automatic bus macro placement for partially reconfigurable FPGA designs.	FPGA	2009	DBLP DOI BibTeX RDF	emips, reconfigurable computing, dynamic partial reconfiguration, floor-planning
26	David B. Thomas, Wayne Luk	FPGA-optimised high-quality uniform random number generators.	FPGA	2008	DBLP DOI BibTeX RDF	generation, random, number
26	Zied Marrakchi, Hayder Mrabet, Habib Mehrez	Configuration tools for a new multilevel hierarchical FPGA.	FPGA	2006	DBLP DOI BibTeX RDF
26	Akhilesh Kumar, Mohab Anis	Dual-Vt FPGA design for leakage power reduction (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
26	Stéphane Simard, Rachid Beguenane, Éric Larouche, Luc Morin	A 2005 review of FPGA arithmetic (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
26	Jianchun Li, Christos A. Papachristou, Raj Shekhar	Accelerating mutual information-based 3D medical image registration with An FPGA computing platform (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
26	Christopher C. Doss, Robert L. Riley Jr.	FPGA-based implementation of single-precision exponential unit.	FPGA	2004	DBLP DOI BibTeX RDF
26	A. Manoj Kumar, B. Jayaram 0002, V. Kamakoti 0001	SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis.	FPGA	2004	DBLP DOI BibTeX RDF