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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 908 occurrences of 401 keywords
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Results
Found 1076 publication records. Showing 1076 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Bogong Su, Wei Zhao, Zhizhong Tang, Stanley Habib |
A VLIW architecture for optimal execution of branch-intensive loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 25th Annual International Symposium on Microarchitecture, Portland, Oregon, USA, November 1992, pp. 119-124, 1992, ACM / IEEE Computer Society, 0-8186-3175-9. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
16 | G. Menez, Michel Auguin, Fernand Boéri, C. Carrière |
Automatic generation of architectural models for designing dedicated VLIW signal processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: 1992 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '92, San Francisco, California, USA, March 23-26, 1992, pp. 541-544, 1992, IEEE Computer Society, 0-7803-0532-9. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
16 | Carrie J. Brownhill, Alexandru Nicolau |
A Hierarchical Parallelizing Compiler for VLIW/MIMD Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 5th International Workshop, New Haven, Connecticut, USA, August 3-5, 1992, Proceedings, pp. 49-63, 1992, Springer, 3-540-57502-2. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
16 | Krste Asanovic, James Beck, Brian Kingsbury, Phil Kohn, Nelson Morgan, John Wawrzynek |
SPERT: a VLIW/SIMD microprocessor for artificial neural network computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: Application Specific Array Processors, ASAP 1992, Proceedings of the International Conference on, Berkeley, CA, USA, 4-7 August, 1992, pp. 178-190, 1992, IEEE, 0-8186-2967-3. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
16 | John G. Holm, Prithviraj Banerjee |
Low Cost Concurrent Error Detection in a VLIW Architecture Using Replicated Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP (1) ![In: Proceedings of the 1992 International Conference on Parallel Processing, University of Michigan, An Arbor, Michigan, USA, August 17-21, 1992. Volume I: Architecture., pp. 192-195, 1992, CRC Press, 0-8493-0781-3. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP BibTeX RDF |
|
16 | Arthur Abnous, Nader Bagherzadeh |
Pipelining and bypassing in a VLIW processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, Australia, May 1992, pp. 434, 1992, ACM, 0-89791-509-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
16 | Michael Werner |
Implementierung von Algorithmen zut Kompaktifizierung von Programmen für VLIW-Architekturen ![Search on Bibsonomy](Pics/bibsonomy.png) |
Forschungsberichte, TU Munich ![In: Forschungsberichte, TU Munich TUM I 9116, pp. 1-187, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
RDF |
|
16 | Gerben Essink, Emile H. L. Aarts, R. van Dongen, Piet J. van Gerwen, Jan H. M. Korst, Kees A. Vissers |
Architecture and Programming of a VLIW Style Programmable Video Signal Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 24, Albuquerque, New Mexico, USA, November 18-20, 1991, pp. 181-188, 1991, ACM/IEEE, 0-89791-460-0. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
16 | Arthur Abnous, Nader Bagherzadeh |
Special Features of a VLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: The Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30 - May 2, 1991., pp. 224-227, 1991, IEEE Computer Society, 0-8186-9167-0. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
16 | Arthur Abnous, Roni Potasman, Nader Bagherzadeh, Alexandru Nicolau |
A Percolation Based VLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP (1) ![In: Proceedings of the International Conference on Parallel Processing, ICPP '91, Austin, Texas, USA, August 1991. Volume I: Architecture/Hardware., pp. 144-148, 1991, CRC Press. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
16 | Hester Bakewell, Donna J. Quammen, Pearl Y. Wang |
Mapping Concurrent Programs to VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the Third ACM SIGPLAN Symposium on Principles & Practice of Parallel Programming (PPOPP), Williamsburg, Virginia, USA, April 21-24, 1991, pp. 21-27, 1991, ACM, 0-89791-390-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
OCCAM |
16 | Andrew Wolfe, John Paul Shen |
A Variable Instruction Stream Extension to the VLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-IV Proceedings - Forth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, California, USA, April 8-11, 1991., pp. 2-14, 1991, ACM Press, 0-89791-380-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
16 | Franco Gasperoni |
Scheduling for Horizontal Systems: The VLIW Paradigm in Persepctive. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1991 |
RDF |
|
16 | Günter Böckle, Siegfried Trosch |
A simulator for VLIW architectures ![Search on Bibsonomy](Pics/bibsonomy.png) |
Forschungsberichte, TU Munich ![In: Forschungsberichte, TU Munich TUM A 9016, pp. 1-50, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
RDF |
|
16 | W. Schenk |
A high speed prolog implementation on a VLIW processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocessing and Microprogramming ![In: Microprocessing and Microprogramming 27(1-5), pp. 601-605, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
16 | Henry G. Dietz, Thomas Schwederski, Matthew T. O'Keefe, Abderrazek Zaafrani |
Static synchronization beyond VLIW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings Supercomputing '89, Reno, NV, USA, November 12-17, 1989, pp. 416-425, 1989, ACM, 0-89791-341-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
16 | Robert P. Colwell, Robert P. Nix, John J. O'Donnell, David B. Papworth, Paul K. Rodman |
A VLIW Architecure for a Trace Scheduling Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(8), pp. 967-979, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
16 | Lothar Nowak |
SAMP: A General Purpose Processor Based on a Self-Timed VLIW Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architektur und Betrieb vpn Rechensystemen, 10. GI/ITG-Fachtagung, 9.-11. März 1988, Paderborn, Germany, Proceedings, pp. 381-390, 1988, Springer, 3-540-18994-7. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
16 | Lothar Nowak |
SAMP: a general purpose processor based on a self-timed VLIW structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 15(4), pp. 32-39, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
16 | Joseph A. Fisher |
The VLIW Machine: A Multiprocessor for Compiling Scientific Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 17(7), pp. 45-53, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
|
16 | Joseph A. Fisher, John J. O'Donnell |
VLIW Machines: Multiprocessors We Can Acutally Program. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPCON ![In: COMPCON'84, Digest of Papers, Twenty-Eighth IEEE Computer Society International Conference, San Francisco, California, USA, February 27 - March 1, 1984, pp. 299-305, 1984, IEEE Computer Society, 0-8186-0525-1. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP BibTeX RDF |
|
14 | Ying Zhang 0016, Yue Hu, Bin Li 0008, Lu Peng 0001 |
Performance and Power Analysis of ATI GPU: A Statistical Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAS ![In: Sixth International Conference on Networking, Architecture, and Storage, NAS 2011, Dalian, China, 28-30 July, 2011, pp. 149-158, 2011, IEEE Computer Society, 978-1-4577-1172-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
model, performance, GPU, power, VLIW, OPENCL |
14 | Qianming Yang, Nan Wu 0003, Mei Wen, Yi He 0008, Huayou Su, Chunyuan Zhang |
SAT: A Stream Architecture Template for Embedded Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: 10th IEEE International Conference on Computer and Information Technology, CIT 2010, Bradford, West Yorkshire, UK, June 29-July 1, 2010, pp. 1711-1718, 2010, IEEE Computer Society, 978-0-7695-4108-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
clustered-VLIW, template, stream processing |
14 | Praveen Raghavan, Murali Jayapala, Andy Lambrechts, Javed Absar, Francky Catthoor |
Playing the trade-off game: Architecture exploration using Coffeee. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(3), pp. 36:1-36:37, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
design, embedded systems, Energy, VLIW, processors, power estimation, loop transformations, architecture exploration, area, power-performance trade-off, compiler-architecture interaction |
14 | Nachiket Kapre, André DeHon |
Accelerating SPICE Model-Evaluation using FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: FCCM 2009, 17th IEEE Symposium on Field Programmable Custom Computing Machines, Napa, California, USA, 5-7 April 2009, Proceedings, pp. 37-44, 2009, IEEE Computer Society, 978-0-7695-3716-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Analog Circuit Simulator, VLIW Scheduling, Floating-Point, Spice, Loop Unrolling, Spatial Computation |
14 | Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. Wouters, Andreas Kanstein, Steven Dupont |
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 51(3), pp. 225-243, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
H.264/AVC decoder, FPGA, multimedia, embedded system, reconfigurable architecture, VLIW |
14 | Tingting Sha, Milo M. K. Martin, Amir Roth |
NoSQ: Store-Load Communication without a Store Queue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(1), pp. 106-113, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
microarchitecture, RISC, pipeline processors, VLIW architectures, CISC |
14 | Leipo Yan, Thambipillai Srikanthan, Niu Gang |
Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'06), Ottawa, Ontario, Canada, June 14-16, 2006, pp. 182-188, 2006, ACM, 1-59593-362-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
CGRA, VLIW, hardware/software partitioning, delay estimation, area estimation |
14 | Sumeet Kumar, Aneesh Aggarwal |
Self-checking instructions: reducing instruction redundancy for concurrent error detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 64-73, 2006, ACM, 1-59593-264-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
RISC/CISC, reducing instruction redundancy, redundant multi-threading, self-checking instructions, concurrent error detection, VLIW architectures |
14 | Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran, Aleksandar Ignjatovic |
Application specific forwarding network and instruction encoding for multi-pipe ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 241-246, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
multi-pipe ASIP, VLIW, forwarding, instruction encoding |
14 | Yu-Kuen Lai, Gregory T. Byrd |
High-throughput sketch update on a low-power stream processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2006, San Jose, California, USA, December 3-5, 2006, pp. 123-132, 2006, ACM, 1-59593-580-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
sketch, SIMD, network processors, VLIW, data stream processing, stream architecture |
14 | Chidamber Kulkarni, C. Ghez, Miguel Miranda, Francky Catthoor, Hugo De Man |
Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(1), pp. 76-81, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
RISC/CISC, VLIW architectures, VLSI systems |
14 | Esther Salamí, Mateo Valero |
Dynamic memory interval test vs. interprocedural pointer analysis in multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 2(2), pp. 199-219, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
multimedia, VLIW, Memory disambiguation |
14 | Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers |
IEEE-Compliant IDCT on FPGA-Augmented TriMedia. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 39(3), pp. 195-212, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
inverse discrete cosine transform, field-programmable gate array, configurable computing, VLIW processor |
14 | Noureddine Chabini, Wayne H. Wolf |
An approach for integrating basic retiming and software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: EMSOFT 2004, September 27-29, 2004, Pisa, Italy, Fourth ACM International Conference On Embedded Software, Proceedings, pp. 287-296, 2004, ACM, 1-58113-860-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
embedded systems, system-on-chip, timings, instruction-level parallelism, software pipelining, VLIW, retiming, superscalar processor, peak power, code size |
14 | Han-Saem Yun, Jihong Kim 0001, Soo-Mook Moon |
Time Optimal Software Pipelining of Loops with Control Flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 31(5), pp. 339-391, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
compiler optimization, instruction-level parallelism, software pipelining, VLIW |
14 | Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson, Hsien-Hsin S. Lee |
Predicate-Aware Scheduling: A Technique for Reducing Resource Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 23-26 March 2003, San Francisco, CA, USA, pp. 169-178, 2003, IEEE Computer Society, 0-7695-1913-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
predicate analysis, software pipelining, instruction scheduling, VLIW processor, resource utilization, predicated execution |
14 | Catherine H. Gebotys, Y. Zhang |
Security wrappers and power analysis for SoC technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003, pp. 162-167, 2003, ACM, 1-58113-742-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
security, performance, design, VLIW, adiabatic |
14 | Toshiyuki Ito, Kentaro Ono, Mayumi Ichikawa, Yuichi Okuyama, Kenichi Kuroda |
Reconfigurable Instruction-Level Parallel Processor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings, pp. 208-220, 2003, Springer, 3-540-20122-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
ILP Processor, PCA, dynamical reconfigurability, VLIW, self-reconfigurability |
14 | Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien |
Constructing and exploiting linear schedules with prescribed parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(1), pp. 159-172, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
multicluster VLIW, systolic array, Linear schedule |
14 | Han-Saem Yun, Jihong Kim 0001, Soo-Mook Moon |
Optimal software pipelining of loops with control flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 16th international conference on Supercomputing, ICS 2002, New York City, NY, USA, June 22-26, 2002, pp. 117-128, 2002, ACM, 1-58113-483-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
instruction-level parallelism, software pipelining, VLIW |
14 | Wu-chun Feng, Michael S. Warren, Eric Weigle |
Honey, I Shrunk the Beowulf! ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 31st International Conference on Parallel Processing (ICPP 2002), 20-23 August 2002, Vancouver, BC, Canada, pp. 141-150, 2002, IEEE Computer Society, 0-7695-1677-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
RLX, Transmeta, code morphing, NAS benchmarks, price-performance ratio, ToPPeR, performance-space ratio, performance-power ratio, n-body code, treecode, cluster, VLIW, Beowulf, blade server |
14 | Michael S. Warren, Eric Weigle, Wu-chun Feng |
High-density computing: a 240-processor Beowulf in one cubic meter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the 2002 ACM/IEEE conference on Supercomputing, Baltimore, Maryland, USA, November 16-22, 2002, CD-ROM, pp. 45:1-45:11, 2002, IEEE Computer Society, 0-7695-1524-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
MIPS-per-watt, RLX, Transmeta, code morphing, performance-per-square-foot, cluster, VLIW, Beowulf, blade server |
14 | Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck |
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 338-344, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
coarse grained logic, code generation, software pipelining, vliw, reconfigurable processor, spatial computation |
14 | Wu-chun Feng, Michael S. Warren, Eric Weigle |
The Bladed Beowulf: A Cost-Effective Alternative to Traditional Beowulf. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: 2002 IEEE International Conference on Cluster Computing (CLUSTER 2002), 23-26 September 2002, Chicago, IL, USA, pp. 245-, 2002, IEEE Computer Society, 0-7695-1745-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
RLX, Trans-meta, code morphing, price-performance ratio, performance-power ratio, performance-space ratio, ToPPeR, cluster, VLIW, Beowulf, blade server |
14 | G. X. Tyson, M. Smelyanskyi, Edward S. Davidson |
Evaluating the Use of Register Queues in Software Pipelined Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(8), pp. 769-783, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
modulo variable expansion, rotating register file, register queues, register connection, Software pipelining, VLIW |
14 | Theo Ungerer |
Mikroprozessoren - Stand der Technik und Forschungstrends. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inform. Spektrum ![In: Inform. Spektrum 24(1), pp. 3-15, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Mikroprozessor, superskalar, Befehlsebenen-, parallelität, mehrfädig, Kontrollfaden-, spekulation, VLIW, EPIC |
14 | Adrian Johnstone, Elizabeth Scott, Tim Womack |
Reverse Compilation for Digital Signal Processors: A Working Example. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 33rd Annual Hawaii International Conference on System Sciences (HICSS-33), 4-7 January, 2000, Maui, Hawaii, USA, 2000, IEEE Computer Society, 0-7695-0493-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
reverse compilation, VLIW architectures, DSP architectures |
14 | Joseph A. Fisher |
Customized Instruction-Sets for Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999., pp. 253-257, 1999, ACM Press. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
custom processors, mass customization of toolchains, instruction-level parallelism, VLIW, embedded processors |
14 | Tao Yu, Zhizhong Tang, Chihong Zhang, Jun Luo |
Control Mechanism for Software Pipelining on Nested Loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APDC ![In: Proceedings of the 1997 Advances in Parallel and Distributed Computing Conference (APDC '97), March 19-21, 1997, Shanghai, China, pp. 345-350, 1997, IEEE Computer Society, 0-8186-7876-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
ILSP, software pipelining, VLIW, dataflow, nested loop |
14 | Nelson L. Passos, Edwin Hsing-Mean Sha |
Achieving Full Parallelism Using Multidimensional Retiming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(11), pp. 1150-1163, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multidimensional data-flow graphs, instruction level parallelism, VLIW, Retiming, loop transformation, superscalar, nested loops |
14 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao |
A Framework for Resource-Constrained Rate-Optimal Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(11), pp. 1133-1149, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
superscalar and VLIW architectures, Instruction-level parallelism, integer linear programming, software pipelining, instruction scheduling |
14 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao |
Co-Scheduling Hardware and Software Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Second International Symposium on High-Performance Computer Architecture, San Jose, CA, USA, February 3-7, 1996, pp. 52-61, 1996, IEEE Computer Society, 0-8186-7237-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Classical Pipeline Theory, Software Pipelining, Pipeline Architecture, VLIW Architectures, Co-Scheduling |
14 | Peter Pfahler, Georg Piepenbrock |
A Comparison of Modulo Scheduling Techniques for Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 6th International Conference, CC'96, Linköping, Sweden, April 24-26, 1996, Proceedings, pp. 18-32, 1996, Springer, 3-540-61053-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Instruction Level Parallelism, Software Pipelining, VLIW, Superscalar Processors |
14 | Roger A. Bringmann, Scott A. Mahlke, Richard E. Hank, John C. Gyllenhaal, Wen-mei W. Hwu |
Speculative execution exception recovery using write-back suppression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 26th Annual International Symposium on Microarchitecture, Austin, Texas, USA, November 1993, pp. 214-223, 1993, ACM / IEEE Computer Society, 0-8186-5280-2. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
exception detection, exception recovery, scheduling, VLIW, speculative execution, superscalar |
14 | Richard E. Hank, Scott A. Mahlke, Roger A. Bringmann, John C. Gyllenhaal, Wen-mei W. Hwu |
Superblock formation using static program analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 26th Annual International Symposium on Microarchitecture, Austin, Texas, USA, November 1993, pp. 247-255, 1993, ACM / IEEE Computer Society, 0-8186-5280-2. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
optimization, VLIW, superscalar, static program analysis, superblock, code scheduling |
14 | William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu, Tokuzo Kiyohara, Pohua P. Chang |
Tolerating data access latency with register preloading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 6th international conference on Supercomputing, ICS 1992, Washington, DC, USA, July 19-24, 1992, pp. 104-113, 1992, ACM, 0-89791-485-6. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
VLIW/superscalar processor, load latency, register preload, register file, data dependence analysis |
14 | Alexandru Nicolau, Joseph A. Fisher |
Measuring the Parallelism Available for Very Long Instruction Word Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(11), pp. 968-976, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
VLIW (very long instruction word) architectures, Memory antialiasing, parallelism, multiprocessors, microcode, trace scheduling |
9 | Anja Niedermeier, Kjetil Svarstad, Frank Bouwens, Jos Hulzink, Jos Huisken |
The challenges of implementing fine-grained power gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 361-364, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
leakage power minimization, analysis, power management, register-transfer-level, power modeling, power gating |
9 | Srimat T. Chakradhar, Murugan Sankaradass, Venkata Jakkula, Srihari Cadambi |
A dynamically configurable coprocessor for convolutional neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 247-257, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dynamic reconfiguration, parallel computer architecture, convolutional neural networks |
9 | Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin |
Compiler-assisted soft error detection under performance and energy constraints in embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 8(4), pp. 27:1-27:30, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
instruction duplication, reliability, Embedded systems, compilers, energy consumption, soft errors |
9 | Narasinga Rao Miniskar, Elena Hammari, Satyakiran Munaga, Stylianos Mamagkakis, Per Gunnar Kjeldsberg, Francky Catthoor |
Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 48-57, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Stephen Friedman, Allan Carroll, Brian Van Essen, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck |
SPR: an architecture-adaptive CGRA mapping tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 191-200, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
modulo graph, spr, static sharing, clustering, scheduling, routing, placement, pathfinder |
9 | Guillermo Payá Vayá, Javier Martín-Langerwerf, Sören Moch, Peter Pirsch |
An Enhanced DMA Controller in SIMD Processors for Video Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2009, 22nd International Conference, Delft, The Netherlands, March 10-13, 2009. Proceedings, pp. 159-170, 2009, Springer, 978-3-642-00453-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
TotalProf: a fast and accurate retargetable source code profiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 305-314, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
source code profiling, architecture description language, performance estimation, instruction set simulation |
9 | Yanqin Yang, Meng Wang 0005, Zili Shao, Minyi Guo |
Dynamic Scratch-Pad Memory Management with Data Pipelining for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSE (2) ![In: Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, CSE 2009, Vancouver, BC, Canada, August 29-31, 2009, pp. 358-365, 2009, IEEE Computer Society, 978-1-4244-5334-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Martin Thuresson, Magnus Själander, Per Stenström |
A Flexible Code Compression Scheme Using Partitioned Look-Up Tables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings, pp. 95-109, 2009, Springer, 978-3-540-92989-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Xiaofeng Wu 0001, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger M. Goodall |
A Novel Delta Sigma Control System Processor and Its VLSI Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(3), pp. 217-228, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Nazish Aslam, Mark Milward, Ahmet T. Erdogan, Tughrul Arslan |
Code Compression and Decompression for Coarse-Grain Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(12), pp. 1596-1608, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | P. Dang |
High Performance Architecture of an Application Specific Processor for the H.264 Deblocking Filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(10), pp. 1321-1334, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Sami Khawam, Ioannis Nousias, Mark Milward, Ying Yi, Mark Muir, Tughrul Arslan |
The Reconfigurable Instruction Cell Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(1), pp. 75-85, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev |
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(2), pp. 31:1-31:21, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
hardware space exploration, embedded system design, Multiprocessor system-on-chip, real time analysis, electrocardiogram algorithms |
9 | Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis |
Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 50(2), pp. 179-200, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
coprocessor data-path, template units, kernels, performance improvements, design flow, energy reductions, architectural synthesis |
9 | Martino Sykora, Giovanni Agosta, Cristina Silvano |
Dynamic configuration of application-specific implicit instructions for embedded pipelined processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), Fortaleza, Ceara, Brazil, March 16-20, 2008, pp. 1509-1516, 2008, ACM, 978-1-59593-753-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
implicit issue, reconfiguration, pipelined architecture |
9 | Min Li 0001, Bruno Bougard, Weiyu Xu, David Novo, Liesbet Van der Perre, Francky Catthoor |
Optimizing Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 444-449, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Giacomo Paci, Axel Nackaerts, Francky Catthoor, Luca Benini, Paul Marchal |
How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 550-557, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Mark Hampton, Krste Asanovic |
Compiling for vector-thread architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Sixth International Symposium on Code Generation and Optimization (CGO 2008), April 5-9, 2008, Boston, MA, USA, pp. 205-215, 2008, ACM, 978-1-59593-978-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
compilers, code generation, vector processors |
9 | Min Li 0001, Bruno Bougard, Eduardo Lopez-Estraviz, André Bourdoux, David Novo, Liesbet Van der Perre, Francky Catthoor |
Selective Spanning with Fast Enumeration: A Near Maximum-Likelihood MIMO Detector Designed for Parallel Programmable Baseband Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: Proceedings of IEEE International Conference on Communications, ICC 2008, Beijing, China, 19-23 May 2008, pp. 737-741, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Yanqin Yang, Zili Shao, Linfeng Pan, Minyi Guo |
ISOS: Space Overlapping Based on Iteration Access Patterns for Dynamic Scratch-pad Memory Management in Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICYCS ![In: Proceedings of the 9th International Conference for Young Computer Scientists, ICYCS 2008, Zhang Jia Jie, Hunan, China, November 18-21, 2008, pp. 1360-1366, 2008, IEEE Computer Society, 978-0-7695-3398-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Kevin Williams 0001, Albert Noll, Andreas Gal, David Gregg |
Optimization strategies for a java virtual machine interpreter on the cell broadband engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 5th Conference on Computing Frontiers, 2008, Ischia, Italy, May 5-7, 2008, pp. 189-198, 2008, ACM, 978-1-60558-077-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
java, virtual machine, interpreter, language implementation |
9 | Bernd Becker 0001, Marc Herbstritt, Natalia Kalinnik, Matthew Lewis 0004, Juri Lichtner, Tobias Nopper, Ralf Wimmer 0001 |
Propositional approximations for bounded model checking of partial circuit designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 52-59, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Jun-Young Lee, Jae-Jin Lee, MooKyoung Jeong, Nak-Woong Eum, Seongmo Park |
A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3462-3465, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai |
Operation shuffling over cycle boundaries for low energy L0 clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 150-155, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Bita Gorjiara, Daniel Gajski |
Automatic architecture refinement techniques for customizing processing elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 379-384, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
GNR, nanocoded architectures, no-instruction-set computer (NISC), refinement, high-level synthesis, power, ASIP, datapath, netlist |
9 | Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee |
An Overview of a Compiler for Mapping Software Binaries to Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(11), pp. 1177-1190, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Samuel Williams 0001, John Shalf, Leonid Oliker, Shoaib Kamil 0001, Parry Husbands, Katherine A. Yelick |
Scientific Computing Kernels on the Cell Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 35(3), pp. 263-298, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
GEMM, SpMV, three level memory, FFT, sparse matrix, Cell processor, Stencil |
9 | Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai |
An Integrated Memory Array Processor for Embedded Image Recognition Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(5), pp. 622-634, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Parallel SIMD processor, memory array processor, image processing, image recognition, parallel language |
9 | Oscal T.-C. Chen, Li-Hsun Chen, Nai-Wei Lin, Chih-Chang Chen |
Application-Specific Data Path for Highly Efficient Computation of Multistandard Video Codecs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 17(1), pp. 26-42, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Xiaotong Zhuang, Santosh Pande |
Allocating architected registers through differential encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 29(2), pp. 9, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
architected register, differential encoding, Register allocation |
9 | Weihua Zhang, Tao Bao, Binyu Zang, Chuanqi Zhu |
Optimizing Bandwidth Constraint through Register Interconnection for Stream Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 434, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Anders Nilsson 0001, Dake Liu |
Area Efficient Fully Programmable Baseband Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings, pp. 333-342, 2007, Springer, 978-3-540-73622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Cyprian Grassmann, Mathias Richter, Mirko Sauermann |
Mapping the physical layer of radio standards to multiprocessor architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1412-1417, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | C. Arbelo, Andreas Kanstein, Sebastián López, José Francisco López, Mladen Berekovic, Roberto Sarmiento, Jean-Yves Mignolet |
Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 177-182, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Koen Van Renterghem, Pieter Demuytere, Dieter Verhulst, Jan Vandewege, Xing-Zhi Qiu |
Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1418-1423, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlke |
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 10-14 February 2007, Phoenix, Arizona, USA, pp. 25-36, 2007, IEEE Computer Society, 1-4244-0804-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Andrew Lines |
The Vortex: A Superscalar Asynchronous Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 12-14 March 2006, Berkeley, California, USA, pp. 39-48, 2007, IEEE Computer Society, 978-0-7695-2771-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Yong Li 0006, Zhiying Wang 0003, Kui Dai |
A Low-Power Application Specific Instruction Set Processor Using Asynchronous Function Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: Seventh International Conference on Computer and Information Technology (CIT 2007), October 16-19, 2007, University of Aizu, Fukushima, Japan, pp. 817-822, 2007, IEEE Computer Society, 978-0-7695-2983-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Min Li 0001, Javed Absar, Bruno Bougard, Liesbet Van der Perre, Francky Catthoor |
Systematic Optimization of Programmable QRD Implementation for Multiple Application Scenarios. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China, pp. 19-24, 2007, IEEE, 1-4244-1222-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Mahendra Kumar Angamuthu Ganesan, Sundeep Singh, Frank May, Jürgen Becker 0001 |
H.264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 467-471, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Alberto Gallini, Lorenzo Pavesi, Claudio Ferretti, Alberto Rosti, Sara Bocchio |
An Automatic Compilation Framework for Configurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 525-528, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
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