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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 908 occurrences of 401 keywords
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Results
Found 1076 publication records. Showing 1076 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Bogong Su, Wei Zhao, Zhizhong Tang, Stanley Habib |
A VLIW architecture for optimal execution of branch-intensive loops. |
MICRO |
1992 |
DBLP DOI BibTeX RDF |
|
16 | G. Menez, Michel Auguin, Fernand Boéri, C. Carrière |
Automatic generation of architectural models for designing dedicated VLIW signal processors. |
ICASSP |
1992 |
DBLP DOI BibTeX RDF |
|
16 | Carrie J. Brownhill, Alexandru Nicolau |
A Hierarchical Parallelizing Compiler for VLIW/MIMD Machines. |
LCPC |
1992 |
DBLP DOI BibTeX RDF |
|
16 | Krste Asanovic, James Beck, Brian Kingsbury, Phil Kohn, Nelson Morgan, John Wawrzynek |
SPERT: a VLIW/SIMD microprocessor for artificial neural network computations. |
ASAP |
1992 |
DBLP DOI BibTeX RDF |
|
16 | John G. Holm, Prithviraj Banerjee |
Low Cost Concurrent Error Detection in a VLIW Architecture Using Replicated Instructions. |
ICPP (1) |
1992 |
DBLP BibTeX RDF |
|
16 | Arthur Abnous, Nader Bagherzadeh |
Pipelining and bypassing in a VLIW processor. |
ISCA |
1992 |
DBLP DOI BibTeX RDF |
|
16 | Michael Werner |
Implementierung von Algorithmen zut Kompaktifizierung von Programmen für VLIW-Architekturen |
Forschungsberichte, TU Munich |
1991 |
RDF |
|
16 | Gerben Essink, Emile H. L. Aarts, R. van Dongen, Piet J. van Gerwen, Jan H. M. Korst, Kees A. Vissers |
Architecture and Programming of a VLIW Style Programmable Video Signal Processor. |
MICRO |
1991 |
DBLP DOI BibTeX RDF |
|
16 | Arthur Abnous, Nader Bagherzadeh |
Special Features of a VLIW Architecture. |
IPPS |
1991 |
DBLP DOI BibTeX RDF |
|
16 | Arthur Abnous, Roni Potasman, Nader Bagherzadeh, Alexandru Nicolau |
A Percolation Based VLIW Architecture. |
ICPP (1) |
1991 |
DBLP BibTeX RDF |
|
16 | Hester Bakewell, Donna J. Quammen, Pearl Y. Wang |
Mapping Concurrent Programs to VLIW Processors. |
PPoPP |
1991 |
DBLP DOI BibTeX RDF |
OCCAM |
16 | Andrew Wolfe, John Paul Shen |
A Variable Instruction Stream Extension to the VLIW Architecture. |
ASPLOS |
1991 |
DBLP DOI BibTeX RDF |
|
16 | Franco Gasperoni |
Scheduling for Horizontal Systems: The VLIW Paradigm in Persepctive. |
|
1991 |
RDF |
|
16 | Günter Böckle, Siegfried Trosch |
A simulator for VLIW architectures |
Forschungsberichte, TU Munich |
1990 |
RDF |
|
16 | W. Schenk |
A high speed prolog implementation on a VLIW processor. |
Microprocessing and Microprogramming |
1989 |
DBLP DOI BibTeX RDF |
|
16 | Henry G. Dietz, Thomas Schwederski, Matthew T. O'Keefe, Abderrazek Zaafrani |
Static synchronization beyond VLIW. |
SC |
1989 |
DBLP DOI BibTeX RDF |
|
16 | Robert P. Colwell, Robert P. Nix, John J. O'Donnell, David B. Papworth, Paul K. Rodman |
A VLIW Architecure for a Trace Scheduling Compiler. |
IEEE Trans. Computers |
1988 |
DBLP DOI BibTeX RDF |
|
16 | Lothar Nowak |
SAMP: A General Purpose Processor Based on a Self-Timed VLIW Structure. |
ARCS |
1988 |
DBLP DOI BibTeX RDF |
|
16 | Lothar Nowak |
SAMP: a general purpose processor based on a self-timed VLIW structure. |
SIGARCH Comput. Archit. News |
1987 |
DBLP DOI BibTeX RDF |
|
16 | Joseph A. Fisher |
The VLIW Machine: A Multiprocessor for Compiling Scientific Code. |
Computer |
1984 |
DBLP DOI BibTeX RDF |
|
16 | Joseph A. Fisher, John J. O'Donnell |
VLIW Machines: Multiprocessors We Can Acutally Program. |
COMPCON |
1984 |
DBLP BibTeX RDF |
|
14 | Ying Zhang 0016, Yue Hu, Bin Li 0008, Lu Peng 0001 |
Performance and Power Analysis of ATI GPU: A Statistical Approach. |
NAS |
2011 |
DBLP DOI BibTeX RDF |
model, performance, GPU, power, VLIW, OPENCL |
14 | Qianming Yang, Nan Wu 0003, Mei Wen, Yi He 0008, Huayou Su, Chunyuan Zhang |
SAT: A Stream Architecture Template for Embedded Applications. |
CIT |
2010 |
DBLP DOI BibTeX RDF |
clustered-VLIW, template, stream processing |
14 | Praveen Raghavan, Murali Jayapala, Andy Lambrechts, Javed Absar, Francky Catthoor |
Playing the trade-off game: Architecture exploration using Coffeee. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
design, embedded systems, Energy, VLIW, processors, power estimation, loop transformations, architecture exploration, area, power-performance trade-off, compiler-architecture interaction |
14 | Nachiket Kapre, André DeHon |
Accelerating SPICE Model-Evaluation using FPGAs. |
FCCM |
2009 |
DBLP DOI BibTeX RDF |
Analog Circuit Simulator, VLIW Scheduling, Floating-Point, Spice, Loop Unrolling, Spatial Computation |
14 | Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. Wouters, Andreas Kanstein, Steven Dupont |
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
H.264/AVC decoder, FPGA, multimedia, embedded system, reconfigurable architecture, VLIW |
14 | Tingting Sha, Milo M. K. Martin, Amir Roth |
NoSQ: Store-Load Communication without a Store Queue. |
IEEE Micro |
2007 |
DBLP DOI BibTeX RDF |
microarchitecture, RISC, pipeline processors, VLIW architectures, CISC |
14 | Leipo Yan, Thambipillai Srikanthan, Niu Gang |
Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures. |
LCTES |
2006 |
DBLP DOI BibTeX RDF |
CGRA, VLIW, hardware/software partitioning, delay estimation, area estimation |
14 | Sumeet Kumar, Aneesh Aggarwal |
Self-checking instructions: reducing instruction redundancy for concurrent error detection. |
PACT |
2006 |
DBLP DOI BibTeX RDF |
RISC/CISC, reducing instruction redundancy, redundant multi-threading, self-checking instructions, concurrent error detection, VLIW architectures |
14 | Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran, Aleksandar Ignjatovic |
Application specific forwarding network and instruction encoding for multi-pipe ASIPs. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
multi-pipe ASIP, VLIW, forwarding, instruction encoding |
14 | Yu-Kuen Lai, Gregory T. Byrd |
High-throughput sketch update on a low-power stream processor. |
ANCS |
2006 |
DBLP DOI BibTeX RDF |
sketch, SIMD, network processors, VLIW, data stream processing, stream architecture |
14 | Chidamber Kulkarni, C. Ghez, Miguel Miranda, Francky Catthoor, Hugo De Man |
Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
RISC/CISC, VLIW architectures, VLSI systems |
14 | Esther Salamí, Mateo Valero |
Dynamic memory interval test vs. interprocedural pointer analysis in multimedia applications. |
ACM Trans. Archit. Code Optim. |
2005 |
DBLP DOI BibTeX RDF |
multimedia, VLIW, Memory disambiguation |
14 | Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers |
IEEE-Compliant IDCT on FPGA-Augmented TriMedia. |
J. VLSI Signal Process. |
2005 |
DBLP DOI BibTeX RDF |
inverse discrete cosine transform, field-programmable gate array, configurable computing, VLIW processor |
14 | Noureddine Chabini, Wayne H. Wolf |
An approach for integrating basic retiming and software pipelining. |
EMSOFT |
2004 |
DBLP DOI BibTeX RDF |
embedded systems, system-on-chip, timings, instruction-level parallelism, software pipelining, VLIW, retiming, superscalar processor, peak power, code size |
14 | Han-Saem Yun, Jihong Kim 0001, Soo-Mook Moon |
Time Optimal Software Pipelining of Loops with Control Flows. |
Int. J. Parallel Program. |
2003 |
DBLP DOI BibTeX RDF |
compiler optimization, instruction-level parallelism, software pipelining, VLIW |
14 | Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson, Hsien-Hsin S. Lee |
Predicate-Aware Scheduling: A Technique for Reducing Resource Constraints. |
CGO |
2003 |
DBLP DOI BibTeX RDF |
predicate analysis, software pipelining, instruction scheduling, VLIW processor, resource utilization, predicated execution |
14 | Catherine H. Gebotys, Y. Zhang |
Security wrappers and power analysis for SoC technologies. |
CODES+ISSS |
2003 |
DBLP DOI BibTeX RDF |
security, performance, design, VLIW, adiabatic |
14 | Toshiyuki Ito, Kentaro Ono, Mayumi Ichikawa, Yuichi Okuyama, Kenichi Kuroda |
Reconfigurable Instruction-Level Parallel Processor Architecture. |
Asia-Pacific Computer Systems Architecture Conference |
2003 |
DBLP DOI BibTeX RDF |
ILP Processor, PCA, dynamical reconfigurability, VLIW, self-reconfigurability |
14 | Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien |
Constructing and exploiting linear schedules with prescribed parallelism. |
ACM Trans. Design Autom. Electr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
multicluster VLIW, systolic array, Linear schedule |
14 | Han-Saem Yun, Jihong Kim 0001, Soo-Mook Moon |
Optimal software pipelining of loops with control flows. |
ICS |
2002 |
DBLP DOI BibTeX RDF |
instruction-level parallelism, software pipelining, VLIW |
14 | Wu-chun Feng, Michael S. Warren, Eric Weigle |
Honey, I Shrunk the Beowulf! |
ICPP |
2002 |
DBLP DOI BibTeX RDF |
RLX, Transmeta, code morphing, NAS benchmarks, price-performance ratio, ToPPeR, performance-space ratio, performance-power ratio, n-body code, treecode, cluster, VLIW, Beowulf, blade server |
14 | Michael S. Warren, Eric Weigle, Wu-chun Feng |
High-density computing: a 240-processor Beowulf in one cubic meter. |
SC |
2002 |
DBLP DOI BibTeX RDF |
MIPS-per-watt, RLX, Transmeta, code morphing, performance-per-square-foot, cluster, VLIW, Beowulf, blade server |
14 | Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck |
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
coarse grained logic, code generation, software pipelining, vliw, reconfigurable processor, spatial computation |
14 | Wu-chun Feng, Michael S. Warren, Eric Weigle |
The Bladed Beowulf: A Cost-Effective Alternative to Traditional Beowulf. |
CLUSTER |
2002 |
DBLP DOI BibTeX RDF |
RLX, Trans-meta, code morphing, price-performance ratio, performance-power ratio, performance-space ratio, ToPPeR, cluster, VLIW, Beowulf, blade server |
14 | G. X. Tyson, M. Smelyanskyi, Edward S. Davidson |
Evaluating the Use of Register Queues in Software Pipelined Loops. |
IEEE Trans. Computers |
2001 |
DBLP DOI BibTeX RDF |
modulo variable expansion, rotating register file, register queues, register connection, Software pipelining, VLIW |
14 | Theo Ungerer |
Mikroprozessoren - Stand der Technik und Forschungstrends. |
Inform. Spektrum |
2001 |
DBLP DOI BibTeX RDF |
Mikroprozessor, superskalar, Befehlsebenen-, parallelität, mehrfädig, Kontrollfaden-, spekulation, VLIW, EPIC |
14 | Adrian Johnstone, Elizabeth Scott, Tim Womack |
Reverse Compilation for Digital Signal Processors: A Working Example. |
HICSS |
2000 |
DBLP DOI BibTeX RDF |
reverse compilation, VLIW architectures, DSP architectures |
14 | Joseph A. Fisher |
Customized Instruction-Sets for Embedded Processors. |
DAC |
1999 |
DBLP DOI BibTeX RDF |
custom processors, mass customization of toolchains, instruction-level parallelism, VLIW, embedded processors |
14 | Tao Yu, Zhizhong Tang, Chihong Zhang, Jun Luo |
Control Mechanism for Software Pipelining on Nested Loop. |
APDC |
1997 |
DBLP DOI BibTeX RDF |
ILSP, software pipelining, VLIW, dataflow, nested loop |
14 | Nelson L. Passos, Edwin Hsing-Mean Sha |
Achieving Full Parallelism Using Multidimensional Retiming. |
IEEE Trans. Parallel Distributed Syst. |
1996 |
DBLP DOI BibTeX RDF |
multidimensional data-flow graphs, instruction level parallelism, VLIW, Retiming, loop transformation, superscalar, nested loops |
14 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao |
A Framework for Resource-Constrained Rate-Optimal Software Pipelining. |
IEEE Trans. Parallel Distributed Syst. |
1996 |
DBLP DOI BibTeX RDF |
superscalar and VLIW architectures, Instruction-level parallelism, integer linear programming, software pipelining, instruction scheduling |
14 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao |
Co-Scheduling Hardware and Software Pipelines. |
HPCA |
1996 |
DBLP DOI BibTeX RDF |
Classical Pipeline Theory, Software Pipelining, Pipeline Architecture, VLIW Architectures, Co-Scheduling |
14 | Peter Pfahler, Georg Piepenbrock |
A Comparison of Modulo Scheduling Techniques for Software Pipelining. |
CC |
1996 |
DBLP DOI BibTeX RDF |
Instruction Level Parallelism, Software Pipelining, VLIW, Superscalar Processors |
14 | Roger A. Bringmann, Scott A. Mahlke, Richard E. Hank, John C. Gyllenhaal, Wen-mei W. Hwu |
Speculative execution exception recovery using write-back suppression. |
MICRO |
1993 |
DBLP DOI BibTeX RDF |
exception detection, exception recovery, scheduling, VLIW, speculative execution, superscalar |
14 | Richard E. Hank, Scott A. Mahlke, Roger A. Bringmann, John C. Gyllenhaal, Wen-mei W. Hwu |
Superblock formation using static program analysis. |
MICRO |
1993 |
DBLP DOI BibTeX RDF |
optimization, VLIW, superscalar, static program analysis, superblock, code scheduling |
14 | William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu, Tokuzo Kiyohara, Pohua P. Chang |
Tolerating data access latency with register preloading. |
ICS |
1992 |
DBLP DOI BibTeX RDF |
VLIW/superscalar processor, load latency, register preload, register file, data dependence analysis |
14 | Alexandru Nicolau, Joseph A. Fisher |
Measuring the Parallelism Available for Very Long Instruction Word Architectures. |
IEEE Trans. Computers |
1984 |
DBLP DOI BibTeX RDF |
VLIW (very long instruction word) architectures, Memory antialiasing, parallelism, multiprocessors, microcode, trace scheduling |
9 | Anja Niedermeier, Kjetil Svarstad, Frank Bouwens, Jos Hulzink, Jos Huisken |
The challenges of implementing fine-grained power gating. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
leakage power minimization, analysis, power management, register-transfer-level, power modeling, power gating |
9 | Srimat T. Chakradhar, Murugan Sankaradass, Venkata Jakkula, Srihari Cadambi |
A dynamically configurable coprocessor for convolutional neural networks. |
ISCA |
2010 |
DBLP DOI BibTeX RDF |
dynamic reconfiguration, parallel computer architecture, convolutional neural networks |
9 | Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin |
Compiler-assisted soft error detection under performance and energy constraints in embedded systems. |
ACM Trans. Embed. Comput. Syst. |
2009 |
DBLP DOI BibTeX RDF |
instruction duplication, reliability, Embedded systems, compilers, energy consumption, soft errors |
9 | Narasinga Rao Miniskar, Elena Hammari, Satyakiran Munaga, Stylianos Mamagkakis, Per Gunnar Kjeldsberg, Francky Catthoor |
Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study. |
SAMOS |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Stephen Friedman, Allan Carroll, Brian Van Essen, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck |
SPR: an architecture-adaptive CGRA mapping tool. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
modulo graph, spr, static sharing, clustering, scheduling, routing, placement, pathfinder |
9 | Guillermo Payá Vayá, Javier Martín-Langerwerf, Sören Moch, Peter Pirsch |
An Enhanced DMA Controller in SIMD Processors for Video Applications. |
ARCS |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
TotalProf: a fast and accurate retargetable source code profiler. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
source code profiling, architecture description language, performance estimation, instruction set simulation |
9 | Yanqin Yang, Meng Wang 0005, Zili Shao, Minyi Guo |
Dynamic Scratch-Pad Memory Management with Data Pipelining for Embedded Systems. |
CSE (2) |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Martin Thuresson, Magnus Själander, Per Stenström |
A Flexible Code Compression Scheme Using Partitioned Look-Up Tables. |
HiPEAC |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Xiaofeng Wu 0001, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger M. Goodall |
A Novel Delta Sigma Control System Processor and Its VLSI Implementation. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Nazish Aslam, Mark Milward, Ahmet T. Erdogan, Tughrul Arslan |
Code Compression and Decompression for Coarse-Grain Reconfigurable Architectures. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
9 | P. Dang |
High Performance Architecture of an Application Specific Processor for the H.264 Deblocking Filter. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Sami Khawam, Ioannis Nousias, Mark Milward, Ying Yi, Mark Muir, Tughrul Arslan |
The Reconfigurable Instruction Cell Array. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev |
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
hardware space exploration, embedded system design, Multiprocessor system-on-chip, real time analysis, electrocardiogram algorithms |
9 | Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis |
Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
coprocessor data-path, template units, kernels, performance improvements, design flow, energy reductions, architectural synthesis |
9 | Martino Sykora, Giovanni Agosta, Cristina Silvano |
Dynamic configuration of application-specific implicit instructions for embedded pipelined processors. |
SAC |
2008 |
DBLP DOI BibTeX RDF |
implicit issue, reconfiguration, pipelined architecture |
9 | Min Li 0001, Bruno Bougard, Weiyu Xu, David Novo, Liesbet Van der Perre, Francky Catthoor |
Optimizing Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Giacomo Paci, Axel Nackaerts, Francky Catthoor, Luca Benini, Paul Marchal |
How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Mark Hampton, Krste Asanovic |
Compiling for vector-thread architectures. |
CGO |
2008 |
DBLP DOI BibTeX RDF |
compilers, code generation, vector processors |
9 | Min Li 0001, Bruno Bougard, Eduardo Lopez-Estraviz, André Bourdoux, David Novo, Liesbet Van der Perre, Francky Catthoor |
Selective Spanning with Fast Enumeration: A Near Maximum-Likelihood MIMO Detector Designed for Parallel Programmable Baseband Architectures. |
ICC |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Yanqin Yang, Zili Shao, Linfeng Pan, Minyi Guo |
ISOS: Space Overlapping Based on Iteration Access Patterns for Dynamic Scratch-pad Memory Management in Embedded Systems. |
ICYCS |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Kevin Williams 0001, Albert Noll, Andreas Gal, David Gregg |
Optimization strategies for a java virtual machine interpreter on the cell broadband engine. |
Conf. Computing Frontiers |
2008 |
DBLP DOI BibTeX RDF |
java, virtual machine, interpreter, language implementation |
9 | Bernd Becker 0001, Marc Herbstritt, Natalia Kalinnik, Matthew Lewis 0004, Juri Lichtner, Tobias Nopper, Ralf Wimmer 0001 |
Propositional approximations for bounded model checking of partial circuit designs. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Jun-Young Lee, Jae-Jin Lee, MooKyoung Jeong, Nak-Woong Eum, Seongmo Park |
A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC decoder. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai |
Operation shuffling over cycle boundaries for low energy L0 clustering. |
ASAP |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Bita Gorjiara, Daniel Gajski |
Automatic architecture refinement techniques for customizing processing elements. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
GNR, nanocoded architectures, no-instruction-set computer (NISC), refinement, high-level synthesis, power, ASIP, datapath, netlist |
9 | Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee |
An Overview of a Compiler for Mapping Software Binaries to Hardware. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Samuel Williams 0001, John Shalf, Leonid Oliker, Shoaib Kamil 0001, Parry Husbands, Katherine A. Yelick |
Scientific Computing Kernels on the Cell Processor. |
Int. J. Parallel Program. |
2007 |
DBLP DOI BibTeX RDF |
GEMM, SpMV, three level memory, FFT, sparse matrix, Cell processor, Stencil |
9 | Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai |
An Integrated Memory Array Processor for Embedded Image Recognition Systems. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
Parallel SIMD processor, memory array processor, image processing, image recognition, parallel language |
9 | Oscal T.-C. Chen, Li-Hsun Chen, Nai-Wei Lin, Chih-Chang Chen |
Application-Specific Data Path for Highly Efficient Computation of Multistandard Video Codecs. |
IEEE Trans. Circuits Syst. Video Technol. |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Xiaotong Zhuang, Santosh Pande |
Allocating architected registers through differential encoding. |
ACM Trans. Program. Lang. Syst. |
2007 |
DBLP DOI BibTeX RDF |
architected register, differential encoding, Register allocation |
9 | Weihua Zhang, Tao Bao, Binyu Zang, Chuanqi Zhu |
Optimizing Bandwidth Constraint through Register Interconnection for Stream Processors. |
PACT |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Anders Nilsson 0001, Dake Liu |
Area Efficient Fully Programmable Baseband Processors. |
SAMOS |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Cyprian Grassmann, Mathias Richter, Mirko Sauermann |
Mapping the physical layer of radio standards to multiprocessor architectures. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
9 | C. Arbelo, Andreas Kanstein, Sebastián López, José Francisco López, Mladen Berekovic, Roberto Sarmiento, Jean-Yves Mignolet |
Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Koen Van Renterghem, Pieter Demuytere, Dieter Verhulst, Jan Vandewege, Xing-Zhi Qiu |
Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlke |
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications. |
HPCA |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Andrew Lines |
The Vortex: A Superscalar Asynchronous Processor. |
ASYNC |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Yong Li 0006, Zhiying Wang 0003, Kui Dai |
A Low-Power Application Specific Instruction Set Processor Using Asynchronous Function Units. |
CIT |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Min Li 0001, Javed Absar, Bruno Bougard, Liesbet Van der Perre, Francky Catthoor |
Systematic Optimization of Programmable QRD Implementation for Multiple Application Scenarios. |
SiPS |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Mahendra Kumar Angamuthu Ganesan, Sundeep Singh, Frank May, Jürgen Becker 0001 |
H.264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Alberto Gallini, Lorenzo Pavesi, Claudio Ferretti, Alberto Rosti, Sara Bocchio |
An Automatic Compilation Framework for Configurable Architectures. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
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