Search results for "interconnects"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Nian-Feng Tzeng	Multistage-Based Switching Fabrics for Scalable Routers.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	Line cards, multistage interconnects, queue speedups, recirculation connections, routing tags, scalability, routers, switching fabrics
15	Maurizio Martina, Guido Masera	A statistical model for estimating the effect of process variations on crosstalk noise.	SLIP	2004	DBLP DOI BibTeX RDF	statistical analysis, interconnects modeling
15	Maged Ghoneima, Yehea I. Ismail	Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses.	ISLPED	2004	DBLP DOI BibTeX RDF	low power, interconnects, buses, coupling capacitance
15	Angelos Bilas, Courtney R. Gibson, Reza Azimi, Rosalia Christodoulopoulou, Peter Jamieson	Using System Emulation to Model Next-Generation Shared Virtual Memory Clusters.	Clust. Comput.	2003	DBLP DOI BibTeX RDF	high-bandwidth interconnects, distributed shared memory, parallel systems, clusters of workstations, low-latency
15	Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu 0001, Anirudh Devgan	Closed form expressions for extending step delay and slew metrics to ramp inputs.	ISPD	2003	DBLP DOI BibTeX RDF	Elmore, slew, delay, timing, interconnects, PDF, moments, median, skewness
15	Thomas M. Warschko	ClusterWorX®: A Framework to Manage Large Clusters Effectively.	IPDPS	2003	DBLP DOI BibTeX RDF	LinuxBIOS, ICE Box™, ClusterWorX®, High-Performance Cluster Computing, High-Speed Interconnects, Cluster Management
15	Steve Sistare, Christopher J. Jackson	Ultra-high performance communication with MPI and the Sun fireTM link interconnect.	SC	2002	DBLP DOI BibTeX RDF	kernel bypass, remote shared memory, performance evaluation, MPI, interconnects, SAN
15	Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh	Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Krylov, large scale systems, model reduction, RLC interconnects, balanced truncation
15	Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu 0001, Anirudh Devgan	PERI: a technique for extending delay and slew metrics to ramp inputs.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	Elmore, slew, delay, interconnects, PDF, moments, median, skewness, standard deviation
15	Dietmar Fey, Marko Degenkolb	Digit Pipelined Arithmetic for 3-D Massively Parallel Optoelectronic Circuits.	J. Supercomput.	2000	DBLP DOI BibTeX RDF	optoelectronic VLSI, signed-digit arithmetic, pipeline processing, optical interconnects, superscalar architectures
15	William E. Cohen, David W. Hyde, Rhonda Kay Gaede	An Optical Bus-Based Distributed Dynamic Barrier Mechanism.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Parallel processing, optical interconnects, barrier synchronization
15	Ravi R. Iyer 0001, Laxmi N. Bhuyan	Design and Evaluation of a Switch Cache Architecture for CC-NUMA Multiprocessors.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	scalable interconnects, shared memory multiprocessors, wormhole routing, execution-driven simulation, Crossbar switches, cache architectures
15	P. Ghosh, Ramon Mangaser, C. Mark, Kenneth Rose	Interconnect-Dominated VLSI Design.	ARVLSI	1999	DBLP DOI BibTeX RDF	Microprocessor Performance Estimation, Interconnects, Floorplanning, VLSI Design, Repeater Insertion
15	C. Patrick Yue, S. Simon Wong	Design Strategy of On-Chip Inductors for Highly Integrated RF Systems.	DAC	1999	DBLP DOI BibTeX RDF	patterned ground shield, spiral inductor, substrate loss, interconnects, quality factor, substrate coupling, skin effect
15	Ahmed Louri, Brent Weech, Costas Neocleous	A Spanning Multichannel Linked Hypercube: A Gradually Scalable Optical Interconnection Network for Massively Parallel Computing.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	scalability, Interconnection networks, wavelength division multiplexing, optical interconnects, massively parallel processing, product networks
15	D. Scott Wills, Huy Cat, José Cruz-Rivera, W. Stephen Lacy, James M. Baker Jr., John Eble, Abelardo López-Lagunas, Michael A. Hopper	High-Throughput, Low-Memory Applications on the Pica Architecture.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	image processing architectures, through-wafer interconnects, Fine-grain parallelism, MIMD architectures
15	Chunming Qiao, Rami G. Melhem	Reducing Communication Latency with Path Multiplexing in Optically Interconnected Multiprocessor Systems.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	fiber-optical interconnects, time slot interchangers, switching networks, time division multiplexing, Communication latency
15	Andrew B. Kahng, Sudhakar Muddu	Analysis of RC interconnections under ramp input.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	diffusion equation analysis, ramp input response, VLSI interconnects
15	David R. Engebretsen, Daniel M. Kuchta, Richard C. Booth, John D. Crow, Wayne G. Nation	Parallel Fiber-Optic SCI Links.	IEEE Micro	1996	DBLP DOI BibTeX RDF	fiber optics, SCI-Link (Scalable Coherent Interface-Link), Parallel processing, interconnects
15	Steve Scott	The GigaRing Channel.	IEEE Micro	1996	DBLP DOI BibTeX RDF	SCX channel, Cray Research, Interconnects, supercomputing, Scalable Coherent Interface
15	David E. Culler, Lok T. Liu, Richard P. Martin, Chad Yoshikawa	Assessing Fast Network Interfaces.	IEEE Micro	1996	DBLP DOI BibTeX RDF	system performance analysis, Interconnects, Myrinet, communication performance
15	Richard B. Gillett	Memory Channel Network for PCI.	IEEE Micro	1996	DBLP DOI BibTeX RDF	Memory Channel, networks, parallel computers, interconnects
15	Stuart Cheshire, Mary Baker	A Wireless Network in MosquitoNet.	IEEE Micro	1996	DBLP DOI BibTeX RDF	mobile computing, Wireless networks, networking, interconnects, packet switching
15	John R. Feehrer, Lars H. Ramfelt	Packet Synchronization for Synchronous Optical Deflection-Routed Interconnection Networks.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	synchronization, interconnection networks, integer programming, packet switching, constrained optimization, optical interconnects, propagation delay, Deflection routing
15	Mongkol Raksapatcharawong, Timothy Mark Pinkston	An Optical Interconnect Model for k-ary n-cube Wormhole Networks.	IPPS	1996	DBLP DOI BibTeX RDF	free-space optical interconnects, optical interconnect model, performance evaluation, wormhole switching, k-ary n-cube networks
15	Hans T. Heineken, Wojciech Maly	Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs.	ICCAD	1996	DBLP DOI BibTeX RDF	Standard Cell Designs, Synthesis, Interconnects, Manufacturability, Yield
15	Mary Mehrnoosh Eshaghian	Parallel Algorithms for Image Processing on OMC.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	OMC, computational limits, free space optics, fine grain image computing, constant time algorithms, parallel algorithms, parallel algorithms, computational complexity, image processing, computerised picture processing, generic model, optical interconnects, optical information processing
14	Donglai Dai, Aniruddha S. Vaidya, Roy Saharoy, Seungjoon Park, Dongkook Park, Hariharan L. Thantry, Ralf Plate, Elmar Maas, Akhilesh Kumar, Mani Azimi	FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, routing algorithm, on-chip interconnect, router architecture
14	Pranay Koka, Michael O. McCracken, Herb Schwetman, Xuezhe Zheng, Ron Ho, Ashok V. Krishnamoorthy	Silicon-photonic network architectures for scalable, power-efficient multi-chip systems.	ISCA	2010	DBLP DOI BibTeX RDF	interconnection networks, nanophotonics
14	Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Rebecca Berman, Peng Liu 0016, Michael C. Huang 0001, Hui Wu, Eby G. Friedman, Gary Wicks, Duncan Moore	An intra-chip free-space optical interconnect.	ISCA	2010	DBLP DOI BibTeX RDF	free-space optical interconnect, intra-chip, 3d
14	Hu Xu 0002, Vasilis F. Pavlidis, Giovanni De Micheli	Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits.	NanoNet	2009	DBLP DOI BibTeX RDF	timing optimization, on-chip interconnect, repeater insertion, 3-D ICs
14	Shirish Bahirat, Sudeep Pasricha	Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	photonic interconnect, network-on-chip, chip multiprocessor
14	Yufeng Guo, Xuejun Yang, Li Luo, Qiong Li, Lu Liu	High Performance Support of Lustre over Customized HSNI for HPC.	APPT	2009	DBLP DOI BibTeX RDF
14	Hyun-Wook Jin, Junbeom Yoo	Exploring the Design Space for Network Protocol Stacks on Special-Purpose Embedded Systems.	SEUS	2009	DBLP DOI BibTeX RDF	Network Protocol Stacks, Network Gateway, Formal Verification, Protocol Verification, Embedded Operating Systems, Embedded Networks
14	Yu Hu 0002, Yan Lin 0001, Lei He 0001, Tim Tuan	Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	FPGA, Low power, retiming
14	Weihang Jiang, Chongfeng Hu, Yuanyuan Zhou 0001, Arkady Kanevsky	Are disks the dominant contributor for storage failures - A comprehensive study of storage subsystem failure characteristics.	ACM Trans. Storage	2008	DBLP DOI BibTeX RDF	failure characteristics, storage subsystem, Storage system, disk failures
14	Jonathan Appavoo, Volkmar Uhlig, Amos Waterland	Project Kittyhawk: building a global-scale computer: Blue Gene/P as a generic computing platform.	ACM SIGOPS Oper. Syst. Rev.	2008	DBLP DOI BibTeX RDF
14	Md. Sajjad Rahaman, Masud H. Chowdhury	BER performance comparison between CDMA and UWB for RF/wireless interconnect application.	EIT	2008	DBLP DOI BibTeX RDF
14	DiaaEldin Khalil, Yehea I. Ismail	A global interconnect link design for many-core microprocessors.	IFMT	2008	DBLP DOI BibTeX RDF	interconnect, link, bus, repeater insertion
14	Michael Hofmann 0002, Gudula Rünger	MPI Reduction Operations for Sparse Floating-point Data.	PVM/MPI	2008	DBLP DOI BibTeX RDF	reduction operation, MPI, pipelining, performance optimization, run length encoding
14	Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma	Interconnect modeling for improved system-level design optimization.	ASP-DAC	2008	DBLP DOI BibTeX RDF
14	Sudeep Pasricha, Nikil D. Dutt	ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip.	ASP-DAC	2008	DBLP DOI BibTeX RDF
14	Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu	LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process.	ASP-DAC	2008	DBLP DOI BibTeX RDF
14	Fujie Wong, Yajun Ha	A low overhead fault tolerant FPGA with new connection box.	FPL	2008	DBLP DOI BibTeX RDF
14	Jie Hao, Silong Peng	HJ-hPl: Hierarchical Mixed-Size Placement Algorithm with Priori Wirelength Estimation.	ICYCS	2008	DBLP DOI BibTeX RDF
14	Huaxi Gu, Jiang Xu 0001, Zheng Wang	ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	microresonator, low power, network on chip, optical interconnect, router architecture, loss
14	Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman 0001, Parthasarathi Dasgupta	Revisiting fidelity: a case of elmore-based Y-routing trees.	SLIP	2008	DBLP DOI BibTeX RDF	routing, Steiner trees, fidelity, rank correlation
14	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability.	ISQED	2008	DBLP DOI BibTeX RDF	reliability, global routing, thermal
14	Sundeep Narravula, Hari Subramoni, Ping Lai, Ranjit Noronha, Dhabaleswar K. Panda 0001	Performance of HPC Middleware over InfiniBand WAN.	ICPP	2008	DBLP DOI BibTeX RDF
14	Pallav Gupta, Niraj K. Jha, Loganathan Lingappan	A Test Generation Framework for Quantum Cellular Automata Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
14	Jongsun Kim, Ingrid Verbauwhede, M.-C. Frank Chang	Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
14	Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar	Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	Performance evaluation, VLIW, ASIP, Clustered VLIW processors
14	Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen	Multilevel Full-Chip Routing With Testability and Yield Enhancement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
14	Evanthia Papadopoulou	Higher Order Voronoi Diagrams of Segments for VLSI Critical Area Extraction.	ISAAC	2007	DBLP DOI BibTeX RDF
14	Peter Sanders 0001, Jochen Speck, Jesper Larsson Träff	Full Bandwidth Broadcast, Reduction and Scan with Only Two Trees.	PVM/MPI	2007	DBLP DOI BibTeX RDF
14	Basab Datta, Wayne P. Burleson	Low power on-chip thermal sensors based on wires.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
14	Junki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, Kazuya Masu	A Multi-Drop Transmission-Line Interconnect in Si LSI.	ASP-DAC	2007	DBLP DOI BibTeX RDF
14	Ouissem Ben Fredj, Éric Renault	Performance Evaluation of Distributed Computing over Heterogeneous Networks.	HPCC	2007	DBLP DOI BibTeX RDF
14	Mohammad J. Rashti, Ahmad Afsahi	10-Gigabit iWARP Ethernet: Comparative Performance Analysis with InfiniBand and Myrinet-10G.	IPDPS	2007	DBLP DOI BibTeX RDF
14	Zhuo Feng, Peng Li 0001	A methodology for timing model characterization for statistical static timing analysis.	ICCAD	2007	DBLP DOI BibTeX RDF
14	Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail	Including inductance in static timing analysis.	ICCAD	2007	DBLP DOI BibTeX RDF
14	Abinash Roy, Masud H. Chowdhury	Global Interconnect Optimization in the Presence of On-chip Inductance.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Yaling Ma, Mingjie Lin	Collaborative Routing Architecture for FPGA.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, Yehia Massoud	Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations.	ISQED	2007	DBLP DOI BibTeX RDF
14	Andrew B. Kahng, Rasit Onur Topaloglu	A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances.	ISQED	2007	DBLP DOI BibTeX RDF
14	Michael N. Skoufis, Haibo Wang 0005, Themistoklis Haniotakis, Spyros Tragoudas	Glitch Control with Dynamic Receiver Threshold Adjustment.	ISQED	2007	DBLP DOI BibTeX RDF
14	Nikil D. Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha	Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends.	VLSI Design	2007	DBLP DOI BibTeX RDF
14	Wu Jigang, Thambipillai Srikanthan	Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Degradable VLSI array, fault tolerance, algorithms, routing, reconfiguration
14	Xiangdong Xuan, Adit D. Singh, Abhijit Chatterjee	Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	IC reliability, reliability simulation, design for reliability, interconnect, electromigration, defect modeling
14	Dongkook Park, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Chita R. Das	Exploring Fault-Tolerant Network-on-Chip Architectures.	DSN	2006	DBLP DOI BibTeX RDF
14	Jacob R. Minz, Somaskanda Thyagaraja, Sung Kyu Lim	Optical routing for 3D system-on-package.	DATE	2006	DBLP DOI BibTeX RDF
14	Pallav Gupta, Niraj K. Jha, Loganathan Lingappan	Test generation for combinational quantum cellular automata (QCA) circuits.	DATE	2006	DBLP DOI BibTeX RDF
14	Michael R. Marty, Mark D. Hill	Coherence Ordering for Ring-based Chip Multiprocessors.	MICRO	2006	DBLP DOI BibTeX RDF
14	Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes 0001	Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism.	ETS	2006	DBLP DOI BibTeX RDF
14	Wei Huang 0003, Jiuxing Liu, Bülent Abali, Dhabaleswar K. Panda 0001	A case for high performance computing with virtual machines.	ICS	2006	DBLP DOI BibTeX RDF
14	David J. Frank, Ruchir Puri, Dorel Toma	Design and CAD challenges in 45nm CMOS and beyond.	ICCAD	2006	DBLP DOI BibTeX RDF
14	Andrew B. Kahng, Rasit Onur Topaloglu	Generation of design guarantees for interconnect matching.	SLIP	2006	DBLP DOI BibTeX RDF	design guarantee generation, interconnect matching
14	Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex	Impact of interconnect resistance increase on system performance of low power and high performance designs.	SLIP	2006	DBLP DOI BibTeX RDF	interconnect sizing, interconnect technology evaluation, power-delay trade-off, wire sizing
14	Sundeep Narravula, Hyun-Wook Jin, Karthikeyan Vaidyanathan, Dhabaleswar K. Panda 0001	Designing Efficient Cooperative Caching Schemes for Multi-Tier Data-Centers over RDMA-enabled Networks.	CCGRID	2006	DBLP DOI BibTeX RDF
14	Guoqing Chen, Eby G. Friedman	Effective capacitance of RLC loads for estimating short-circuit power.	ISCAS	2006	DBLP DOI BibTeX RDF
14	H. J. Kadim, Lacina M. Coulibaly	EM-based analytical model for estimation of worst-case crosstalk noise.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Vasilis F. Pavlidis, Eby G. Friedman	Via placement for minimum interconnect delay in three-dimensional (3D) circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Calin Ciordas, Kees Goossens, Andrei Radulescu, Twan Basten	NoC monitoring: impact on the design flow.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Krishnamoorthy Natarajan, S. J. Nagalakshmi	Repeater Sizing and Insertion Length of Interconnect to Minimize the Overall Time Delay using a Truncated Fourier Series Approach.	CCECE	2006	DBLP DOI BibTeX RDF
14	Lele Jiang, Junfa Mao	Global Interconnect Analysis and Optimization for Nanometer Scale VLSI.	APCCAS	2006	DBLP DOI BibTeX RDF
14	Dharin Shah, Kothamasu Siva, G. Girishankar, N. S. Nagaraj	Optimizing Interconnect for Performance in Standard Cell Library.	APCCAS	2006	DBLP DOI BibTeX RDF
14	Abinash Roy, Masud H. Chowdhury	Impacts of Inductance on the Figures of Merit to Optimize Global Interconnect.	APCCAS	2006	DBLP DOI BibTeX RDF
14	Yuantao Peng, Xun Liu	Low-power repeater insertion with both delay and slew rate constraints.	DAC	2006	DBLP DOI BibTeX RDF	low power, interconnect, repeater insertion, slew rate
14	N. Venkateswaran 0002, S. Balaji, V. Sridhar	Fault tolerant bus architecture for deep submicron based processors.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF	deep submicron technology, fault tolerance, interconnect, electromigration
14	Mohamed A. Elgamel, Ashok Kumar 0001, Magdy A. Bayoumi	Efficient shield insertion for inductive noise reduction in nanometer technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
14	Magdy A. El-Moursy, Eby G. Friedman	Exponentially tapered H-tree clock distribution networks.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
14	Michael B. Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal	Scalar Operand Networks.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	microprocessors, distributed architectures, Interconnection architectures
14	Yuanyuan Zhou 0001, Angelos Bilas, Suresh Jagannathan, Dimitrios Xinidis, Cezary Dubnicki, Kai Li 0001	VI-Attached Database Storage.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	Database storage, performance evaluation, user-level communication, server cluster, Virtual Interface, storage server
14	Mario R. Casu, Luca Macchiarulo	Throughput-driven floorplanning with wire pipelining.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
14	Jun Chen 0008, Lei He 0001	Piecewise linear model for transmission line with capacitive loading and ramp input.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
14	Davide Bertozzi, Luca Benini, Giovanni De Micheli	Error control schemes for on-chip communication links: the energy-reliability tradeoff.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
14	Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar	Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.	DATE	2005	DBLP DOI BibTeX RDF
14	Luca Benini	Energy efficient NoC design.	SBCCI	2005	DBLP DOI BibTeX RDF
14	Jie Chen 0010, William A. Watson III, Robert G. Edwards, Weizhen Mao	Message Passing for Linux Clusters with Gigabit Ethernet Mesh Connections.	IPDPS	2005	DBLP DOI BibTeX RDF
14	Gary L. McAlpine, Manoj Wadekar, Tanmay Gupta, Alan Crouch, Donald Newell	An Architecture for Congestion Management in Ethernet Clusters.	IPDPS	2005	DBLP DOI BibTeX RDF