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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 5390 occurrences of 2060 keywords
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Found 21101 publication records. Showing 21101 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
21 | Ewerson Carvalho, Ney Calazans, Eduardo Wenzel Brião, Fernando Moraes 0001 |
PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 10-15, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
dynamically and partially reconfigurable systems, partial bitstream generation, reconfiguration control, run-time reconfiguration |
21 | Nozar Tabrizi, Nader Bagherzadeh, Amir Hosein Kamalizad, Haitao Du |
MaRS: a macro-pipelined reconfigurable system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004, pp. 343-349, 2004, ACM, 1-58113-741-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
2D-mesh network, multimedia, computer graphics, wireless communication, reconfigurable architectures, MIMD |
21 | Marjan Karkooti, Joseph R. Cavallaro |
Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCC (1) ![In: International Conference on Information Technology: Coding and Computing (ITCC'04), Volume 1, April 5-7, 2004, Las Vegas, Nevada, USA, pp. 579-585, 2004, IEEE Computer Society, 0-7695-2108-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA imple-mentation, area-time tradeoffs, parallel architecture, Reconfigurable architecture, channel coding |
21 | Javier Resano, Daniel Mozos |
Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 119-124, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
dynamic reconfigurable hardware, run-time scheduling |
21 | M. Arif Wani, Hamid R. Arabnia |
Parallel Edge-Region-Based Segmentation Algorithm Targeted at Reconfigurable MultiRing Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 25(1), pp. 43-62, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
parallel algorithm for segmentation, edge-region-based segmentation, fold-edged, semi-step edges, boundary edges, reconfigurable MultiRing network, broadcasting mechanisms for MultiRing network |
21 | Issam W. Damaj, Hassan B. Diab |
Performance Analysis of Linear Algebraic Functions Using Reconfigurable Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 24(1), pp. 91-107, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
MorphoSys, coarse grained systems, performance evaluation, parallel algorithms, parallel processing, Reconfigurable computing, geometrical transformations |
21 | Paul M. Heysters, Gerard J. M. Smit, Egbert Molenkamp |
A Flexible and Energy-Efficient Coarse-Grained Reconfigurable Architecture for Mobile Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 26(3), pp. 283-308, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
coarse-grained reconfigurable, heterogeneous system-on-chip (SoC), mobile computing, energy-efficient architectures |
21 | Volker Baumgarten, G. Ehlers, Frank May, Armin Nückel, Martin Vorbach, Markus Weinhardt |
PACT XPP - A Self-Reconfigurable Data Processing Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 26(2), pp. 167-184, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
XPP, partial reconfiguration, run-time reconfiguration, adaptive computing, reconfigurable processor |
21 | Christopher Kachris, Nikolaos G. Bourbakis, Apostolos Dollas |
A Reconfigurable Logic-Based Processor for the SCAN Image and Video Encryption Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 31(6), pp. 489-506, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
cryptography, block cipher, reconfigurable logic, image encryption |
21 | João M. P. Cardoso |
On Combining Temporal Partitioning and Sharing of Functional Units in Compilation for Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(10), pp. 1362-1375, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
scheduling, FPGAs, reconfigurable computing, temporal partitioning |
21 | Sami Khawam, Tughrul Arslan, Fred Westall |
Domain-Specific Reconfigurable Array for Distributed Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 1139-1144, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Embedded reconfigurable array, FPGA, low-power, programmable, distributed arithmetic, domain specific |
21 | Arezou Koohi, Nader Bagherzadeh, Chengzi Pan |
A fast parallel reed-solomon decoder on a reconfigurable architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003, pp. 59-64, 2003, ACM, 1-58113-742-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Berlekamp algorithm, Chein search, reconfigurable architecture, Reed-Solomon codes, SIMD processor |
21 | John Morris |
Reconfigurable Logic: A Saviour for Experimental Computer Architecture Research. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings, pp. 69-85, 2003, Springer, 3-540-20122-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
programmable hardware, data flow, stereo correspondence, Reconfigurable logic, asynchronous logic |
21 | Osvaldo Colavin, Davide Rizzo |
A scalable wide-issue clustered VLIW with a reconfigurable interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 148-158, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
clustered VLIW, reconfigurable co-processor (RCP), modulo scheduling, IDCT |
21 | Paul Beckett |
Exploiting multiple functionality for nano-scale reconfigurable systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 50-55, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
chalcogenide, double gate transistors, multi-valued RAM, multiple functionality, resonant tunneling, nanotechnology, reconfigurable systems, carbon nanotube, nanoelectronics, RTD |
21 | Manish Handa, Rajesh Radhakrishnan, Madhubanti Mukherjee, Ranga Vemuri |
A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 91-, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
FPGA, Reconfigurable Computing, Partial Reconfiguration |
21 | Michele Borgatti, Lorenzo Cali, Guido De Sandre, Benoit Forêt, David Iezzi, Francesco Lertora, Gilberto Muzzi, Marco Pasotti, Marco Poles, Pier Luigi Rolandi |
A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 691-695, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), reconfigurable architectures, integrated circuit design, multimedia computing, digital signal processors |
21 | Amitava Datta |
Efficient Graph-Theoretic Algorithms on a Linear Array with a Reconfigurable Pipelined Bus System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 23(2), pp. 193-211, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
reconfigurable pipelined bus, minimum spanning forest, parallel algorithm, graph algorithms, connected components, optical computing, biconnected components |
21 | Amitava Datta, Subbiah Soundaralakshmi, Robyn A. Owens |
Fast Sorting Algorithms on a Linear Array with a Reconfigurable Pipelined Bus System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 13(3), pp. 212-222, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
reconfigurable bus, pipelined communication, merging, sorting algorithm, optical bus, deterministic sampling |
21 | Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang |
Performance-driven placement for dynamically reconfigurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(4), pp. 628-642, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
field-programmable gate array, placement, dynamically reconfigurable, layout, Computer-aided design of VLSI |
21 | Mario Porrmann, Ulf Witkowski, Heiko Kalte, Ulrich Rückert 0001 |
Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 10th Euromicro Workshop on Parallel, Distributed and Network-Based Processing (PDP 2002), 9-11 January 2002, Canary Islands, Spain, pp. 243-, 2002, IEEE Computer Society, 0-7695-1444-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Kohonen, FPGA, Artificial Neural Networks, Self-organizing Map, Reconfigurable, RBF, Hardware Accelerator, Associative Memory |
21 | Edson L. Horta, Sergio Takeo Kofuji |
A Run-Time Reconfigurable ATM Switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Partial RTR, ATM Switch, Reconfigurable Logic |
21 | Chin-Hsiung Wu, Shi-Jinn Horng, Yi Pan 0001 |
Parallel Algorithms for Median Filtering on Arrays with Reconfigurable Optical Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
reconfigurable optical bus system, image processing, selection, nonlinear filter, median filter |
21 | Juanjo Noguera, Rosa M. Badia |
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, Estes Park, Colorado, USA, May 6-8, 2002, pp. 205-210, 2002, ACM, 1-58113-542-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
dynamic run-time scheduling, reconfigurable architectures |
21 | Carles Rodoreda Sala, Natalino G. Busá |
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 44-49, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
VLIW processors, reconfigurable logic, architectural synthesis |
21 | Juan Carlos López 0001, Fernando Rincón, Francisco Moya, José Manuel Moya |
Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 255-260, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
reconfigurable datapaths, hardware-software codesign |
21 | Horng-Ren Tsai |
Parallel Algorithms for the Medial Axis Transform on Linear Arrays with a Reconfigurable Pipelined Bus System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 9th International Conference on Parallel and Distributed Systems, ICPADS 2002, Taiwan, ROC, December 17-20, 2002, pp. 123-128, 2002, IEEE Computer Society, 0-7695-1760-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
linear array with a reconfigurable pipelined bus system, computer vision, parallel algorithms, image processing, image compression, Medial axis transform |
21 | Rong Lin, Martin Margala |
Novel design and verification of a 16 x 16-b self-repairable reconfigurable inner product processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002, pp. 172-177, 2002, ACM, 1-58113-462-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
fault tolerance, image processing, VLSI, reconfigurable, arithmetic circuits, self-repair, decomposition algorithms |
21 | Omar Bouattane, Jelloul Elmesbahi, Mohammed Khaldoun, A. Rami |
A Fast Algorithm for k-Nearest Neighbor Problem on a Reconfigurable Mesh Computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 32(3), pp. 347-360, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
reconfigurable mesh computer, parallel processing, data analysis, k-nearest neighbor, SIMD architecture |
21 | Keqin Li, Victor Y. Pan |
Parallel Matrix Multiplication on a Linear Array with a Reconfigurable Pipelined Bus System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(5), pp. 519-525, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Bilinear algorithm, optical pipelined bus, distributed memory system, matrix multiplication, speedup, PRAM, reconfigurable system, linear array, cost-optimality |
21 | Chin-Hsiung Wu, Shi-Jinn Horng |
L2 Vector Median Filters on Arrays with Reconfigurable Optical Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 12(12), pp. 1281-1292, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
image (signal) processing, reconfigurable optical bus system, Parallel algorithm, nonlinear filter, scalable algorithm, vector median filter |
21 | Marlene Wan, Hui Zhang 0008, George Varghese, Martin Benes 0002, Arthur Abnous, Vandana Prabhu, Jan M. Rabaey |
Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 28(1-2), pp. 47-61, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
low-power, design methodology, reconfigurable architecture, digital signal processor |
21 | Chin-Hsiung Wu, Shi-Jinn Horng, Yi-Wen Chen, Chen-Kuo Yu |
Run-Length Chain Coding and Shape's Moment Computations on Arrays with Reconfigurable Optical Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: Proceedings of the 2001 International Conference on Parallel Processing, ICPP 2002, 3-7 September 2001, Valencia, Spain, pp. 479-488, 2001, IEEE Computer Society, 0-7695-1257-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
shape's moments, run-length chain code, reconfigurable optical bus system, parallel algorithm, boundary extraction |
21 | Issam W. Damaj, Hassan B. Diab |
Performance Analysis of Extended Vector-Scalar Operations Using Reconfigurable Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICCSA ![In: 2001 ACS / IEEE International Conference on Computer Systems and Applications (AICCSA 2001), 26-29 June 2001, Beirut, Lebanon, pp. 227-, 2001, IEEE Computer Society, 0-7695-1165-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Parallel Processing, Reconfigurable Computing, Algorithm Mapping, Algebraic Functions |
21 | Keith D. Underwood, Ron Sass, Walter B. Ligon III |
A Reconfigurable Extension to the Network Interface of Beowulf Clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: 2001 IEEE International Conference on Cluster Computing (CLUSTER 2001), 8-11 October 2001, Newport Beach, CA, USA, pp. 212-, 2001, IEEE Computer Society, 0-7695-1116-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
network hardware, cluster, FPGA, reconfigurable, intelligent network, beowulf |
21 | S. Ramanathan, S. K. Nandy 0001, V. Visvanathan |
Reconfigurable Filter Coprocessor Architecture for DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 26(3), pp. 333-359, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
reconfigurable coprocessors, filter coprocessor architecture, systolic architectures and digital signal processing, pipelined architectures, low-power architectures |
21 | Ding-Chau Wang, Chih-Ping Chu, Ing-Ray Chen |
Analyzing Reconfigurable Algorithms for Managing Replicated Data with Strict Consistency Requirements: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPSAC ![In: 24th International Computer Software and Applications Conference (COMPSAC 2000), 25-28 October 2000, Taipei, Taiwan, pp. 608-613, 2000, IEEE Computer Society, 0-7695-0792-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
dynamic voting, distributed systems, availability, data replication, stochastic Petri nets, reconfigurable systems, data contention |
21 | Anu G. Bourgeois, Jerry L. Trahan |
Relating Two-Dimensional Reconfigurable Meshes with Optically Pipelined Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), Cancun, Mexico, May 1-5, 2000, pp. 747-752, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Reconfigurable models, optical buses, complexity, model simulations |
21 | Chin-Hsiung Wu, Shi-Jinn Horng, Jinn-Fu Lin, Horng-Ren Tsai, Tsrong-Lay Lin |
An Optimal Parallel Algorithm for Computing Moments on Arrays with Reconfigurable Optical Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), Cancun, Mexico, May 1-5, 2000, pp. 741-746, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
suffix sums, reconfigurable optical bus, image processing, moments, moment invariants |
21 | Rong Lin |
A Reconfigurable Low-Power High-Performance Matrix Multiplier Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 321-328, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
low-power CMOS circuits, parallel counter-multiplier circuits, reconfigurable architecture, Matrix multiplication |
21 | Wayne Luk, T. K. Lee, J. Rice, Nabeel Shirazi, Peter Y. K. Cheung |
Reconfigurable Computing for Augmented Reality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 136-145, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
FPGAs, augmented reality, reconfigurable computing, video analysis, video synthesis |
21 | Kazimierz Wiatr |
Pipeline Architecture of Specialized Reconfigurable Processors in FPGA Structures for Real-Time Image Pre-Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 24th EUROMICRO '98 Conference, Engineering Systems and Software for the Next Decade, 25-27 August 1998, Vesteras, Sweden, pp. 10131-10138, 1998, IEEE Computer Society, 0-8186-8646-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Image processors, FPGAs, real-time systems, reconfigurable systems |
21 | Sanguthevar Rajasekaran, Sartaj Sahni |
Sorting, Selection, and Routing on the Array with Reconfigurable Optical Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 8(11), pp. 1123-1132, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
comparison problems, sorting, interprocessor communication, optical computing, mesh-connected computers, Reconfigurable networks |
21 | John Woodfill, Brian Von Herzen |
Real-time stereo vision on the PARTS reconfigurable computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 16-18 April 1997, Napa Valley, CA, USA, pp. 201-210, 1997, IEEE Computer Society, 0-8186-8159-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
powerful scalable reconfigurable computer, PARTS engine, real-time stereo vision, Xilinx 4025 FPGAs, partial torus, concurrent SRAM access, standard PCI card, stereo vision algorithm, stereo disparity computation, RISC-equivalent operations, 1 Mbyte, images, SRAMs, stereo image processing, personal computer, workstation, memory access |
21 | Yi Pan 0001, Keqin Li 0001, Si-Qing Zheng |
Fast nearest neighbor algorithms on a linear array with a reconfigurable pipelined bus system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97), 18-20 December 1997, Taipei, Taiwan, pp. 444-450, 1997, IEEE Computer Society, 0-8186-8259-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
reconfigurable pipelined bus, nearest neighbor problem, O(log log n)time, n/sup 3/ processors, O(1) time, image processing, binary image, linear array, nearest neighbor algorithms |
21 | Hossam A. ElGindy, Arun K. Somani, Heiko Schröder 0001, Hartmut Schmeck, Andrew Spray |
RMB - A Reconfigurable Multiple Bus Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Second International Symposium on High-Performance Computer Architecture, San Jose, CA, USA, February 3-7, 1996, pp. 108-117, 1996, IEEE Computer Society, 0-8186-7237-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Reconfigurable Multiple Bus Network, Multiprocessor systems, Permutation Routing, Interconnection Structure |
21 | Sandy Pavel, Selim G. Akl |
Efficient Algorithms for the Hough Transform on Arrays with Reconfigurable Optical Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 697-701, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
arrays with reconfigurable optical buses, Hough transform |
21 | Tzong-Wann Kao, Shi-Jinn Horng |
Computing Dominators and Its Applications on Processor Arrays with Reconfigurable Bus Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), June 12-14, 1996, Beijing, China, pp. 302-308, 1996, IEEE Computer Society, 0-8186-7460-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
bridge-connected components, reconfigurable bus system, dominator, undirected graphs, bridge, dominator tree, biconnected components, articulation point |
21 | Serge Miguet, Yves Robert |
Reduction Operations on a Distributed Memory Machine with a Reconfigurable Interconnection Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 3(4), pp. 500-505, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
reconfigurable interconnection network, reductionoperations, interconnection graph, transputer-based networks, graph theory, multiprocessor interconnection networks, distributed memory machine |
21 | Jacques Briat, M. Favre, Cláudio F. R. Geyer, Jacques Chassin de Kergommeaux |
Schheduling of OR-parallel Prolog on a Scalable, Reconfigurable, Distributed-Memory Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE (2) ![In: PARLE '91: Parallel Architectures and Languages Europe, Volume II: Parallel Languages, Eindhoven, The Netherlands, June 10-13, 1991, Proceedings, pp. 385-402, 1991, Springer, 3-540-54152-7. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
OPERA, OR-parallel Prolog, reconfigurable multiprocessor, distributed-memory, WAM, Supernode, scalable multiprocessor |
21 | Pavel G. Zaykov, Georgi Kuzmanov, Georgi Nedeltchev Gaydadjiev |
Reconfigurable Multithreading Architectures: A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 263-274, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Luigi Carro, Stephan Wong |
Introduction to the Future of Reconfigurable Computing and Processor Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 226, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Zhiyuan Wang, Jianhua Huang, Ziming Guan |
The SOBER Family Ciphers Reconfigurable Processing Architecture Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IAS ![In: Proceedings of the Fifth International Conference on Information Assurance and Security, IAS 2009, Xi'An, China, 18-20 August 2009, pp. 322-326, 2009, IEEE Computer Society, 978-0-7695-3744-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Heiner Giefers, Marco Platzner |
ARMLang: A language and compiler for programming reconfigurable mesh many-cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-8, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Vu Manh Tuan, Naohiro Katsura, Hiroki Matsutani, Hideharu Amano |
Evaluation of a multicore reconfigurable architecture with variable core sizes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-8, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Sofia A. Paredes, Gregor von Bochmann, Trevor J. Hall |
Deploying agile photonic networks over reconfigurable optical networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCC ![In: Proceedings of the 14th IEEE Symposium on Computers and Communications (ISCC 2009), July 5-8, Sousse, Tunisia, pp. 182-187, 2009, IEEE Computer Society, 978-1-4244-4672-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Abderrahmane Bennis, Miriam Leeser, Gilead Tadmor |
Implementing a Highly Parameterized Digital PIV System on Reconfigurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2009, July 7-9, 2009, Boston, MA, USA, pp. 32-37, 2009, IEEE Computer Society, 978-0-7695-3732-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Yan Xiao, Zhenhua Duan, Pengcheng Nie |
An Efficient Algorithm for Finding Empty Space for Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TASE ![In: TASE 2009, Third IEEE International Symposium on Theoretical Aspects of Software Engineering, 29-31 July 2009, Tianjin, China, pp. 36-43, 2009, IEEE Computer Society, 978-0-7695-3757-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Joseph Hassoun |
Resiliency in Elemental Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 2, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Nazish Aslam, Mark Milward, Ahmet T. Erdogan, Tughrul Arslan |
Code Compression and Decompression for Coarse-Grain Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(12), pp. 1596-1608, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Gerard K. Rauwerda, Paul M. Heysters, Gerard J. M. Smit |
Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(1), pp. 3-13, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Katherine Compton, Scott Hauck |
Automatic Design of Reconfigurable Domain-Specific Flexible Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(5), pp. 493-503, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Zhi Guo, Betul Buyukkurt, John Cortes, Abhishek Mitra, Walid A. Najjar |
A Compiler Intermediate Representation for Reconfigurable Fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 36(5), pp. 493-520, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, VHDL, Configurable computing, Intermediate representation |
21 | Jason C. Chen, Shao-Yi Chien |
CRISP: Coarse-Grained Reconfigurable Image Stream Processor for Digital Still Cameras and Camcorders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 18(9), pp. 1223-1236, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 7(4), pp. 40:1-40:31, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
coarse-grained FPGA, VLIW, ASIP |
21 | Kamana Sigdel, Mark Thompson 0001, Andy D. Pimentel, Todor P. Stefanov, Koen Bertels |
System-Level Design Space Exploration of Dynamic Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008. Proceedings, pp. 279-288, 2008, Springer, 978-3-540-70549-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | David Johan Christensen, David Brandt, Kasper Støy, Ulrik Pagh Schultz |
A unified simulator for Self-Reconfigurable Robots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IROS ![In: 2008 IEEE/RSJ International Conference on Intelligent Robots and Systems, September 22-26, 2008, Acropolis Convention Center, Nice, France, pp. 870-876, 2008, IEEE, 978-1-4244-2057-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Ho Seok Ahn, Young Min Baek, Inkyu Sa, Woo-Sung Kang, Jin Hee Na, Jin Young Choi 0002 |
Design of reconfigurable heterogeneous modular architecture for service robots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IROS ![In: 2008 IEEE/RSJ International Conference on Intelligent Robots and Systems, September 22-26, 2008, Acropolis Convention Center, Nice, France, pp. 1313-1318, 2008, IEEE, 978-1-4244-2057-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Antonio Carlos Schneider Beck, Mateus B. Rutzig, Georgi Gaydadjiev, Luigi Carro |
Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1208-1213, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Zhiming Chang, XinJun Mao, Zhichang Qi |
Towards a Formal Model for Reconfigurable Software Architectures by Bigraphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WICSA ![In: Seventh Working IEEE / IFIP Conference on Software Architecture (WICSA 2008), 18-22 February 2008, Vancouver, BC, Canada, pp. 331-334, 2008, IEEE Computer Society, 978-0-7695-3092-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Bigraph, Software Architecture, Reconfiguration |
21 | Carlo Curino, Luca Fossati, Vincenzo Rana, Francesco Redaelli, Marco D. Santambrogio, Donatella Sciuto |
The Shining embedded system design methodology based on self dynamic reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 595-600, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Mirko Bordignon, Lars Lindegaard Mikkelsen, Ulrik Pagh Schultz |
Implementing Flexible Parallelism for Modular Self-reconfigurable Robots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIMPAR ![In: Simulation, Modeling, and Programming for Autonomous Robots, First International Conference, SIMPAR 2008, Venice, Italy, November 3-6, 2008. Proceedings, pp. 123-134, 2008, Springer, 978-3-540-89075-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa |
On-the-fly attestation of reconfigurable hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 71-76, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Vlad Mihai Sima, Elena Moscu Panainte, Koen Bertels |
Resource allocation algorithm and OpenMP extensions for parallel execution on a heterogeneous reconfigurable platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 651-654, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Matthew A. Watkins, Mark J. Cianchetti, David H. Albonesi |
Shared reconfigurable architectures for CMPS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 299-304, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa |
Towards benchmarking energy efficiency of reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 691-694, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Lars Bauer, Muhammad Shafique 0001, Jörg Henkel |
A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 203-208, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Götz Kappen, Tobias G. Noll |
Application-specific reconfigurable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 350, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Claudio Brunelli, Fabio Garzia, Jari Nurmi, Fabio Campi, Damien Picard |
Reconfigurable hardware: The holy grail of matching performance with programming productivity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 409-414, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Dirk Koch, Christian Beckhoff, Jürgen Teich |
ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 119-124, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Wenyin Fu, Katherine Compton |
Active kernel monitoring to combat scheduler gaming in reconfigurable computing systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 611-614, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Fabio Garzia, Claudio Brunelli, Davide Rossi, Jari Nurmi |
Implementation of a floating-point matrix-vector multiplication on a reconfigurable architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-6, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Lukás Sekanina, Petr Mikusek |
Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EvoWorkshops ![In: Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. Proceedings, pp. 144-153, 2008, Springer, 978-3-540-78760-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Ting Liu 0007, Camel Tanougast, Serge Weber |
A framework of architectural synthesis for dynamically reconfigurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 283-286, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Syed Waqar Nabi, Cade C. Wells, Wim Vanderbauwhede |
A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 151-154, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | J. Divyasree, H. Rajashekar, Kuruvilla Varghese |
Dynamically reconfigurable regular expression matching architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 120-125, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Ritesh Rajore, Ganesh Garga, H. S. Jamadagni, S. K. Nandy 0001 |
Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 49-54, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Junji Kitamichi, Koji Ueda, Kenichi Kuroda |
A Modeling of a Dynamically Reconfigurable Processor Using SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 91-96, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Frank Bouwens, Mladen Berekovic, Bjorn De Sutter, Georgi Gaydadjiev |
Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings, pp. 66-81, 2008, Springer, 978-3-540-77559-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Zhen Zhang, Alain Greiner, Sami Taktak |
A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 441-446, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
2D-Mesh NoC, DSPIN, MP2-SoC, fault-tolerant, reconfiguration, routing algorithm |
21 | Antonio Carlos Schneider Beck, Mateus B. Rutzig, Georgi Gaydadjiev, Luigi Carro |
Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings, pp. 111-123, 2008, Springer, 978-3-540-78609-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis |
Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(12), pp. 1362-1366, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Lukás Sekanina |
Evolutionary functional recovery in virtual reconfigurable circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 3(2), pp. 8, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA, evolutionary algorithms, Dependability, evolvable hardware |
21 | Proshanta Saha, Tarek A. El-Ghazawi |
A Methodology for Automating Co-Scheduling for Reconfigurable Computing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30 - June 1st, Nice, France, pp. 159-168, 2007, IEEE Computer Society, 1-4244-1050-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Ricardo S. Ferreira 0001, Alisson Garcia, Tiago Teixeira, João M. P. Cardoso |
A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 61-66, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Simone Corbetta, Fabrizio Ferrandi, Massimo Morandi, Marco Novati, Marco D. Santambrogio, Donatella Sciuto |
Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 457-458, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Yoon-suk Jin, Yang-wook Kim, Jun Park |
ARMO: Augmented Reality based Reconfigurable MOck-up. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMAR ![In: Sixth IEEE/ACM International Symposium on Mixed and Augmented Reality, ISMAR 2007, 13-16 November 2007, Nara, Japan, pp. 273-274, 2007, IEEE Computer Society, 978-1-4244-1749-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Wing On Fung, Tughrul Arslan |
A multi-objective algorithm for the design of high performance reconfigurable architectures with embedded decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Congress on Evolutionary Computation ![In: Proceedings of the IEEE Congress on Evolutionary Computation, CEC 2007, 25-28 September 2007, Singapore, pp. 4399-4404, 2007, IEEE, 978-1-4244-1339-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Mihai Sima, Michael McGuire |
Embedded Reconfigurable Solution for OFDM Detection Over Fast Fading Radio Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China, pp. 13-18, 2007, IEEE, 1-4244-1222-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Chang-Seok Choi, Hanho Lee |
A Partial Self-Reconfigurable Adaptive FIR Filter System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China, pp. 204-209, 2007, IEEE, 1-4244-1222-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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