Search results for "reconfigurable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Ewerson Carvalho, Ney Calazans, Eduardo Wenzel Brião, Fernando Moraes 0001	PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems.	SBCCI	2004	DBLP DOI BibTeX RDF	dynamically and partially reconfigurable systems, partial bitstream generation, reconfiguration control, run-time reconfiguration
21	Nozar Tabrizi, Nader Bagherzadeh, Amir Hosein Kamalizad, Haitao Du	MaRS: a macro-pipelined reconfigurable system.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	2D-mesh network, multimedia, computer graphics, wireless communication, reconfigurable architectures, MIMD
21	Marjan Karkooti, Joseph R. Cavallaro	Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding.	ITCC (1)	2004	DBLP DOI BibTeX RDF	FPGA imple-mentation, area-time tradeoffs, parallel architecture, Reconfigurable architecture, channel coding
21	Javier Resano, Daniel Mozos	Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware.	DAC	2004	DBLP DOI BibTeX RDF	dynamic reconfigurable hardware, run-time scheduling
21	M. Arif Wani, Hamid R. Arabnia	Parallel Edge-Region-Based Segmentation Algorithm Targeted at Reconfigurable MultiRing Network.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	parallel algorithm for segmentation, edge-region-based segmentation, fold-edged, semi-step edges, boundary edges, reconfigurable MultiRing network, broadcasting mechanisms for MultiRing network
21	Issam W. Damaj, Hassan B. Diab	Performance Analysis of Linear Algebraic Functions Using Reconfigurable Computing.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	MorphoSys, coarse grained systems, performance evaluation, parallel algorithms, parallel processing, Reconfigurable computing, geometrical transformations
21	Paul M. Heysters, Gerard J. M. Smit, Egbert Molenkamp	A Flexible and Energy-Efficient Coarse-Grained Reconfigurable Architecture for Mobile Systems.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	coarse-grained reconfigurable, heterogeneous system-on-chip (SoC), mobile computing, energy-efficient architectures
21	Volker Baumgarten, G. Ehlers, Frank May, Armin Nückel, Martin Vorbach, Markus Weinhardt	PACT XPP - A Self-Reconfigurable Data Processing Architecture.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	XPP, partial reconfiguration, run-time reconfiguration, adaptive computing, reconfigurable processor
21	Christopher Kachris, Nikolaos G. Bourbakis, Apostolos Dollas	A Reconfigurable Logic-Based Processor for the SCAN Image and Video Encryption Algorithm.	Int. J. Parallel Program.	2003	DBLP DOI BibTeX RDF	cryptography, block cipher, reconfigurable logic, image encryption
21	João M. P. Cardoso	On Combining Temporal Partitioning and Sharing of Functional Units in Compilation for Reconfigurable Architectures.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	scheduling, FPGAs, reconfigurable computing, temporal partitioning
21	Sami Khawam, Tughrul Arslan, Fred Westall	Domain-Specific Reconfigurable Array for Distributed Arithmetic.	FPL	2003	DBLP DOI BibTeX RDF	Embedded reconfigurable array, FPGA, low-power, programmable, distributed arithmetic, domain specific
21	Arezou Koohi, Nader Bagherzadeh, Chengzi Pan	A fast parallel reed-solomon decoder on a reconfigurable architecture.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	Berlekamp algorithm, Chein search, reconfigurable architecture, Reed-Solomon codes, SIMD processor
21	John Morris	Reconfigurable Logic: A Saviour for Experimental Computer Architecture Research.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF	programmable hardware, data flow, stereo correspondence, Reconfigurable logic, asynchronous logic
21	Osvaldo Colavin, Davide Rizzo	A scalable wide-issue clustered VLIW with a reconfigurable interconnect.	CASES	2003	DBLP DOI BibTeX RDF	clustered VLIW, reconfigurable co-processor (RCP), modulo scheduling, IDCT
21	Paul Beckett	Exploiting multiple functionality for nano-scale reconfigurable systems.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	chalcogenide, double gate transistors, multi-valued RAM, multiple functionality, resonant tunneling, nanotechnology, reconfigurable systems, carbon nanotube, nanoelectronics, RTD
21	Manish Handa, Rajesh Radhakrishnan, Madhubanti Mukherjee, Ranga Vemuri	A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs.	VLSI Design	2003	DBLP DOI BibTeX RDF	FPGA, Reconfigurable Computing, Partial Reconfiguration
21	Michele Borgatti, Lorenzo Cali, Guido De Sandre, Benoit Forêt, David Iezzi, Francesco Lertora, Gilberto Muzzi, Marco Pasotti, Marco Poles, Pier Luigi Rolandi	A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory.	DAC	2003	DBLP DOI BibTeX RDF	field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), reconfigurable architectures, integrated circuit design, multimedia computing, digital signal processors
21	Amitava Datta	Efficient Graph-Theoretic Algorithms on a Linear Array with a Reconfigurable Pipelined Bus System.	J. Supercomput.	2002	DBLP DOI BibTeX RDF	reconfigurable pipelined bus, minimum spanning forest, parallel algorithm, graph algorithms, connected components, optical computing, biconnected components
21	Amitava Datta, Subbiah Soundaralakshmi, Robyn A. Owens	Fast Sorting Algorithms on a Linear Array with a Reconfigurable Pipelined Bus System.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	reconfigurable bus, pipelined communication, merging, sorting algorithm, optical bus, deterministic sampling
21	Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang	Performance-driven placement for dynamically reconfigurable FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	field-programmable gate array, placement, dynamically reconfigurable, layout, Computer-aided design of VLSI
21	Mario Porrmann, Ulf Witkowski, Heiko Kalte, Ulrich Rückert 0001	Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator.	PDP	2002	DBLP DOI BibTeX RDF	Kohonen, FPGA, Artificial Neural Networks, Self-organizing Map, Reconfigurable, RBF, Hardware Accelerator, Associative Memory
21	Edson L. Horta, Sergio Takeo Kofuji	A Run-Time Reconfigurable ATM Switch.	IPDPS	2002	DBLP DOI BibTeX RDF	Partial RTR, ATM Switch, Reconfigurable Logic
21	Chin-Hsiung Wu, Shi-Jinn Horng, Yi Pan 0001	Parallel Algorithms for Median Filtering on Arrays with Reconfigurable Optical Buses.	IPDPS	2002	DBLP DOI BibTeX RDF	reconfigurable optical bus system, image processing, selection, nonlinear filter, median filter
21	Juanjo Noguera, Rosa M. Badia	Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures.	CODES	2002	DBLP DOI BibTeX RDF	dynamic run-time scheduling, reconfigurable architectures
21	Carles Rodoreda Sala, Natalino G. Busá	A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor.	ISSS	2002	DBLP DOI BibTeX RDF	VLIW processors, reconfigurable logic, architectural synthesis
21	Juan Carlos López 0001, Fernando Rincón, Francisco Moya, José Manuel Moya	Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable Coprocessors.	ISSS	2002	DBLP DOI BibTeX RDF	reconfigurable datapaths, hardware-software codesign
21	Horng-Ren Tsai	Parallel Algorithms for the Medial Axis Transform on Linear Arrays with a Reconfigurable Pipelined Bus System.	ICPADS	2002	DBLP DOI BibTeX RDF	linear array with a reconfigurable pipelined bus system, computer vision, parallel algorithms, image processing, image compression, Medial axis transform
21	Rong Lin, Martin Margala	Novel design and verification of a 16 x 16-b self-repairable reconfigurable inner product processor.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	fault tolerance, image processing, VLSI, reconfigurable, arithmetic circuits, self-repair, decomposition algorithms
21	Omar Bouattane, Jelloul Elmesbahi, Mohammed Khaldoun, A. Rami	A Fast Algorithm for k-Nearest Neighbor Problem on a Reconfigurable Mesh Computer.	J. Intell. Robotic Syst.	2001	DBLP DOI BibTeX RDF	reconfigurable mesh computer, parallel processing, data analysis, k-nearest neighbor, SIMD architecture
21	Keqin Li, Victor Y. Pan	Parallel Matrix Multiplication on a Linear Array with a Reconfigurable Pipelined Bus System.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Bilinear algorithm, optical pipelined bus, distributed memory system, matrix multiplication, speedup, PRAM, reconfigurable system, linear array, cost-optimality
21	Chin-Hsiung Wu, Shi-Jinn Horng	L2 Vector Median Filters on Arrays with Reconfigurable Optical Buses.	IEEE Trans. Parallel Distributed Syst.	2001	DBLP DOI BibTeX RDF	image (signal) processing, reconfigurable optical bus system, Parallel algorithm, nonlinear filter, scalable algorithm, vector median filter
21	Marlene Wan, Hui Zhang 0008, George Varghese, Martin Benes 0002, Arthur Abnous, Vandana Prabhu, Jan M. Rabaey	Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	low-power, design methodology, reconfigurable architecture, digital signal processor
21	Chin-Hsiung Wu, Shi-Jinn Horng, Yi-Wen Chen, Chen-Kuo Yu	Run-Length Chain Coding and Shape's Moment Computations on Arrays with Reconfigurable Optical Buses.	ICPP	2001	DBLP DOI BibTeX RDF	shape's moments, run-length chain code, reconfigurable optical bus system, parallel algorithm, boundary extraction
21	Issam W. Damaj, Hassan B. Diab	Performance Analysis of Extended Vector-Scalar Operations Using Reconfigurable Computing.	AICCSA	2001	DBLP DOI BibTeX RDF	Parallel Processing, Reconfigurable Computing, Algorithm Mapping, Algebraic Functions
21	Keith D. Underwood, Ron Sass, Walter B. Ligon III	A Reconfigurable Extension to the Network Interface of Beowulf Clusters.	CLUSTER	2001	DBLP DOI BibTeX RDF	network hardware, cluster, FPGA, reconfigurable, intelligent network, beowulf
21	S. Ramanathan, S. K. Nandy 0001, V. Visvanathan	Reconfigurable Filter Coprocessor Architecture for DSP Applications.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF	reconfigurable coprocessors, filter coprocessor architecture, systolic architectures and digital signal processing, pipelined architectures, low-power architectures
21	Ding-Chau Wang, Chih-Ping Chu, Ing-Ray Chen	Analyzing Reconfigurable Algorithms for Managing Replicated Data with Strict Consistency Requirements: A Case Study.	COMPSAC	2000	DBLP DOI BibTeX RDF	dynamic voting, distributed systems, availability, data replication, stochastic Petri nets, reconfigurable systems, data contention
21	Anu G. Bourgeois, Jerry L. Trahan	Relating Two-Dimensional Reconfigurable Meshes with Optically Pipelined Buses.	IPDPS	2000	DBLP DOI BibTeX RDF	Reconfigurable models, optical buses, complexity, model simulations
21	Chin-Hsiung Wu, Shi-Jinn Horng, Jinn-Fu Lin, Horng-Ren Tsai, Tsrong-Lay Lin	An Optimal Parallel Algorithm for Computing Moments on Arrays with Reconfigurable Optical Buses.	IPDPS	2000	DBLP DOI BibTeX RDF	suffix sums, reconfigurable optical bus, image processing, moments, moment invariants
21	Rong Lin	A Reconfigurable Low-Power High-Performance Matrix Multiplier Design.	ISQED	2000	DBLP DOI BibTeX RDF	low-power CMOS circuits, parallel counter-multiplier circuits, reconfigurable architecture, Matrix multiplication
21	Wayne Luk, T. K. Lee, J. Rice, Nabeel Shirazi, Peter Y. K. Cheung	Reconfigurable Computing for Augmented Reality.	FCCM	1999	DBLP DOI BibTeX RDF	FPGAs, augmented reality, reconfigurable computing, video analysis, video synthesis
21	Kazimierz Wiatr	Pipeline Architecture of Specialized Reconfigurable Processors in FPGA Structures for Real-Time Image Pre-Processing.	EUROMICRO	1998	DBLP DOI BibTeX RDF	Image processors, FPGAs, real-time systems, reconfigurable systems
21	Sanguthevar Rajasekaran, Sartaj Sahni	Sorting, Selection, and Routing on the Array with Reconfigurable Optical Buses.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	comparison problems, sorting, interprocessor communication, optical computing, mesh-connected computers, Reconfigurable networks
21	John Woodfill, Brian Von Herzen	Real-time stereo vision on the PARTS reconfigurable computer.	FCCM	1997	DBLP DOI BibTeX RDF	powerful scalable reconfigurable computer, PARTS engine, real-time stereo vision, Xilinx 4025 FPGAs, partial torus, concurrent SRAM access, standard PCI card, stereo vision algorithm, stereo disparity computation, RISC-equivalent operations, 1 Mbyte, images, SRAMs, stereo image processing, personal computer, workstation, memory access
21	Yi Pan 0001, Keqin Li 0001, Si-Qing Zheng	Fast nearest neighbor algorithms on a linear array with a reconfigurable pipelined bus system.	ISPAN	1997	DBLP DOI BibTeX RDF	reconfigurable pipelined bus, nearest neighbor problem, O(log log n)time, n/sup 3/ processors, O(1) time, image processing, binary image, linear array, nearest neighbor algorithms
21	Hossam A. ElGindy, Arun K. Somani, Heiko Schröder 0001, Hartmut Schmeck, Andrew Spray	RMB - A Reconfigurable Multiple Bus Network.	HPCA	1996	DBLP DOI BibTeX RDF	Reconfigurable Multiple Bus Network, Multiprocessor systems, Permutation Routing, Interconnection Structure
21	Sandy Pavel, Selim G. Akl	Efficient Algorithms for the Hough Transform on Arrays with Reconfigurable Optical Buses.	IPPS	1996	DBLP DOI BibTeX RDF	arrays with reconfigurable optical buses, Hough transform
21	Tzong-Wann Kao, Shi-Jinn Horng	Computing Dominators and Its Applications on Processor Arrays with Reconfigurable Bus Systems.	ISPAN	1996	DBLP DOI BibTeX RDF	bridge-connected components, reconfigurable bus system, dominator, undirected graphs, bridge, dominator tree, biconnected components, articulation point
21	Serge Miguet, Yves Robert	Reduction Operations on a Distributed Memory Machine with a Reconfigurable Interconnection Network.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	reconfigurable interconnection network, reductionoperations, interconnection graph, transputer-based networks, graph theory, multiprocessor interconnection networks, distributed memory machine
21	Jacques Briat, M. Favre, Cláudio F. R. Geyer, Jacques Chassin de Kergommeaux	Schheduling of OR-parallel Prolog on a Scalable, Reconfigurable, Distributed-Memory Multiprocessor.	PARLE (2)	1991	DBLP DOI BibTeX RDF	OPERA, OR-parallel Prolog, reconfigurable multiprocessor, distributed-memory, WAM, Supernode, scalable multiprocessor
21	Pavel G. Zaykov, Georgi Kuzmanov, Georgi Nedeltchev Gaydadjiev	Reconfigurable Multithreading Architectures: A Survey.	SAMOS	2009	DBLP DOI BibTeX RDF
21	Luigi Carro, Stephan Wong	Introduction to the Future of Reconfigurable Computing and Processor Architectures.	SAMOS	2009	DBLP DOI BibTeX RDF
21	Zhiyuan Wang, Jianhua Huang, Ziming Guan	The SOBER Family Ciphers Reconfigurable Processing Architecture Design.	IAS	2009	DBLP DOI BibTeX RDF
21	Heiner Giefers, Marco Platzner	ARMLang: A language and compiler for programming reconfigurable mesh many-cores.	IPDPS	2009	DBLP DOI BibTeX RDF
21	Vu Manh Tuan, Naohiro Katsura, Hiroki Matsutani, Hideharu Amano	Evaluation of a multicore reconfigurable architecture with variable core sizes.	IPDPS	2009	DBLP DOI BibTeX RDF
21	Sofia A. Paredes, Gregor von Bochmann, Trevor J. Hall	Deploying agile photonic networks over reconfigurable optical networks.	ISCC	2009	DBLP DOI BibTeX RDF
21	Abderrahmane Bennis, Miriam Leeser, Gilead Tadmor	Implementing a Highly Parameterized Digital PIV System on Reconfigurable Hardware.	ASAP	2009	DBLP DOI BibTeX RDF
21	Yan Xiao, Zhenhua Duan, Pengcheng Nie	An Efficient Algorithm for Finding Empty Space for Reconfigurable Systems.	TASE	2009	DBLP DOI BibTeX RDF
21	Joseph Hassoun	Resiliency in Elemental Computing.	ARC	2009	DBLP DOI BibTeX RDF
21	Nazish Aslam, Mark Milward, Ahmet T. Erdogan, Tughrul Arslan	Code Compression and Decompression for Coarse-Grain Reconfigurable Architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
21	Gerard K. Rauwerda, Paul M. Heysters, Gerard J. M. Smit	Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
21	Katherine Compton, Scott Hauck	Automatic Design of Reconfigurable Domain-Specific Flexible Cores.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
21	Zhi Guo, Betul Buyukkurt, John Cortes, Abhishek Mitra, Walid A. Najjar	A Compiler Intermediate Representation for Reconfigurable Fabrics.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	FPGA, VHDL, Configurable computing, Intermediate representation
21	Jason C. Chen, Shao-Yi Chien	CRISP: Coarse-Grained Reconfigurable Image Stream Processor for Digital Still Cameras and Camcorders.	IEEE Trans. Circuits Syst. Video Technol.	2008	DBLP DOI BibTeX RDF
21	Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	coarse-grained FPGA, VLIW, ASIP
21	Kamana Sigdel, Mark Thompson 0001, Andy D. Pimentel, Todor P. Stefanov, Koen Bertels	System-Level Design Space Exploration of Dynamic Reconfigurable Architectures.	SAMOS	2008	DBLP DOI BibTeX RDF
21	David Johan Christensen, David Brandt, Kasper Støy, Ulrik Pagh Schultz	A unified simulator for Self-Reconfigurable Robots.	IROS	2008	DBLP DOI BibTeX RDF
21	Ho Seok Ahn, Young Min Baek, Inkyu Sa, Woo-Sung Kang, Jin Hee Na, Jin Young Choi 0002	Design of reconfigurable heterogeneous modular architecture for service robots.	IROS	2008	DBLP DOI BibTeX RDF
21	Antonio Carlos Schneider Beck, Mateus B. Rutzig, Georgi Gaydadjiev, Luigi Carro	Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications.	DATE	2008	DBLP DOI BibTeX RDF
21	Zhiming Chang, XinJun Mao, Zhichang Qi	Towards a Formal Model for Reconfigurable Software Architectures by Bigraphs.	WICSA	2008	DBLP DOI BibTeX RDF	Bigraph, Software Architecture, Reconfiguration
21	Carlo Curino, Luca Fossati, Vincenzo Rana, Francesco Redaelli, Marco D. Santambrogio, Donatella Sciuto	The Shining embedded system design methodology based on self dynamic reconfigurable architectures.	ASP-DAC	2008	DBLP DOI BibTeX RDF
21	Mirko Bordignon, Lars Lindegaard Mikkelsen, Ulrik Pagh Schultz	Implementing Flexible Parallelism for Modular Self-reconfigurable Robots.	SIMPAR	2008	DBLP DOI BibTeX RDF
21	Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa	On-the-fly attestation of reconfigurable hardware.	FPL	2008	DBLP DOI BibTeX RDF
21	Vlad Mihai Sima, Elena Moscu Panainte, Koen Bertels	Resource allocation algorithm and OpenMP extensions for parallel execution on a heterogeneous reconfigurable platform.	FPL	2008	DBLP DOI BibTeX RDF
21	Matthew A. Watkins, Mark J. Cianchetti, David H. Albonesi	Shared reconfigurable architectures for CMPS.	FPL	2008	DBLP DOI BibTeX RDF
21	Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa	Towards benchmarking energy efficiency of reconfigurable architectures.	FPL	2008	DBLP DOI BibTeX RDF
21	Lars Bauer, Muhammad Shafique 0001, Jörg Henkel	A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor.	FPL	2008	DBLP DOI BibTeX RDF
21	Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Götz Kappen, Tobias G. Noll	Application-specific reconfigurable processors.	FPL	2008	DBLP DOI BibTeX RDF
21	Claudio Brunelli, Fabio Garzia, Jari Nurmi, Fabio Campi, Damien Picard	Reconfigurable hardware: The holy grail of matching performance with programming productivity.	FPL	2008	DBLP DOI BibTeX RDF
21	Dirk Koch, Christian Beckhoff, Jürgen Teich	ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
21	Wenyin Fu, Katherine Compton	Active kernel monitoring to combat scheduler gaming in reconfigurable computing systems.	FPL	2008	DBLP DOI BibTeX RDF
21	Fabio Garzia, Claudio Brunelli, Davide Rossi, Jari Nurmi	Implementation of a floating-point matrix-vector multiplication on a reconfigurable architecture.	IPDPS	2008	DBLP DOI BibTeX RDF
21	Lukás Sekanina, Petr Mikusek	Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures.	EvoWorkshops	2008	DBLP DOI BibTeX RDF
21	Ting Liu 0007, Camel Tanougast, Serge Weber	A framework of architectural synthesis for dynamically reconfigurable FPGAs.	SoCC	2008	DBLP DOI BibTeX RDF
21	Syed Waqar Nabi, Cade C. Wells, Wim Vanderbauwhede	A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices.	SoCC	2008	DBLP DOI BibTeX RDF
21	J. Divyasree, H. Rajashekar, Kuruvilla Varghese	Dynamically reconfigurable regular expression matching architecture.	ASAP	2008	DBLP DOI BibTeX RDF
21	Ritesh Rajore, Ganesh Garga, H. S. Jamadagni, S. K. Nandy 0001	Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture.	ASAP	2008	DBLP DOI BibTeX RDF
21	Junji Kitamichi, Koji Ueda, Kenichi Kuroda	A Modeling of a Dynamically Reconfigurable Processor Using SystemC.	VLSI Design	2008	DBLP DOI BibTeX RDF
21	Frank Bouwens, Mladen Berekovic, Bjorn De Sutter, Georgi Gaydadjiev	Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array.	HiPEAC	2008	DBLP DOI BibTeX RDF
21	Zhen Zhang, Alain Greiner, Sami Taktak	A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip.	DAC	2008	DBLP DOI BibTeX RDF	2D-Mesh NoC, DSPIN, MP2-SoC, fault-tolerant, reconfiguration, routing algorithm
21	Antonio Carlos Schneider Beck, Mateus B. Rutzig, Georgi Gaydadjiev, Luigi Carro	Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems.	ARC	2008	DBLP DOI BibTeX RDF
21	Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis	Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
21	Lukás Sekanina	Evolutionary functional recovery in virtual reconfigurable circuits.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	FPGA, evolutionary algorithms, Dependability, evolvable hardware
21	Proshanta Saha, Tarek A. El-Ghazawi	A Methodology for Automating Co-Scheduling for Reconfigurable Computing Systems.	MEMOCODE	2007	DBLP DOI BibTeX RDF
21	Ricardo S. Ferreira 0001, Alisson Garcia, Tiago Teixeira, João M. P. Cardoso	A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures.	ISVLSI	2007	DBLP DOI BibTeX RDF
21	Simone Corbetta, Fabrizio Ferrandi, Massimo Morandi, Marco Novati, Marco D. Santambrogio, Donatella Sciuto	Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System.	ISVLSI	2007	DBLP DOI BibTeX RDF
21	Yoon-suk Jin, Yang-wook Kim, Jun Park	ARMO: Augmented Reality based Reconfigurable MOck-up.	ISMAR	2007	DBLP DOI BibTeX RDF
21	Wing On Fung, Tughrul Arslan	A multi-objective algorithm for the design of high performance reconfigurable architectures with embedded decoding.	IEEE Congress on Evolutionary Computation	2007	DBLP DOI BibTeX RDF
21	Mihai Sima, Michael McGuire	Embedded Reconfigurable Solution for OFDM Detection Over Fast Fading Radio Channels.	SiPS	2007	DBLP DOI BibTeX RDF
21	Chang-Seok Choi, Hanho Lee	A Partial Self-Reconfigurable Adaptive FIR Filter System.	SiPS	2007	DBLP DOI BibTeX RDF