Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
14 | Assim Sagahyroon |
From AHPL to VHDL: a course in hardware description languages. |
IEEE Trans. Educ. |
2000 |
DBLP DOI BibTeX RDF |
|
14 | J. M. Álvarez, Nieves Pavón, J. Ballesteros |
A Visual Simulation Environment for MIPS Based on VHDL. |
Computers and Education in the 21st Century |
2000 |
DBLP BibTeX RDF |
|
14 | Ayuko Takagi, Shogo Muramatsu, Hitoshi Kiya |
Motion Estimation With Power Scalability and its VHDL Model. |
ICIP |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Amjad Hajjar, Tom Chen 0001, Anneliese von Mayrhauser |
On statistical behavior of branch coverage in testing behavioral VHDL models. |
HLDVT |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Wolfgang Ecker, Mike Heuchling, Jochen Mades, Thomas Schneider 0006, André Windisch, Ke Yang |
VXML: VHDL Hardware Design Representation in XML. |
MBMV |
2000 |
DBLP BibTeX RDF |
|
14 | Jürgen Haase, Peter Schwarz, Peter Trappe, Wolfgang Vermeiren |
Erfahrungen mit VHDL-AMS bei der Simulation heterogener Systeme. |
MBMV |
2000 |
DBLP BibTeX RDF |
|
14 | Dietmar P. F. Möller |
Componetware; VHDL based embedded controller design methodology. |
ESM |
2000 |
DBLP BibTeX RDF |
|
14 | Fabian Vargas 0001, Alexandre M. Amory |
Recent Improvements on the Specification of Transient-Fault Tolerant VHDL Descriptions: A Case-Study for Area Overhead Analysis. |
SBCCI |
2000 |
DBLP BibTeX RDF |
|
14 | Vanderlei Moraes Rodrigues, Dominique Borrione, Philippe Georgelin |
An ACL2 Model of VHDL for Symbolic Simulation and Formal Verification. |
SBCCI |
2000 |
DBLP BibTeX RDF |
|
14 | Régis Leveugle, K. Hadjiat |
Optimized Generation of VHDL Mutants for Injection of Transition Errors. |
SBCCI |
2000 |
DBLP BibTeX RDF |
|
14 | Dunets Bohdan, Anatoly O. Melnyk |
The translator from SMP-description of algorithm to VHDL-model of ASIC23. |
CCU |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero |
Automatic Validation of Protocol Interfaces Described in VHDL. |
EvoWorkshops |
2000 |
DBLP DOI BibTeX RDF |
|
14 | José-Alejandro López Alcantud, Tom Kazmierski |
VHDL-AMS modeling of self-organizing neural systems. |
ISCAS |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Eduardo J. Peralías, Antonio J. Acosta 0001, Adoración Rueda, José L. Huertas |
VHDL-based behavioural description of pipeline ADCs. |
ISCAS |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Fabian Vargas 0001, Alexandre M. Amory, Raoul Velazco |
Fault-Tolerance in VHDL Description: Transient-Fault Injection & Early Reliability Estimation. |
LATW |
2000 |
DBLP BibTeX RDF |
|
14 | Thomas Schneider 0006, Jochen Mades, Manfred Glesner, André Windisch, Wolfgang Ecker |
An Open VHDL-AMS Simulation Framework. |
BMAS |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Martin Vogels, Bart De Smedt, Georges G. E. Gielen |
Modeling and Simulation of a Sigma-Delta Digital to Analog Converter Using VHDL-AMS. |
BMAS |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Martin Schubert |
VHDL Based Simulation of a Sigma-Delta A/D Converter. |
BMAS |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Pascal Bontoux, Fabien Mieyeville, Ian O'Connor, Frédéric Gaffiot, Gilles Jacquemod |
Design and Optimization of Optical Links Based on VHDL-AMS Modeling. |
BMAS |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Vishwashanth R. Kasulasrinivas, Harold W. Carter |
Modeling and Simulating Semiconductor Devices Using VHDL-AMS. |
BMAS |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Gabriel Stefan Popescu |
On Accommodating Particular Analog System Models with VHDL. |
BMAS |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Qiushuang Zhang, Ian G. Harris |
A domain coverage metric for the validation of behavioral VHDL descriptions. |
ITC |
2000 |
DBLP DOI BibTeX RDF |
|
14 | Ilkka Saastamoinen, Tapio Saramäki, Olli Vainio |
VHDL-based implementations of area and power efficient filter architectures. |
EUSIPCO |
2000 |
DBLP BibTeX RDF |
|
14 | James H. Aylor, Robert H. Klenke |
Performance Modeling and Analysis in VHDL. |
The VLSI Handbook |
1999 |
DBLP DOI BibTeX RDF |
|
14 | James R. Armstrong, F. Gail Gray, Meng-Wei Lin |
VHDL modeling and model testing for DSP applications. |
IEEE Trans. Ind. Electron. |
1999 |
DBLP DOI BibTeX RDF |
|
14 | Peter J. Ashenden, Philip A. Wilsey |
Principles for Language Extensions to VHDL to Support High-Level Modeling. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
14 | Mingye Liu, Dongxiao Zhang, Qingping Xu |
Technical decisions on several key problems in VHDL high level synthesis system. |
J. Comput. Sci. Technol. |
1999 |
DBLP DOI BibTeX RDF |
|
14 | Kimmo Kuusilinna, Timo Hämäläinen 0001, Jukka Saarinen |
Practical VHDL optimization for timing critical FPGA applications. |
Microprocess. Microsystems |
1999 |
DBLP DOI BibTeX RDF |
|
14 | Iain D. Craig |
VHDL for Logic Synthesis, by Andrew Rushton, Wiley, Chichester, UK, 1998, 375 pages, inc. Index (Hb, £29.95). |
Robotica |
1999 |
DBLP DOI BibTeX RDF |
|
14 | Peter J. Ashenden, Philip A. Wilsey |
Protected Shared Variables in VHDL: IEEE Standard 1076a. |
IEEE Des. Test Comput. |
1999 |
DBLP DOI BibTeX RDF |
|
14 | Tony P. W. Price, David M. Howard 0001, Alwyn V. Lewis, Andrew M. Tyrrell |
Adaptive microphone array beamforming for teleconferencing using VHDL and parallel architectures. |
PDP |
1999 |
DBLP DOI BibTeX RDF |
|
14 | John McCluskey |
Practical Applications of Recursive VHDL Components in FPGA Synthesis. |
FPGA |
1999 |
DBLP DOI BibTeX RDF |
|
14 | Paulo Gomes, Carlos Bento |
Automatic Conversion of VHDL Programs into Cases. |
ICCBR Workshops |
1999 |
DBLP BibTeX RDF |
|
14 | Hisashi Sasaki |
A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
14 | |
Java, VHDL-AMS, ADA or C for System Level Specifications? |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
14 | Marc Renaudin, Pascal Vivet, Frédéric Robin |
A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation. |
ASYNC |
1999 |
DBLP DOI BibTeX RDF |
|
14 | Cristina Barna, Wolfgang Rosenstiel |
Description and Classification of VHDL Objects in the Reuse Management System. |
MBMV |
1999 |
DBLP BibTeX RDF |
|
14 | Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero |
Simulation-based sequential equivalence checking of RTL VHDL. |
ICECS |
1999 |
DBLP DOI BibTeX RDF |
|
14 | László Varga 0003, Gábor Hosszú, Ferenc Kovács |
Circuit synthesis based on VHDL language transformations. |
ICECS |
1999 |
DBLP DOI BibTeX RDF |
|
14 | James Hwang, Cameron Patterson, Sujoy Mitra |
VHDL Placement Directives for Parametric IP Blocks. |
FCCM |
1999 |
DBLP DOI BibTeX RDF |
|
14 | Olaf Drögehorn, Oliver Terhorst, Heinz-Dieter Hümmer, Walter Geisselhardt |
Formal Specification and Verification of Communication-Systems for designing in VHDL. |
FBT |
1999 |
DBLP BibTeX RDF |
|
14 | M. Diepenhorst, Martijn van Veelen, J. A. G. Nijhuis, Lambert Spaanenburg |
Automatic generation of VHDL code for neural applications. |
IJCNN |
1999 |
DBLP DOI BibTeX RDF |
|
14 | Cordula Hansen, Francisco Nascimento, Wolfgang Rosenstiel |
An Approach for Extracting RT Timing Information to Annotate Algorithmic VHDL Specifications. |
DAC |
1999 |
DBLP DOI BibTeX RDF |
|
14 | Georg J. Kempa |
Entwurf digitaler Komponenten nachrichtentechnischer Systeme mit petrinetzmodellierten VHDL-Modellen. |
|
1999 |
RDF |
|
14 | Markus Pfaff |
Verfahren zur beschleunigten Systemsimulation mit VHDL durch Integration von externen Hardware-Software-Komponenten. |
|
1999 |
RDF |
|
14 | Markus Schutti |
Modellbildung und Verifikation von komplexen digitalen Schaltungen in einem Designflow basierend auf VHDL und Synthese. |
|
1999 |
RDF |
|
14 | Guido Schumacher |
Object oriented hardware specification and design with a language extension to VHDL. |
|
1999 |
RDF |
|
14 | Carlos A. Valderrama, François Naçabal, Pierre G. Paulin, Ahmed Amine Jerraya |
Automatic VHDL-C Interface Generation for Distributed Cosimulation: Application to Large Design Examples. |
Des. Autom. Embed. Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
14 | Martin Radetzki, Wolfram Putzke-Röming, Wolfgang Nebel |
A Unified Approach to Object-Oriented VHDL. |
J. Inf. Sci. Eng. |
1998 |
DBLP BibTeX RDF |
|
14 | Yee-Wing Hsieh, Steven P. Levitan |
Control / Data-Flow Analysis for VHDL Semantic Extraction. |
J. Inf. Sci. Eng. |
1998 |
DBLP BibTeX RDF |
|
14 | C.-J. Richard Shi |
Entity Overloading for Mixed-Signal Abstraction in VHDL. |
J. Inf. Sci. Eng. |
1998 |
DBLP BibTeX RDF |
|
14 | Nihal J. Godambe, C.-J. Richard Shi |
Behavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS. |
J. Electron. Test. |
1998 |
DBLP DOI BibTeX RDF |
behavioral fault modeling, noise, fault modeling, fault simulation, jitter, analog test |
14 | Vytautas Stuikys |
Design of Reusable VHDL Component Using External Functions. |
Informatica |
1998 |
DBLP DOI BibTeX RDF |
|
14 | Ronald Herrmann |
Effizientes symbolisches Model-Checking von Realzeitaspekten für VHDL. |
|
1998 |
RDF |
|
14 | Ben Cohen |
VHDL answers to frequently asked questions (2. ed.). |
|
1998 |
RDF |
|
14 | Jérome Boué, Philippe Pétillon, Yves Crouzet |
MEFISTO-L: A VHDL-Based Fault Injection Tool for the Experimental Assessment of Fault Tolerance. |
FTCS |
1998 |
DBLP DOI BibTeX RDF |
|
14 | Abdellatif Ben Rabaa, Abdelkerim Zitouni, Mohamed Abid, Rached Tourki |
Implementation of an acoustic echo canceller based on NLMS-neural networks structures by using the VHDL. |
ICC |
1998 |
DBLP DOI BibTeX RDF |
|
14 | Alberto Allara, Massimo Bombana, Patrizia Cavalloro, Wolfgang Nebel, Wolfram Putzke-Röming, Martin Radetzki |
ATM Cell Modelling using Objective VHDL. |
ASP-DAC |
1998 |
DBLP DOI BibTeX RDF |
|
14 | Fahim Rahim-Sarwary, Emmanuelle Encrenaz, Michel Minoux, Rajesh K. Bawa |
Modular model checking of VLSI designs described in VHDL. |
CATA |
1998 |
DBLP BibTeX RDF |
|
14 | Stefan Reichör, Markus Pfaff, Markus Schutti |
Integration externer Komponenten in den Simulationsablauf von VHDL. |
MBMV |
1998 |
DBLP BibTeX RDF |
|
14 | Nikolaus Lange, Matthias Mutz |
Formale Verifikation eines funktionalen VHDL Modells der J1850 Busarbitrierung. |
MBMV |
1998 |
DBLP BibTeX RDF |
|
14 | Peter Thole, Wolfgang Rosenstiel |
Profilierung von VHDL-Prozessen mit minimierten Aufwand. |
MBMV |
1998 |
DBLP BibTeX RDF |
|
14 | Vanderlei Moraes Rodrigues, Flávio Rech Wagner |
A Temporal Logic for Data-Flow VHDL. |
SBCCI |
1998 |
DBLP DOI BibTeX RDF |
|
14 | Jose Edinson Aedo Cobo, Wilhelmus A. M. Van Noije |
VHDL Models for High Level Synthesis of Fuzzy Logic Controllers. |
SBCCI |
1998 |
DBLP DOI BibTeX RDF |
|
14 | David Déharbe, Subash Shankar, Edmund M. Clarke |
Formal Verification of VHDL ¾ The Model Checker CV. |
SBCCI |
1998 |
DBLP DOI BibTeX RDF |
|
14 | Tania Vassileva, Vassilliy Tchoumatchenko, Ilario Astinov, Ivan Furnadjiev |
Virtual VHDL laboratory. |
ICECS |
1998 |
DBLP DOI BibTeX RDF |
|
14 | Nicolás J. Medrano-Marqués, Bonifacio Martín-del-Brío |
General purpose neuroemulator architecture: design and VHDL simulation. |
ICECS |
1998 |
DBLP DOI BibTeX RDF |
|
14 | Peter Frey, Kathiresan Nellayappan, Vasudevan Sahnmugasundaram, Ramesh Sankaran Mayiladuthurai, Chetput L. Chandrashekar, Harold W. Carter |
SEAMS: Simulation Environment for VHDL-AMS. |
WSC |
1998 |
DBLP DOI BibTeX RDF |
|
14 | Mike Mills, Greg Peterson |
Hardware/Software Co-Design: VHDL and Ada 95 Code Migration and Integrated Analysis. |
SIGAda |
1998 |
DBLP DOI BibTeX RDF |
Ada |
14 | Robert L. Popp, David J. Montana, Richard R. Gassner, Gordon Vidaver, Suraj Iyer |
Automated hardware design using genetic programming, VHDL, and FPGAs. |
SMC |
1998 |
DBLP DOI BibTeX RDF |
|
14 | D. Corvino, Italo Epicoco, Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto |
Automatic VHDL restructuring for RTL synthesis optimization and testability improvement. |
ICCD |
1998 |
DBLP DOI BibTeX RDF |
|
14 | F. S. Bietti, Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto |
VHDL Testability Analysis Based on Fault Clustering and Implicit Fault Injection. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
|
14 | Vijay A. Nebhrajani, Nayan Suthar |
Finite State Machines: A Deeper Look into Synthesis Optimization for VHDL. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
|
14 | Morris Mengwei Lin |
A Test Planning System for Functional Validation of VHDL DSP Models. |
|
1998 |
RDF |
|
14 | |
VHDL fault injection questioned. |
IEEE Des. Test Comput. |
1997 |
DBLP BibTeX RDF |
|
14 | Donatella Sciuto |
Special section on VHDL. |
J. Syst. Archit. |
1997 |
DBLP DOI BibTeX RDF |
|
14 | Cristiana Bolchini, Luciano Baresi |
Software methodologies in VHDL code analysis. |
J. Syst. Archit. |
1997 |
DBLP DOI BibTeX RDF |
|
14 | Venkatram Krishnaswamy, Rajesh Gupta 0001, Prithviraj Banerjee |
Implications of VHDL timing models on simulation and software synthesis. |
J. Syst. Archit. |
1997 |
DBLP DOI BibTeX RDF |
|
14 | Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli |
Post-synthesis back-annotation of timing information in behavioral VHDL. |
J. Syst. Archit. |
1997 |
DBLP DOI BibTeX RDF |
|
14 | William Fornaciari, Paolo Gubian, Donatella Sciuto, Cristina Silvano |
A VHDL-based approach for power estimation of embedded systems. |
J. Syst. Archit. |
1997 |
DBLP DOI BibTeX RDF |
|
14 | Martin V. Künzli |
Vom Gatter zu VHDL - eine Einführung in die Digitaltechnik. |
|
1997 |
RDF |
|
14 | J. P. Castellano, A. Suarez, J. C. Bordon |
Intermediate representations of concurrent VHDL-based specifications. |
PDP |
1997 |
DBLP BibTeX RDF |
|
14 | Volkmar Sieh, Oliver Tschäche, Frank Balbach |
VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault Descriptions. |
FTCS |
1997 |
DBLP DOI BibTeX RDF |
|
14 | Steffen Dolling, Dirk Timmermann, Andreas Wassatsch |
Digit-On-Line-Architekturen und VHDL-Cores für die Umsetzung von schnellen seriellen MSD-First-Signalverarbeitungsalgorithmen. |
ARCS |
1997 |
DBLP BibTeX RDF |
|
14 | Jinian Bian, Hongxi Xue, Ming Su |
VIDE: a visual VHDL integrated design environment. |
ASP-DAC |
1997 |
DBLP DOI BibTeX RDF |
|
14 | Venkatram Krishnaswamy, Rajesh Gupta 0001, Prithviraj Banerjee |
A procedure for software synthesis from VHDL models. |
ASP-DAC |
1997 |
DBLP DOI BibTeX RDF |
|
14 | John V. McCanny, Douglas Ridge, Yi Hu, Jill K. Hunter |
Hierarchical VHDL libraries for DSP ASIC design. |
ICASSP |
1997 |
DBLP DOI BibTeX RDF |
|
14 | Seow Chuan Lim, Arthur Robert Temple, Simon Jones 0001, Ray Meddis |
VHDL-based design of biologically inspired pitch detection system. |
ICNN |
1997 |
DBLP DOI BibTeX RDF |
|
14 | Ching-Chuen Jong, Y. Y. H. Lam, L. S. Ng |
FPGA implementation of a digital IQ demodulator using VHDL. |
FPL |
1997 |
DBLP DOI BibTeX RDF |
|
14 | Kathi Fisler, Robert P. Kurshan |
Verifying VHDL Designs with COSPAN. |
Formal Hardware Verification |
1997 |
DBLP DOI BibTeX RDF |
|
14 | Nectarios Koziris, Theodore Andronikos, George Economakos, George K. Papakonstantinou, Panayotis Tsanakas |
Automatic Hardware Synthesis of Nested Loops Using UET Grids and VHDL. |
HPCN |
1997 |
DBLP DOI BibTeX RDF |
|
14 | Angus Wu |
Interactive learning toolbox for logic synthesis with VHDL. |
MSE |
1997 |
DBLP DOI BibTeX RDF |
|
14 | P. L. Jones |
Getting started with VHDL. |
MSE |
1997 |
DBLP DOI BibTeX RDF |
|
14 | Tsai Chi Huang, Roy W. Melton, Philip R. Bingham, Cecil O. Alford, Farzad Ghannadian |
The teaching of VHDL in computer architecture. |
MSE |
1997 |
DBLP DOI BibTeX RDF |
|
14 | Natividad Martínez Madrid, Peter T. Breuer, Carlos Delgado Kloos |
A semantic model for VHDL-AMS. |
CHARME |
1997 |
DBLP BibTeX RDF |
|
14 | Subash Shankar, James R. Slagle |
A polymodal semantics for VHDL. |
CHARME |
1997 |
DBLP BibTeX RDF |
|
14 | Dominique Borrione, F. Vestman, H. Bouamama |
An approach to Verilog-VHDL interoperability for synchronous designs. |
CHARME |
1997 |
DBLP BibTeX RDF |
|
14 | M. Bacis, Giacomo Buonanno, Fabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto |
Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels. |
ICCD |
1997 |
DBLP DOI BibTeX RDF |
|
14 | Ahmed E. Barbour, Mike P. Nassif |
Basic Concepts of Hardware Verification Using ORA Larch/VHDL. |
PDPTA |
1997 |
DBLP BibTeX RDF |
|
14 | Charles E. Stroud, M. Ding, S. Seshadri, Ramesh Karri, I. Kim, Subhajit Roy 0001, S. Wu |
A Parameterized VHDL Library for On-Line Testing. |
ITC |
1997 |
DBLP DOI BibTeX RDF |
|