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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 15796 occurrences of 4131 keywords
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Results
Found 37106 publication records. Showing 37106 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Anna Wang 0001, Junfang Liu, Hao Wang, Ran Tao |
A Novel Fault Diagnosis of Analog Circuit Algorithm Based on Incomplete Wavelet Packet Transform and Improved Balanced Binary-Tree SVMs. |
LSMS (1) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Munkang Choi, Linda S. Milor |
Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Natasa Miskov-Zivanov, Diana Marculescu |
Circuit Reliability Analysis Using Symbolic Techniques. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Jorge Campos, Hussain Al-Asaad |
Circuit Profiling Mechanisms for High-Level {ATPG}. |
MTV |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Shan Jiang, Manh Anh Do, Kiat Seng Yeo |
A 200-MHz CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs. |
VLSI-SoC |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Hsin-Chou Chi, Chia-Ming Wu |
An Efficient Scheduler for Circuit-Switched Network-on-Chip Architectures. |
VLSI-SoC |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Tadayoshi Enomoto, Nobuaki Kobayashi |
A low dynamic power and low leakage power 90-nm CMOS square-root circuit. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Sean X. Shi, Peng Yu, David Z. Pan |
A unified non-rectangular device and circuit simulation model for timing and power. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
physical design, VLSI CAD, device modeling |
17 | Song Guo, Hoi Lee |
A low-power active substrate-noise decoupling circuit with feedforward compensation for mixed-signal SoCs. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
active substrate noise decoupling, feedforward frequency compensation, substrate noise suppression, system-on-a-chip |
17 | Mo M. Zhang, Paul J. Hurst |
Effect of nonlinearity in the CMFB circuit that uses the differential-difference amplifier. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Jin-Tai Yan, Kai-Ping Lin, Yue-Fong Luo |
Floorplan-aware decoupling capacitance budgeting on equivalent circuit model. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Ayhan A. Mutlu, Charles Kwong, Abir Mukherjee, Mahmud Rahman |
Statistical circuit performance variability minimization under manufacturing variations. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Daniel Mueller 0001, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann |
Fast evaluation of analog circuit structures by polytopal approximations. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | R. Jancke, P. Schwarz |
Supporting analog synthesis by abstracting circuit behavior using a modeling methodology. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Hou-Ming Chen, Chih-Liang Huang, Robert Chen-Hao Chang |
A new temperature-compensated CMOS bandgap reference circuit for portable applications. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Jun-Hong Weng, Meng-Ting Tsai, Jung-Mao Lin, Ching-Yuan Yang |
A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Haleh Vahedi, Radu Muresan, Stefano Gregori |
On-chip current flattening circuit with dynamic voltage scaling. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Rajesh Garg, Mario Sánchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri |
A design flow to optimize circuit delay by using standard cells and PLAs. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
PLA, standard cell |
17 | Takayuki Sato, Kazuyuki Amano, Akira Maruoka |
On the Negation-Limited Circuit Complexity of Sorting and Inverting k-tonic Sequences. |
COCOON |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Kenji Ohno, Hiroki Matsumoto, Kenji Murao |
A Switched-Voltage High-Accuracy Sample/Hold Circuit. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Shan Gao, Junning Chen, Daoming Ke, Xiulong Wu |
A Compact Equivalent Circuit Model of HVLDMOS and Application in HIVC Design. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar |
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
pareto surfaces, performance space, optimization, yield |
17 | Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen |
Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
application-specific designs, low-power, NOC, SOC |
17 | Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri |
A PLA based asynchronous micropipelining approach for subthreshold circuit design. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
micro-pipelining, asynchronous, PLA, sub-threshold |
17 | Haiying Yuan, Guangju Chen |
Fault Diagnosis in Nonlinear Circuit Based on Volterra Series and Recurrent Neural Network. |
ICONIP (3) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Felipe Machado, Teresa Riesgo, Yago Torroja |
A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Preetham Lakshmikanthan, Adrian Nunez |
A Novel Methodology to Reduce Leakage Power in CMOS Complementary Circuits. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Xiaomeng Shi, Jianguo Ma, Kiat Seng Yeo, Manh Anh Do, Erping Li |
Equivalent circuit model of on-wafer CMOS interconnects for RFICs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Lech Józwiak, Szymon Bieganski |
High-quality Sub-function Construction in the Information-driven Circuit Synthesis with Gates. |
DSD |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Kenichi Okada, Yoshiaki Yoshihara, Hirotaka Sugawara, Kazuya Masu |
A dynamic reconfigurable RF circuit architecture. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Pascal T. Wolkotte, Gerard J. M. Smit, Gerard K. Rauwerda, Lodewijk T. Smit |
An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip. |
IPDPS |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Nicola Viarani, Nicola Massari, Massimo Gottardi |
A new switched capacitor circuit for parallel-pixel image processing [vision sensor integrated signal processing]. |
ISCAS (6) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Sheng-Yu Peng, Bradley A. Minch, Paul E. Hasler |
A programmable floating-gate bump circuit with variable width. |
ISCAS (5) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Fathi A. Farag, Carlos Galup-Montoro, Márcio C. Schneider |
Inverter-based switched current circuit for very low-voltage and low-power applications. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown |
Controlled-Load Limited Switch Dynamic Logic Circuit. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Chih-Jen Yen, Wen-Yaw Chung, Mely Chen Chi |
A Wide-Swing V_T-Referenced Circuit with Insensitivity to Device Mismatch. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Blair Schiffner, Jianhua Li, Laleh Behjat |
A Multivalue Eigenvalue Based Circuit Partitioning Technique. |
IWSOC |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Aseem Agarwal, Kaviraj Chopra, David T. Blaauw, Vladimir Zolotov |
Circuit optimization using statistical static timing analysis. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Valentine Kabanets, Russell Impagliazzo |
Derandomizing Polynomial Identity Tests Means Proving Circuit Lower Bounds. |
Comput. Complex. |
2004 |
DBLP DOI BibTeX RDF |
68Q17, 68Q15, Subject classification. 68Q10 |
17 | José C. García 0001, Juan A. Montiel-Nelson, Javier Sosa, Héctor Navarro |
A Direct Bootstrapped CMOS Large Capacitive-Load Driver Circuit. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Jin Soo Noh, Chang Gyun Park, Kang Hyeon Rhee |
Path Sensitization and Sub-circuit Partition of CUT Using t-Distribution for Pseudo-exhaustive Testing. |
AsiaSim |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik |
HiSIM: hierarchical interconnect-centric circuit simulator. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Chunyan Wang 0004, Kuo-Ting Wu |
Design of a pixel array circuit for thinning process. |
ISCAS (3) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Armin Tajalli, Saeid Mehrmanesh, Seyed Mojtaba Atarodi |
A duty cycle control circuit for high speed applications. |
ISCAS (1) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Kenneth P. Parker |
A New Probing Technique for High-Speed/High-Density Printed Circuit Boards. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Tushar S. Shelar, G. S. Visweswaran |
Inclusion of Thermal Effects in the Simulation of Bipolar Circuits using Circuit Level Behavioral Modeling. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Victor N. Kravets, Prabhakar Kudva |
Implicit enumeration of structural changes in circuit optimization. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
optimization, decomposition, technology mapping, physical synthesis, re-synthesis |
17 | Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm |
Worst-case circuit delay taking into account power supply variations. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
voltage fluctuations, static timing analysis, power grid |
17 | Yen-Chun Lin, Yao-Hsien Hsu, Chun-Keng Liu |
Constructing H4, a Fast Depth-Size Optimal Parallel Prefix Circuit. |
J. Supercomput. |
2003 |
DBLP DOI BibTeX RDF |
depth-size optimal, prefix circuits, size optimal, parallel algorithms, depth, fan-out |
17 | H. C. Srinivasaiah, Navakanta Bhat |
Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Raul Baños, Consolación Gil, Maria Dolores Gil Montoya, Julio Ortega Lopera |
A Parallel Evolutionary Algorithm for Circuit Partitioning. |
PDP |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Feng Lu 0002, Li-C. Wang, Kwang-Ting Cheng, Ric C.-Y. Huang |
A Circuit SAT Solver With Signal Correlation Guided Learning. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Lech Józwiak, Szymon Bieganski, Artur Chojnacki |
Information-driven Library-based Circuit Synthesis. |
DSD |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita |
A BIST Circuit for IDDQ Tests. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Gunnar Tufte, Pauline C. Haddow |
Building Knowledge into Developmental Rules for Circuit Design. |
ICES |
2003 |
DBLP DOI BibTeX RDF |
|
17 | C. Karnjanapiboon, Y. Rungruengphalanggul, Itsda Boonyaroonate |
The low stress voltage balance charging circuit for series connected batteries based on buck-boost topology. |
ISCAS (3) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Haigang Feng, Rouying Zhan, Qiong Wu 0013, Guang Chen, Xiaokang Guan, Haolu Xie, Albert Z. Wang |
Mixed-mode ESD protection circuit simulation-design methodology. |
ISCAS (4) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Tetsuya Fujiwara, Yoshihiko Horio, Kazuyuki Aihara |
An integrated multi-scroll circuit with floating-gate MOSFETs. |
ISCAS (3) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | P. C. Chen, James B. Kuo |
Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Ahmed S. Elwakil |
Nonautonomous pulse-driven chaotic oscillator based on Chua's circuit. |
ISCAS (3) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Sei Hyung Jang |
A new synchronous mirror delay with an auto-skew-generation circuit. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Armin Tajalli, Seyed Mojtaba Atarodi |
Structured design of an integrated subscriber line interface system and circuit. |
ISCAS (2) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula |
Computation and Refinement of Statistical Bounds on Circuit Delay. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Hao Yu 0001, Lei He 0001 |
Vector potential equivalent circuit based on PEEC inversion. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Santanu Chattopadhyay |
Efficient Circuit Specific Pseudoexhaustive Testing with Cellular Automata. |
Asian Test Symposium |
2002 |
DBLP DOI BibTeX RDF |
cellular automata, Test pattern generators, pseudoexhaustive testing |
17 | Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah |
Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Kazuo Aoyama |
A reconfigurable logic circuit based on threshold elements with a controlled floating gate. |
ISCAS (5) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Seraphim Poriazis |
The two-phase twisted-ring counter circuit. |
ISCAS (4) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Mika Kontiala, Aarne Heinonen, Jari Nurmi |
Low-power methodology issues in digital circuit design. |
ISCAS (1) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Jeng-Jie Peng, Ming-Dou Ker, Hsin-Chin Jiang |
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits. |
ISCAS (5) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | R. Timothy Edwards |
Circuit Morphologies and Ontogenies. |
Evolvable Hardware |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Peter M. Lee, Shinji Ito, Takeaki Hashimoto, Junji Sato, Tomomasa Touma, Goichi Yokomizo |
A Parallel and Accelerated Circuit Simulator with Precise Accuracy. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Wendy Belluomini, Chris J. Myers, H. Peter Hofstee |
Timed circuit verification using TEL structures. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Erik Lindberg, Krishnamurthy Murali, Arünas Tamasevicius |
Hyperchaotic circuit with damped harmonic oscillators. |
ISCAS (3) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Cong-Kha Pham |
A novel synapses circuit and its application to a neural-based A/D converter. |
ISCAS (3) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Jin-Ku Kang, Dong-Hee Kim |
A CMOS clock and data recovery with two-XOR phase-frequency detector circuit. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Kasin Vichienchom, Mark Clements, Wentai Liu |
A multi-gigabit CMOS data recovery circuit using an analog parallel sampling technique. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Alexander Fish, Orly Yadid-Pecht |
CMOS current/voltage mode winner-take-all circuit with spatial filtering. |
ISCAS (3) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Christian Pacha, Uwe Auer, Christian Burwick, Peter Glösekötter, Andreas Brennemann, Werner Prost, Franz-Josef Tegude, Karl F. Goser |
Threshold logic circuit design of parallel adders using resonant tunneling devices. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Takao Waho, Kazufumi Hattori, Kouji Honda |
Novel Resonant-Tunneling Multiple-Threshold Logic Circuit Based on Switching Sequence Detection. |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
Multiple-threshold, analog-to-digital converter, Resonant-tunneling diode |
17 | Gi-Noung Byun, Chol-U Lee, Seung-Yong Park, Heung-Soo Kim |
A Study on the Ternary Parallel Circuit Design with DCG Properties Based on the Matrix Equation. |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Madhu K. Iyer, Michael L. Bushnell |
Effect of Noise on Analog Circuit Testing. |
J. Electron. Test. |
1999 |
DBLP DOI BibTeX RDF |
analog test generation, noise analysis |
17 | Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch |
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. |
Asian Test Symposium |
1999 |
DBLP DOI BibTeX RDF |
BIST Design, Test, Low-power Design, Energy Consumption |
17 | Chandramouli Visweswariah, Andrew R. Conn |
Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation. |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Jing Shen, Koichi Tanno, Okihiko Ishizuka |
Down Literal Circuit with Neuron-MOS Transistors and Its Applications. |
ISMVL |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Yoshihiko Horio, Izumi Kobayashi, Masato Kawakami, Hiroshi Hayashi, Kazuyuki Aihara |
Switched-capacitor multi-internal-state chaotic neuron circuit with unipolar and bipolar output functions. |
ISCAS (5) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | L. Wu, Huiting Chen, S. Nagavarapu, Randall L. Geiger, Edward Lee, W. Black |
A monolithic 1.25 Gbits/sec CMOS clock/data recovery circuit for fibre channel transceiver. |
ISCAS (2) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss |
Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Irith Pomeranz, Sudhakar M. Reddy |
On methods to match a test pattern generator to a circuit-under-test. |
IEEE Trans. Very Large Scale Integr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Shih-Arn Hwang, Jin-Hua Hong, Cheng-Wen Wu |
Sequential circuit fault simulation using logic emulation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Daniel R. Brasen, Gabriele Saucier |
Using cone structures for circuit partitioning into FPGA packages. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Consolación Gil, Julio Ortega 0001, Antonio F. Díaz, Maria Dolores Gil Montoya, Alberto Prieto |
Load Balancing in Parallel Circuit Testing with Annealing-Based and Genetic Algorithms. |
PPSN |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Huiqun Liu, Kai Zhu 0001, D. F. Wong 0001 |
Circuit Partitioning with Complex Resource Constraints in FPGAs. |
FPGA |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Sameh W. Asaad, Kevin W. Warren |
Speed Optimization of the ALR Circuit Using an FPGA with Embedded RAM: A Design Experience. |
FPL |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Jason D. Lohn, Silvano Colombano |
Automated Analog Circuit Sythesis Using a Linear Representation. |
ICES |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Christer Svensson, Atila Alvandpour |
Low power and low voltage CMOS digital circuit techniques. |
ISLPED |
1998 |
DBLP DOI BibTeX RDF |
low power, CMOS, digital circuits, low voltage |
17 | Hassan O. Elwan, Mohammed Ismail 0001 |
Low Voltage Low power CMOS AGC circuit for wireless communication. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
Automatic gain control, Variable gain amplifier, dB-Linear |
17 | J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor |
Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors. |
Asian Test Symposium |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Andreas Jakoby, Christian Schindelhauer |
On the Complexity of Worst Case and Expected Time in a Circuit. |
STACS |
1996 |
DBLP DOI BibTeX RDF |
expected time, computational complexity, average case analysis, worst case, theory of parallel and distributed computation, timed circuits |
17 | Uming Ko, Poras T. Balsara |
Short-circuit power driven gate sizing technique for reducing power dissipation. |
IEEE Trans. Very Large Scale Integr. Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
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