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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 12478 occurrences of 5080 keywords
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Results
Found 19048 publication records. Showing 19048 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
11 | Chien-Hsing Wu 0002, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang |
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(3), pp. 375-380, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Stein's algorithm, Euclid's algorithm, Finite field, systolic array, division |
11 | Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng |
Efficient test solutions for core-based designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5), pp. 758-775, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian |
Distributed Diagnosis of Interconnections in SoC and MCM Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(3), pp. 291-307, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect test and diagnosis, performance fault diagnosis, design for testability for SOCs and MCMs, MISR reconfiguration |
11 | Genyuan Wang, Huiyong Liao, Haiquan Wang, Xiang-Gen Xia 0001 |
Systematic and optimal cyclotomic lattices and diagonal space-time block code designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 50(12), pp. 3348-3360, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | T. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang |
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 21(3), pp. 241-247, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Carla P. Gomes, Meinolf Sellmann, Cindy van Es, Harold van Es |
The Challenge of Generating Spatially Balanced Scientific Experiment Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CPAIOR ![In: Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems, First International Conference, CPAIOR 2004, Nice, France, April 20-22, 2004, Proceedings, pp. 387-394, 2004, Springer, 3-540-21836-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Xuandong Li, Jianhua Zhao, Gong Jiayu, Shi Yaoxin, Guoliang Zheng |
Verifying Compositional Designs for Scenario-Based Timing Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISORC ![In: 7th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2004), 12-14 May 2004, Vienna, Austria, pp. 253-256, 2004, IEEE Computer Society, 0-7695-2124-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Early ISS Integration into Network-on-Chip Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 443-452, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Nicolas Telle, Wayne Luk, Ray C. C. Cheung |
Customising Hardware Designs for Elliptic Curve Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 274-283, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 138-148, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Earl E. Swartzlander Jr. |
A Review of Large Parallel Counter Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 89-98, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Raul Silaghi |
Refining designs along middleware-specific concern-dimensions at different MDA-levels of abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OOPSLA Companion ![In: Companion to the 19th Annual ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications, OOPSLA 2004, October 24-28, 2004, Vancouver, BC, Canada, pp. 60-62, 2004, ACM, 1-58113-833-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
middleware concerns, AOP, MDA, model transformations, aspectJ, UML profiles, eclipse plug-ins, parallax, enterprise fondue |
11 | Raul Silaghi |
Refining designs along middleware-specific concern-dimensions at different MDA-levels of abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OOPSLA Companion ![In: Companion to the 19th Annual ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications, OOPSLA 2004, October 24-28, 2004, Vancouver, BC, Canada, pp. 318-319, 2004, ACM, 1-58113-833-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
middleware concerns, AOP, MDA, model transformations, aspectJ, UML profiles, eclipse plug-ins, parallax, enterprise fondue |
11 | Mehdi Baradaran Tahoori, Fabrizio Lombardi |
Testing of Quantum Dot Cellular Automata Based Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1408-1409, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Vicki L. Hanson |
The user experience: designs and adaptations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
W4A ![In: Proceedings of the International Cross-Disciplinary Workshop on Web Accessibility, New York, NY, USA, 17-22 May 2004, pp. 1-11, 2004, ACM, 1-58113-903-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
usability, standards, Web accessibility, Web design |
11 | Boumediene Belkhouche, Anastasia Nix, Johnette Hassell |
Plagiarism detection in software designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference ![In: Proceedings of the 42nd Annual Southeast Regional Conference, 2004, Huntsville, Alabama, USA, April 2-3, 2004, pp. 207-211, 2004, ACM, 1-58113-870-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | César Augusto Dueñas M. |
Verification and test challenges in SoC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 9, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Peng Yin 0003, Andrew J. Turberfield, John H. Reif |
Designs of Autonomous Unidirectional Walking DNA Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DNA ![In: DNA Computing, 10th International Workshop on DNA Computing, DNA 10, Milan, Italy, June 7-10, 2004, Revised Selected Papers, pp. 410-425, 2004, Springer, 3-540-26174-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Adriana J. Berlanga, Francisco J. García-Peñalvo |
Towards Adaptive Learning Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AH ![In: Adaptive Hypermedia and Adaptive Web-Based Systems, Third International Conference, AH 2004, Eindhoven, The Netherlands, August 23-26, 2004, Proceedings, pp. 372-375, 2004, Springer, 3-540-22895-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung |
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, USA, Proceedings, pp. 79-88, 2004, IEEE Computer Society, 0-7695-2230-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Beryl Plimmer, Mark D. Apperley |
INTERACTING with sketched interface designs: an evaluation study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI Extended Abstracts ![In: Extended abstracts of the 2004 Conference on Human Factors in Computing Systems, CHI 2004, Vienna, Austria, April 24 - 29, 2004, pp. 1337-1340, 2004, ACM, 1-58113-703-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
prototyping, scenario-based design, sketch tools |
11 | Iciar Font, Siep Weiland, Martijn Franken, Maarten Steinbuch, Loy Rovers |
Haptic feedback designs in teleoperation systems for minimal invasive surgery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMC (3) ![In: Proceedings of the IEEE International Conference on Systems, Man & Cybernetics: The Hague, Netherlands, 10-13 October 2004, pp. 2513-2518, 2004, IEEE, 0-7803-8566-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Jim Woodcock 0001, Ana Cavalcanti 0001 |
A Tutorial Introduction to Designs in Unifying Theories of Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFM ![In: Integrated Formal Methods, 4th International Conference, IFM 2004, Canterbury, UK, April 4-7, 2004, Proceedings, pp. 40-66, 2004, Springer, 3-540-21377-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex |
Interconnect width selection for deep submicron designs using the table lookup method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 41-44, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect sizing, power-delay trade-off, wire sizing |
11 | Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwini Verma |
XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 208-215, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Earl E. Lee II, John E. Mitchell 0001, William A. Wallace |
Assessing Vulnerability of Proposed Designs for Interdependent Infrastructure Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 37th Hawaii International Conference on System Sciences (HICSS-37 2004), CD-ROM / Abstracts Proceedings, 5-8 January 2004, Big Island, HI, USA, 2004, IEEE Computer Society, 0-7695-2056-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Ju-Hyun Lee, Sungkwon Kang, Hoo-Kyun Choi |
A Fast Construction Algorithm for the Incidence Matrices of a Class of Symmetric Balanced Incomplete Block Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (4) ![In: Computational Science and Its Applications - ICCSA 2004, International Conference, Assisi, Italy, May 14-17, 2004, Proceedings, Part IV, pp. 11-19, 2004, Springer, 3-540-22060-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu |
Failure Factor Based Yield Enhancement for SRAM Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 20-28, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Kui Huang, Zhaotao Zhou, Yanbo Han, Gang Li, Jing Wang 0002 |
An Algorithm for Calculating Process Similarity to Cluster Open-Source Process Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GCC Workshops ![In: Grid and Cooperative Computing - GCC 2004 Workshops: GCC 2004 International Workshops, IGKG, SGT, GISS, AAC-GEVO, and VVS, Wuhan, China, October 21-24, 2004. Proceedings, pp. 107-114, 2004, Springer, 3-540-23578-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Karthik Sundararaman, Shambhu J. Upadhyaya, Martin Margala |
Cost Model Analysis of DFT Based Fault Tolerant SOC Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 465-469, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Tobias Nopper, Christoph Scholl 0001 |
Approximate Symbolic Model Checking for Incomplete Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15-17, 2004, Proceedings, pp. 290-305, 2004, Springer, 3-540-23738-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Mehdi Baradaran Tahoori, Subhasish Mitra |
Interconnect Delay Testing of Designs on Programmable Logic Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 635-644, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Grzegorz Mrugalski, Chen Wang 0014, Artur Pogiel, Jerzy Tyszer, Janusz Rajski |
Fault Diagnosis in Designs with Convolutional Compactors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 498-507, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Manan Syal, Michael S. Hsiao, Sreejit Chakravarty |
Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1034-1043, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ali Reza Ejlali |
Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 3-5 March 2004, Papeete, Tahiti, pp. 327-332, 2004, IEEE Computer Society, 0-7695-2076-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Carlo Brandolese, William Fornaciari, Fabio Salice |
An area estimation methodology for FPGA based designs at systemc-level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 129-132, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
area metrics, FPGAs, systemc |
11 | Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani |
Integrated floorplanning with buffer/channel insertion for bus-based designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6), pp. 730-741, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Karim El Guemhioui |
A framework for distributing object-oriented designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 4(3), pp. 381-396, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Distributed systems, Object-oriented design, Coupling metrics |
11 | Yun Shao 0002, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara |
On Selecting Testable Paths in Scan Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(4), pp. 447-456, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
testable path, delay testing, delay fault, path delay fault, path selection |
11 | Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz |
On test data volume reduction for multiple scan chain designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(4), pp. 460-469, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Decompressor, Don't care identification, Encoding techniques, Design for testability, Test data compression |
11 | Alexander Klaiber, Sinclair Chau |
Automatic Detection of Logic Bugs in Hardware Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Fourth International Workshop on Microprocessor Test and Verification, Common Challenges and Solutions (MTV 2003), May 29-30, 2003, Hyatt Town Lake Hotel, Austin, Texas, USA, pp. 47-53, 2003, IEEE Computer Society, 0-7695-2045-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Behzad Akbarpour, Sofiène Tahar |
The Application of Formal Verification to SPW Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), Architectures, Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey, pp. 325-333, 2003, IEEE Computer Society, 0-7695-2003-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz |
Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 313-323, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | William DuMouchel, Deepak K. Agarwal |
Applications of sampling and fractional factorial designs to model-free data squashing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KDD ![In: Proceedings of the Ninth ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, Washington, DC, USA, August 24 - 27, 2003, pp. 511-516, 2003, ACM, 1-58113-737-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
data squashing, fractional factorial design, summary of massive datasets, stratified sampling |
11 | Xi Chen 0024, Harry Hsieh, Felice Balarin, Yosinori Watanabe |
Case Studies of Model Checking for Embedded System Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 18-20 June 2003, Guimaraes, Portugal, pp. 20-28, 2003, IEEE Computer Society, 0-7695-1887-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Michael J. Wirthlin, Darrel Eric Johnson, Nathan Rollins, Michael P. Caffrey, Paul S. Graham |
The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 8-11 April 2003, Napa, CA, USA, Proceedings, pp. 133-142, 2003, IEEE Computer Society, 0-7695-1979-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Thilo Pionteck, A. Garcya, Lukusa D. Kabulepa, Manfred Glesner |
The requirement for flexibility in IP-based designs increasesHardware Evaluation of Low Power Communication Mechanisms for Transport-Triggered Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 9-11 June 2003, San Diego, CA, USA, pp. 141-147, 2003, IEEE Computer Society, 0-7695-1943-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Vikas Chandra, Gary D. Carpenter, Jeffrey L. Burns |
Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 134-139, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Jaume Abella 0001, Antonio González 0001 |
Power Efficient Data Cache Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 8-13, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Mohammad M. Mansour, Amit Mehrotra |
Efficient core designs based on parameterized macrocells with accurate delay models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 517-520, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Margarita Valor, Francisco Albert, José María Gomis, Manuel Contero |
Analysis Tool for Cataloguing Textile and Tile Pattern Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (3) ![In: Computational Science and Its Applications - ICCSA 2003, International Conference, Montreal, Canada, May 18-21, 2003, Proceedings, Part III, pp. 569-578, 2003, Springer, 3-540-40156-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra |
Parameterized Macrocells with Accurate Delay Models for Core-Based Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 319-324, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Erik Larsson, Hideo Fujiwara |
Test Resource Partitioning and Optimization for SOC Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 319-324, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Huaxing Tang, Sudhakar M. Reddy, Irith Pomeranz |
On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 1079-1088, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Seongmoon Wang, Srimat T. Chakradhar |
A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 574-583, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Miroslav N. Velev |
Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 138-147, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Xijiang Lin, Rob Thompson |
Test generation for designs with multiple clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 662-667, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
clock domain, ATPG, scan design |
11 | Barbara A. Kitchenham, John Fry, Stephen G. Linkman |
The Case Against Cross-Over Designs in Software Engineering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STEP ![In: 11th International Workshop on Software Technology and Engineering Practice (STEP 2003), 19-21 September 2003, Amsterdam, The Netherlands, pp. 65-67, 2003, IEEE Computer Society, 0-7695-2218-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Jun Xu 0014, Mukesh Singhal |
Cost-Effective Flow Table Designs for High-Speed Routers: Architecture and Performance Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(9), pp. 1089-1099, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Flow table, performance analysis, router architecture, universal hashing |
11 | Yeow Meng Chee, Alan C. H. Ling |
Uniform Group Divisible Designs with Block Sizes Three and n. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Graphs Comb. ![In: Graphs Comb. 18(3), pp. 421-445, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai |
Optimal time borrowing analysis and timing budgeting optimization for latch-based designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(1), pp. 217-230, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
latch-based design, time borrowing, timing budgeting, static timing analysis, Cycle stealing |
11 | Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey |
Embedded Software-Based Self-Test for Programmable Core-Based Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 19(4), pp. 18-27, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Kanna Shimizu, David L. Dill |
Using Formal Specifications for Functional Validation of Hardware Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 19(4), pp. 96-106, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Luís Miguel Silveira, Nuno Vargas |
Characterizing Substrate Coupling in Deep-Submicron Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 19(2), pp. 4-15, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou |
Effective Error Diagnosis for RTL Designs in HDLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 362-367, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Dylan Carline, Paul Coulton |
A Novel Watermarking Technique for LUT Based FPGA Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 1152-1155, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi, James Hwang |
Automating Customisation of Floating-Point Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 523-533, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Oswaldo Cadenas, Graham M. Megson |
A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 322-331, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung |
On Optimum Designs of Universal Switch Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 142-151, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Oliver Diessel, Usama Malik, Keith So |
Towards High-Level Specification, Synthesis, and Virtualization of Programmable Logic Designs (Research Note). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2002, Parallel Processing, 8th International Euro-Par Conference Paderborn, Germany, August 27-30, 2002, Proceedings, pp. 314-318, 2002, Springer, 3-540-44049-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani |
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 56-61, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
floorplanning, routability, interconnect estimation |
11 | James Lin, Michael Thomsen, James A. Landay |
A visual language for sketching large and complex interactive designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI ![In: Proceedings of the CHI 2002 Conference on Human Factors in Computing Systems: Changing our World, Changing ourselves, Minneapolis, Minnesota, USA, April 20-25, 2002., pp. 307-314, 2002, ACM, 1-58113-453-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
denim, user interface design, visual language, web design |
11 | Rajesh K. Gupta 0001, Sandeep K. Shukla, Nick Savoiu |
Efficient Simulation of Synthesis-Oriented System Level Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 168-173, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
simulation, SystemC, system-level design |
11 | David E. Lackey, Paul S. Zuchowski, Thomas R. Bednar, Douglas W. Stout, Scott W. Gould, John M. Cohn |
Managing power and performance for System-on-Chip designs using Voltage Islands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 195-202, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Sasha Novakovsky, Shy Shyman, Ziyad Hanna |
High capacity and automatic functional extraction tool for industrial VLSI circuit designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 520-525, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Formal Equivalence Verification (FEV), Hardware Description Languages (HDL), Switch Level Analysis, functional abstraction, satisfiability procedures, synthesis, Design For Testability (DFT), logic simulation, Binary Decision Diagrams (BDDs) |
11 | Kevin Lano, David Clark 0001, Kelly Androutsopoulos |
From Implicit Specifications to Explicit Designs in Reactive System Development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFM ![In: Integrated Formal Methods, Third International Conference, IFM 2002, Turku, Finland, May 15-18, 2002, Proceedings, pp. 49-68, 2002, Springer, 3-540-43703-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
B AMN, RSDS, model-checking, UML, Reactive Systems |
11 | Natalino G. Busá, Ghiath Alkadi, Michael J. Verberne, Rafael Peset Llopis, Sethuraman Ramanatha |
RAPIDO: A Modular, Multi-Board, Heterogeneous Multi-Processor, PCI Bus Based Prototyping Framework for the Validation of SoC VLSI Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 1-3 July 2002, Darmstadt, Germany, pp. 159-165, 2002, IEEE Computer Society, 0-7695-1703-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh |
A Standard-Cell Placement Tool for Designs with High Row Utilization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 45-, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Pallab K. Chatterjee, Richard Goering |
Evening Panel Discussion: Are the Interoperability Standards for EDA Too Little/Too Late for Real SoC Designs? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 15, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham |
Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 275-280, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz |
On Test Data Volume Reduction for Multiple Scan Chain Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 103-110, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Amit R. Pandey, Janak H. Patel |
Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs . ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 9-15, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Ilkka Saastamoinen, David A. Sigüenza-Tortosa, Jari Nurmi |
Interconnect IP Node for Future System-on-Chip Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 116-122, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
System-on-Chip, reuse, on-chip communication, packet network |
11 | Yannick Bonhomme, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch |
Test Power: a Big Issue in Large SOC Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 447-449, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
DfT, BIST, Scan, Low Power Testing, Test Power |
11 | Haris Lekatsas, Jörg Henkel |
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 113-120, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
bus invert, low power, bus encoding |
11 | Yi-Min Jiang, Kwang-Ting Cheng |
Vector generation for power supply noise estimation and verification of deep submicron designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(2), pp. 329-340, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Abdel Ejnioui, N. Ranganathan |
A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(2), pp. 407-410, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Ramesh Karri, Balakrishnan Iyer |
Introspection: A register transfer level technique for cocurrent error detection and diagnosis in data dominated designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(4), pp. 505-515, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Concurrent error detection, register transfer level, on line testing |
11 | Serdar Tasiran, Kurt Keutzer |
Coverage Metrics for Functional Validation of Hardware Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 18(4), pp. 36-45, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Patrice Gerin, Sungjoo Yoo, Gabriela Nicolescu, Ahmed Amine Jerraya |
Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 63-68, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Michael L. Metz, Jack Jordan |
Verification of object-oriented simulation designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSC ![In: Proceedings of the 33nd conference on Winter simulation, WSC 2001, Arlington, VA, USA, December 9-12, 2001, pp. 600-603, 2001, WSC, 0-7803-7309-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Krissanapong Nandhasri, Jitkasem Ngarmnil |
Designs of analog and digital comparators with FGMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 25-28, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Svetla Nikova, Ventzislav Nikov |
Improvement of the Delsarte Bound for tau-Designs in Finite Polynomial Metric Spaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMACC ![In: Cryptography and Coding, 8th IMA International Conference, Cirencester, UK, December 17-19, 2001, Proceedings, pp. 191-204, 2001, Springer, 3-540-43026-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Mihaela Radu, Dan Pitica, Radu Munteanu, Cristian Posteuca |
Complex Reliability Evaluation of Voters for Fault Tolerant Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 331-336, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Debabrata Bagchi, Dipanwita Roy Chowdhury, Joy Mukherjee, Santanu Chattopadhyay |
A Novel Strategy to Test Core Based Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 122-127, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | N. V. Arvind, P. R. Suresh, V. Sivakumar, Chandrani Pal, Debaprasad Das |
Integrated Crosstalk And Oxide Integrity Analysis In Dsm Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 518-523, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell |
Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 365-370, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Tong Liu 0007, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi |
Testing and testable designs for one-time programmable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11), pp. 1370-1375, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai |
Timing optimization on routed designs with incremental placementand routing characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2), pp. 188-196, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Irith Pomeranz, Sudhakar M. Reddy |
Test-Point Insertion to Enhance Test Compaction for Scan Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2000 International Conference on Dependable Systems and Networks (DSN 2000) (formerly FTCS-30 and DCCA-8), 25-28 June 2000, New York, NY, USA, pp. 375-381, 2000, IEEE Computer Society, 0-7695-0707-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Scan design, test-point insertion, static test compaction |
|
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