Search results for "designs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Chien-Hsing Wu 0002, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang	High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m).	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Stein's algorithm, Euclid's algorithm, Finite field, systolic array, division
11	Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng	Efficient test solutions for core-based designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
11	Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian	Distributed Diagnosis of Interconnections in SoC and MCM Designs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	interconnect test and diagnosis, performance fault diagnosis, design for testability for SOCs and MCMs, MISR reconfiguration
11	Genyuan Wang, Huiyong Liao, Haiquan Wang, Xiang-Gen Xia 0001	Systematic and optimal cyclotomic lattices and diagonal space-time block code designs.	IEEE Trans. Inf. Theory	2004	DBLP DOI BibTeX RDF
11	T. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang	New Challenges in Delay Testing of Nanometer, Multigigahertz Designs.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
11	Carla P. Gomes, Meinolf Sellmann, Cindy van Es, Harold van Es	The Challenge of Generating Spatially Balanced Scientific Experiment Designs.	CPAIOR	2004	DBLP DOI BibTeX RDF
11	Xuandong Li, Jianhua Zhao, Gong Jiayu, Shi Yaoxin, Guoliang Zheng	Verifying Compositional Designs for Scenario-Based Timing Specifications.	ISORC	2004	DBLP DOI BibTeX RDF
11	Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Early ISS Integration into Network-on-Chip Designs.	SAMOS	2004	DBLP DOI BibTeX RDF
11	Nicolas Telle, Wayne Luk, Ray C. C. Cheung	Customising Hardware Designs for Elliptic Curve Cryptography.	SAMOS	2004	DBLP DOI BibTeX RDF
11	Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs.	SAMOS	2004	DBLP DOI BibTeX RDF
11	Earl E. Swartzlander Jr.	A Review of Large Parallel Counter Designs.	ISVLSI	2004	DBLP DOI BibTeX RDF
11	Raul Silaghi	Refining designs along middleware-specific concern-dimensions at different MDA-levels of abstraction.	OOPSLA Companion	2004	DBLP DOI BibTeX RDF	middleware concerns, AOP, MDA, model transformations, aspectJ, UML profiles, eclipse plug-ins, parallax, enterprise fondue
11	Raul Silaghi	Refining designs along middleware-specific concern-dimensions at different MDA-levels of abstraction.	OOPSLA Companion	2004	DBLP DOI BibTeX RDF	middleware concerns, AOP, MDA, model transformations, aspectJ, UML profiles, eclipse plug-ins, parallax, enterprise fondue
11	Mehdi Baradaran Tahoori, Fabrizio Lombardi	Testing of Quantum Dot Cellular Automata Based Designs.	DATE	2004	DBLP DOI BibTeX RDF
11	Vicki L. Hanson	The user experience: designs and adaptations.	W4A	2004	DBLP DOI BibTeX RDF	usability, standards, Web accessibility, Web design
11	Boumediene Belkhouche, Anastasia Nix, Johnette Hassell	Plagiarism detection in software designs.	ACM Southeast Regional Conference	2004	DBLP DOI BibTeX RDF
11	César Augusto Dueñas M.	Verification and test challenges in SoC designs.	SBCCI	2004	DBLP DOI BibTeX RDF
11	Peng Yin 0003, Andrew J. Turberfield, John H. Reif	Designs of Autonomous Unidirectional Walking DNA Devices.	DNA	2004	DBLP DOI BibTeX RDF
11	Adriana J. Berlanga, Francisco J. García-Peñalvo	Towards Adaptive Learning Designs.	AH	2004	DBLP DOI BibTeX RDF
11	Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung	Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs.	FCCM	2004	DBLP DOI BibTeX RDF
11	Beryl Plimmer, Mark D. Apperley	INTERACTING with sketched interface designs: an evaluation study.	CHI Extended Abstracts	2004	DBLP DOI BibTeX RDF	prototyping, scenario-based design, sketch tools
11	Iciar Font, Siep Weiland, Martijn Franken, Maarten Steinbuch, Loy Rovers	Haptic feedback designs in teleoperation systems for minimal invasive surgery.	SMC (3)	2004	DBLP DOI BibTeX RDF
11	Jim Woodcock 0001, Ana Cavalcanti 0001	A Tutorial Introduction to Designs in Unifying Theories of Programming.	IFM	2004	DBLP DOI BibTeX RDF
11	Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex	Interconnect width selection for deep submicron designs using the table lookup method.	SLIP	2004	DBLP DOI BibTeX RDF	interconnect sizing, power-delay trade-off, wire sizing
11	Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwini Verma	XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs.	ICCD	2004	DBLP DOI BibTeX RDF
11	Earl E. Lee II, John E. Mitchell 0001, William A. Wallace	Assessing Vulnerability of Proposed Designs for Interdependent Infrastructure Systems.	HICSS	2004	DBLP DOI BibTeX RDF
11	Ju-Hyun Lee, Sungkwon Kang, Hoo-Kyun Choi	A Fast Construction Algorithm for the Incidence Matrices of a Class of Symmetric Balanced Incomplete Block Designs.	ICCSA (4)	2004	DBLP DOI BibTeX RDF
11	Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu	Failure Factor Based Yield Enhancement for SRAM Designs.	DFT	2004	DBLP DOI BibTeX RDF
11	Kui Huang, Zhaotao Zhou, Yanbo Han, Gang Li, Jing Wang 0002	An Algorithm for Calculating Process Similarity to Cluster Open-Source Process Designs.	GCC Workshops	2004	DBLP DOI BibTeX RDF
11	Karthik Sundararaman, Shambhu J. Upadhyaya, Martin Margala	Cost Model Analysis of DFT Based Fault Tolerant SOC Designs.	ISQED	2004	DBLP DOI BibTeX RDF
11	Tobias Nopper, Christoph Scholl 0001	Approximate Symbolic Model Checking for Incomplete Designs.	FMCAD	2004	DBLP DOI BibTeX RDF
11	Mehdi Baradaran Tahoori, Subhasish Mitra	Interconnect Delay Testing of Designs on Programmable Logic Devices.	ITC	2004	DBLP DOI BibTeX RDF
11	Grzegorz Mrugalski, Chen Wang 0014, Artur Pogiel, Jerzy Tyszer, Janusz Rajski	Fault Diagnosis in Designs with Convolutional Compactors.	ITC	2004	DBLP DOI BibTeX RDF
11	Manan Syal, Michael S. Hsiao, Sreejit Chakravarty	Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks.	ITC	2004	DBLP DOI BibTeX RDF
11	Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ali Reza Ejlali	Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs.	PRDC	2004	DBLP DOI BibTeX RDF
11	Carlo Brandolese, William Fornaciari, Fabio Salice	An area estimation methodology for FPGA based designs at systemc-level.	DAC	2004	DBLP DOI BibTeX RDF	area metrics, FPGAs, systemc
11	Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani	Integrated floorplanning with buffer/channel insertion for bus-based designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
11	Karim El Guemhioui	A framework for distributing object-oriented designs.	Int. J. Softw. Tools Technol. Transf.	2003	DBLP DOI BibTeX RDF	Distributed systems, Object-oriented design, Coupling metrics
11	Yun Shao 0002, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara	On Selecting Testable Paths in Scan Designs.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	testable path, delay testing, delay fault, path delay fault, path selection
11	Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz	On test data volume reduction for multiple scan chain designs.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Decompressor, Don't care identification, Encoding techniques, Design for testability, Test data compression
11	Alexander Klaiber, Sinclair Chau	Automatic Detection of Logic Bugs in Hardware Designs.	MTV	2003	DBLP DOI BibTeX RDF
11	Behzad Akbarpour, Sofiène Tahar	The Application of Formal Verification to SPW Designs.	DSD	2003	DBLP DOI BibTeX RDF
11	K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz	Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations.	FPL	2003	DBLP DOI BibTeX RDF
11	William DuMouchel, Deepak K. Agarwal	Applications of sampling and fractional factorial designs to model-free data squashing.	KDD	2003	DBLP DOI BibTeX RDF	data squashing, fractional factorial design, summary of massive datasets, stratified sampling
11	Xi Chen 0024, Harry Hsieh, Felice Balarin, Yosinori Watanabe	Case Studies of Model Checking for Embedded System Designs.	ACSD	2003	DBLP DOI BibTeX RDF
11	Michael J. Wirthlin, Darrel Eric Johnson, Nathan Rollins, Michael P. Caffrey, Paul S. Graham	The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets.	FCCM	2003	DBLP DOI BibTeX RDF
11	Thilo Pionteck, A. Garcya, Lukusa D. Kabulepa, Manfred Glesner	The requirement for flexibility in IP-based designs increasesHardware Evaluation of Low Power Communication Mechanisms for Transport-Triggered Architectures.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
11	Vikas Chandra, Gary D. Carpenter, Jeffrey L. Burns	Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs.	ICCD	2003	DBLP DOI BibTeX RDF
11	Jaume Abella 0001, Antonio González 0001	Power Efficient Data Cache Designs.	ICCD	2003	DBLP DOI BibTeX RDF
11	Mohammad M. Mansour, Amit Mehrotra	Efficient core designs based on parameterized macrocells with accurate delay models.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
11	Margarita Valor, Francisco Albert, José María Gomis, Manuel Contero	Analysis Tool for Cataloguing Textile and Tile Pattern Designs.	ICCSA (3)	2003	DBLP DOI BibTeX RDF
11	Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra	Parameterized Macrocells with Accurate Delay Models for Core-Based Designs.	ISQED	2003	DBLP DOI BibTeX RDF
11	Erik Larsson, Hideo Fujiwara	Test Resource Partitioning and Optimization for SOC Designs.	VTS	2003	DBLP DOI BibTeX RDF
11	Huaxing Tang, Sudhakar M. Reddy, Irith Pomeranz	On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs.	ITC	2003	DBLP DOI BibTeX RDF
11	Seongmoon Wang, Srimat T. Chakradhar	A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs.	ITC	2003	DBLP DOI BibTeX RDF
11	Miroslav N. Velev	Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar Designs.	ITC	2003	DBLP DOI BibTeX RDF
11	Xijiang Lin, Rob Thompson	Test generation for designs with multiple clocks.	DAC	2003	DBLP DOI BibTeX RDF	clock domain, ATPG, scan design
11	Barbara A. Kitchenham, John Fry, Stephen G. Linkman	The Case Against Cross-Over Designs in Software Engineering.	STEP	2003	DBLP DOI BibTeX RDF
11	Jun Xu 0014, Mukesh Singhal	Cost-Effective Flow Table Designs for High-Speed Routers: Architecture and Performance Evaluation.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Flow table, performance analysis, router architecture, universal hashing
11	Yeow Meng Chee, Alan C. H. Ling	Uniform Group Divisible Designs with Block Sizes Three and n.	Graphs Comb.	2002	DBLP DOI BibTeX RDF
11	Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai	Optimal time borrowing analysis and timing budgeting optimization for latch-based designs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	latch-based design, time borrowing, timing budgeting, static timing analysis, Cycle stealing
11	Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey	Embedded Software-Based Self-Test for Programmable Core-Based Designs.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
11	Kanna Shimizu, David L. Dill	Using Formal Specifications for Functional Validation of Hardware Designs.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
11	Luís Miguel Silveira, Nuno Vargas	Characterizing Substrate Coupling in Deep-Submicron Designs.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
11	Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou	Effective Error Diagnosis for RTL Designs in HDLs.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
11	Dylan Carline, Paul Coulton	A Novel Watermarking Technique for LUT Based FPGA Designs.	FPL	2002	DBLP DOI BibTeX RDF
11	Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi, James Hwang	Automating Customisation of Floating-Point Designs.	FPL	2002	DBLP DOI BibTeX RDF
11	Oswaldo Cadenas, Graham M. Megson	A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs.	FPL	2002	DBLP DOI BibTeX RDF
11	Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung	On Optimum Designs of Universal Switch Blocks.	FPL	2002	DBLP DOI BibTeX RDF
11	Oliver Diessel, Usama Malik, Keith So	Towards High-Level Specification, Synthesis, and Virtualization of Programmable Logic Designs (Research Note).	Euro-Par	2002	DBLP DOI BibTeX RDF
11	Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani	Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs.	ISPD	2002	DBLP DOI BibTeX RDF	floorplanning, routability, interconnect estimation
11	James Lin, Michael Thomsen, James A. Landay	A visual language for sketching large and complex interactive designs.	CHI	2002	DBLP DOI BibTeX RDF	denim, user interface design, visual language, web design
11	Rajesh K. Gupta 0001, Sandeep K. Shukla, Nick Savoiu	Efficient Simulation of Synthesis-Oriented System Level Designs.	ISSS	2002	DBLP DOI BibTeX RDF	simulation, SystemC, system-level design
11	David E. Lackey, Paul S. Zuchowski, Thomas R. Bednar, Douglas W. Stout, Scott W. Gould, John M. Cohn	Managing power and performance for System-on-Chip designs using Voltage Islands.	ICCAD	2002	DBLP DOI BibTeX RDF
11	Sasha Novakovsky, Shy Shyman, Ziyad Hanna	High capacity and automatic functional extraction tool for industrial VLSI circuit designs.	ICCAD	2002	DBLP DOI BibTeX RDF	Formal Equivalence Verification (FEV), Hardware Description Languages (HDL), Switch Level Analysis, functional abstraction, satisfiability procedures, synthesis, Design For Testability (DFT), logic simulation, Binary Decision Diagrams (BDDs)
11	Kevin Lano, David Clark 0001, Kelly Androutsopoulos	From Implicit Specifications to Explicit Designs in Reactive System Development.	IFM	2002	DBLP DOI BibTeX RDF	B AMN, RSDS, model-checking, UML, Reactive Systems
11	Natalino G. Busá, Ghiath Alkadi, Michael J. Verberne, Rafael Peset Llopis, Sethuraman Ramanatha	RAPIDO: A Modular, Multi-Board, Heterogeneous Multi-Processor, PCI Bus Based Prototyping Framework for the Validation of SoC VLSI Designs.	IEEE International Workshop on Rapid System Prototyping	2002	DBLP DOI BibTeX RDF
11	Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh	A Standard-Cell Placement Tool for Designs with High Row Utilization.	ICCD	2002	DBLP DOI BibTeX RDF
11	Pallab K. Chatterjee, Richard Goering	Evening Panel Discussion: Are the Interoperability Standards for EDA Too Little/Too Late for Real SoC Designs?	ISQED	2002	DBLP DOI BibTeX RDF
11	Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham	Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs?	VTS	2002	DBLP DOI BibTeX RDF
11	Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz	On Test Data Volume Reduction for Multiple Scan Chain Designs.	VTS	2002	DBLP DOI BibTeX RDF
11	Amit R. Pandey, Janak H. Patel	Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs .	VTS	2002	DBLP DOI BibTeX RDF
11	Ilkka Saastamoinen, David A. Sigüenza-Tortosa, Jari Nurmi	Interconnect IP Node for Future System-on-Chip Designs.	DELTA	2002	DBLP DOI BibTeX RDF	System-on-Chip, reuse, on-chip communication, packet network
11	Yannick Bonhomme, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch	Test Power: a Big Issue in Large SOC Designs.	DELTA	2002	DBLP DOI BibTeX RDF	DfT, BIST, Scan, Low Power Testing, Test Power
11	Haris Lekatsas, Jörg Henkel	ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	bus invert, low power, bus encoding
11	Yi-Min Jiang, Kwang-Ting Cheng	Vector generation for power supply noise estimation and verification of deep submicron designs.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
11	Abdel Ejnioui, N. Ranganathan	A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
11	Ramesh Karri, Balakrishnan Iyer	Introspection: A register transfer level technique for cocurrent error detection and diagnosis in data dominated designs.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	Concurrent error detection, register transfer level, on line testing
11	Serdar Tasiran, Kurt Keutzer	Coverage Metrics for Functional Validation of Hardware Designs.	IEEE Des. Test Comput.	2001	DBLP DOI BibTeX RDF
11	Patrice Gerin, Sungjoo Yoo, Gabriela Nicolescu, Ahmed Amine Jerraya	Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures.	ASP-DAC	2001	DBLP DOI BibTeX RDF
11	Michael L. Metz, Jack Jordan	Verification of object-oriented simulation designs.	WSC	2001	DBLP DOI BibTeX RDF
11	Krissanapong Nandhasri, Jitkasem Ngarmnil	Designs of analog and digital comparators with FGMOS.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
11	Svetla Nikova, Ventzislav Nikov	Improvement of the Delsarte Bound for tau-Designs in Finite Polynomial Metric Spaces.	IMACC	2001	DBLP DOI BibTeX RDF
11	Mihaela Radu, Dan Pitica, Radu Munteanu, Cristian Posteuca	Complex Reliability Evaluation of Voters for Fault Tolerant Designs.	ISQED	2001	DBLP DOI BibTeX RDF
11	Debabrata Bagchi, Dipanwita Roy Chowdhury, Joy Mukherjee, Santanu Chattopadhyay	A Novel Strategy to Test Core Based Designs.	VLSI Design	2001	DBLP DOI BibTeX RDF
11	N. V. Arvind, P. R. Suresh, V. Sivakumar, Chandrani Pal, Debaprasad Das	Integrated Crosstalk And Oxide Integrity Analysis In Dsm Designs.	VLSI Design	2001	DBLP DOI BibTeX RDF
11	Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell	Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations.	VLSI Design	2001	DBLP DOI BibTeX RDF
11	Tong Liu 0007, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi	Testing and testable designs for one-time programmable FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
11	Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai	Timing optimization on routed designs with incremental placementand routing characterization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
11	Irith Pomeranz, Sudhakar M. Reddy	Test-Point Insertion to Enhance Test Compaction for Scan Designs.	DSN	2000	DBLP DOI BibTeX RDF	Scan design, test-point insertion, static test compaction