Search results for "instruction"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Sue M. Gray, Rod Adams, G. J. Green, Gordon B. Steven	Static instruction scheduling for the HARP multiple-instruction-issue architecture.	Microprocess. Microsystems	1993	DBLP DOI BibTeX RDF
18	Liang Wang 0016	Instruction scheduling for a family of multiple instruction issue architectures.		1993	RDF
18	David R. Kaeli, Philip G. Emma, Joshua W. Knight, Thomas R. Puzak	Contrasting instruction-fetch time and instruction-decode time branch prediction mechanisms: Achieving synergy through their cooperative operation.	Microprocess. Microprogramming	1992	DBLP DOI BibTeX RDF
18	Komei Kato, Takaya Arita, Masahiro Sowa	Delayed instruction execution on a long instruction word (LIW) computer.	Syst. Comput. Jpn.	1992	DBLP DOI BibTeX RDF
18	Chih-Po Wen	Improving instruction supply efficiency in superscalar architectures using instruction trace buffers.	SAC	1992	DBLP DOI BibTeX RDF
18	Gideon D. Intrater, Ilan Y. Spillinger	Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers.	ISCA	1992	DBLP DOI BibTeX RDF
18	Erik Dirkx	CRISC Configurable Reduced Instruction Set Computer or Complex Reconfigurable Instruction Set Computer.	Microprocess. Microprogramming	1988	DBLP DOI BibTeX RDF
18	Thomas Tensi	Worst case analysis for reducing algorithms on instruction systolic arrays with simple instruction sets.	Parcella	1988	DBLP DOI BibTeX RDF
18	V. Lonnie Lawson	Using a computer-assisted instruction program as an alternative to the traditional library orientation/instruction tour: An evaluative study.		1988	RDF
18	Kevin J. McNeley, Veljko M. Milutinovic	Emulating a Complex Instruction Set Computer with a Reduced Instruction Set Computer.	IEEE Micro	1987	DBLP DOI BibTeX RDF
18	Andrew Tellop	Two methods of instruction for an introductory computer programming course: a language oriented vs a non-language oriented method of instruction.	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
18	Gregory F. Grohoski, Janak H. Patel	A performance model for instruction prefetch in pipelined instruction units.	ICPP	1982	DBLP BibTeX RDF
18	B. Ramakrishna Rau, George E. Rossman	The Effect of Instruction Fetch Strategies upon the Performance of Pipelined Instruction Units.	ISCA	1977	DBLP DOI BibTeX RDF
18	Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris	Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	instruction-level error, microprocessor controller, Fault simulation, concurrent error detection
18	Hu Chen, Sheng Liu 0001, Shuming Chen	A Novel Highly Scalable Architecture with Partially Distributed Pipeline and Hardware/Software Instruction Encoding.	NAS	2011	DBLP DOI BibTeX RDF	distributed commitment, clustered architecture, distributed execution, instruction encoding
18	Walter Yuan-Hwa Li, Chin-Ling Huang, Chung-Ping Chung	Tolerating Load Miss-Latency by Extending Effective Instruction Window with Low Complexity.	ICPP	2011	DBLP DOI BibTeX RDF	Execute Ahead, Hardware Speculation, Instruction-Level Parallelism, Processor Architecture, Memory-Level Parallelism, Runahead Execution
18	Tony M. Brewer	Instruction Set Innovations for the Convey HC-1 Computer.	IEEE Micro	2010	DBLP DOI BibTeX RDF	hybrid-core computing, FPGAs, reconfigurable computing, heterogeneous computing, accelerators, coprocessors, instruction set design
18	James Z. Wang 0002, Timothy A. Davis 0002, James Westall, Pradip K. Srimani	Undergraduate database instruction with MeTube.	ITiCSE	2010	DBLP DOI BibTeX RDF	CPATH, MeTube, TEXNH, problem-based instruction, DBMS
18	Jun Zhang, Kuizhi Mei, Jizhong Zhao	An Adaptive and Selective Instruction Active Push Mechanism for Multi-core Architecture.	NAS	2010	DBLP DOI BibTeX RDF	Chip Multi-core, Instruction Pre-fetch, Active Push, Adaptation, Memory System, Confidence Estimation
18	Andrey Mokhov, Arseniy Alekseyev, Alexandre Yakovlev	Automated Synthesis of Instruction Codes in the Context of Micro-architecture Design.	ACSD	2010	DBLP DOI BibTeX RDF	synthesis, microarchitecture, partial orders, instruction set, asynchronous control
18	Luis C. Aparicio, Juan Segarra, Clemente Rodríguez, Víctor Viñals	Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems.	RTCSA	2010	DBLP DOI BibTeX RDF	prefetch, WCET, instruction cache
18	Yu-Teng Chang, Chih-Yao Lo, Ping-Chang Chen	Study on Adaptive Computer-Assisted Instruction for In-Service Training.	AMT	2009	DBLP DOI BibTeX RDF	In-Service Training, Adaptive Computer-Assisted Instruction, e-Learning
18	Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli	Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2m).	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Microprocessor/microcomputer applications, Performance Evaluation, Cryptography, Elliptic curves, Public key cryptosystems, Processor Architectures, Pipeline processors, Portable devices, Hardware/software interfaces, Instruction set design
18	Feihu Hu, Liang Fu, Le Liu, Guanqun Zhang	An Algorithm about Transforming PLC Ladder Diagram to Instruction List Based on Series-Parallel Merging Method.	PACIIA (1)	2008	DBLP DOI BibTeX RDF	ladder diagram, instruction list, PLC
18	Jim Blythe, Thomas A. Russ	Case-based reasoning for procedure learning by instruction.	IUI	2008	DBLP DOI BibTeX RDF	learning by instruction, procedure learning, knowledge acquisition
18	Joe Gebis, David A. Patterson 0001	Embracing and Extending 20th-Century Instruction Set Architectures.	Computer	2007	DBLP DOI BibTeX RDF	instruction set architectures, PowerPC, SIMD processors, vector architecture
18	Jui-ni Sun, Yu-Chen Hsu	A Study of Learners' Perceptions of the Interactivity of Web-Based Instruction.	HCI (4)	2007	DBLP DOI BibTeX RDF	Interactivity, satisfaction, usefulness, ease of use, Web-based instruction
18	Daiji Kobayashi, Hiroaki Murata, Sakae Yamamoto	Study on the Instruction Method for Plant Operator.	HCI (13)	2007	DBLP DOI BibTeX RDF	thinking process, operator, instruction, plant
18	Youtao Zhang, Jun Yang 0002	Low cost instruction cache designs for tag comparison elimination.	ISLPED	2003	DBLP DOI BibTeX RDF	low-power instruction cache, tag comparison elimination
18	Dmitry Ponomarev 0001, Gurhan Kucuk, Kanad Ghose	Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources.	MICRO	2001	DBLP DOI BibTeX RDF	energy-efficient datapath, superscalar processor, power reduction, dynamic instruction scheduling
18	Gurhan Kucuk, Kanad Ghose, Dmitry Ponomarev 0001, Peter M. Kogge	Energy: efficient instruction dispatch buffer design for superscalar processors.	ISLPED	2001	DBLP DOI BibTeX RDF	bitline segmentation, low power comparator, low power instruction scheduling, low-power superscalar datapath
18	Marie Iding, Martha E. Crosby, Thomas Speitel, Thanh Trúc T. Nguyên, Tyra Shimabuku	Cooperative and Collaborative Learning in Computer-based Science Instruction.	HICSS	2001	DBLP DOI BibTeX RDF	Computer-Based Science Instruction, Collaborative Learning, Cooperative Learning
18	Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung	Flexible instruction processors.	CASES	2000	DBLP DOI BibTeX RDF	instruction processors, high-level synthesis, ASIP
18	Marian Kuras, Mariusz Grabowski, Agnieszka Zajac	Changing IS curriculum and methods of instruction.	ITiCSE	1999	DBLP DOI BibTeX RDF	IT/IS instruction, active teaching, project-based learning
18	Lea Hwang Lee, Bill Moyer, John Arends	Instruction fetch energy reduction using loop caches for embedded applications with small tight loops.	ISLPED	1999	DBLP DOI BibTeX RDF	instruction buffering, small program loops, embedded systems, low power, low cost
18	Joseph A. Fisher	Customized Instruction-Sets for Embedded Processors.	DAC	1999	DBLP DOI BibTeX RDF	custom processors, mass customization of toolchains, instruction-level parallelism, VLIW, embedded processors
18	Josep Torrellas, Chun Xia, Russell L. Daigle	Optimizing the Instruction Cache Performance of the Operating System.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	code layout optimization, instruction caches, Cache miss rates
18	P. Bosch, A. Carloganu, Daniel Etiemble	Complete x86 instruction trace generation from hardware bus collect.	EUROMICRO	1997	DBLP DOI BibTeX RDF	complete x86 instruction trace generation, hardware bus collect, architectural improvements, benchmark traces, hardware/software approach, x86 execution traces, commercial analyzer, computer architecture, microprocessors, memory hierarchies, trace driven simulation, performance data
18	Meng-chou Chang, Feipei Lai	Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	multilevel boosting, shadow register file, conjugate register file, scheduling-conflict graph, Instruction-level parallelism, speculative execution, superscalar processors
18	Chung-Chi Jim Li, Shyh-Kwei Chen, W. Kent Fuchs, Wen-mei W. Hwu	Compiler-Based Multiple Instruction Retry.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	compilers, fault-tolerant computing, rollback recovery, instruction retry
18	Neal J. Alewine, Shyh-Kwei Chen, W. Kent Fuchs, Wen-mei W. Hwu	Compiler-Assisted Multiple Instruction Rollback Recovery Using a Read Buffer.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	Fault-tolerance, compilers, error recovery, instruction retry
18	F. Kanehara, S. Satoh, T. Hamada	A flexible image retrieval using explicit visual instruction.	ICDAR	1995	DBLP DOI BibTeX RDF	flexible image retrieval, explicit visual instruction, flexible image content retrieval system, silhouette images, drawing sketch, sketch user interface, local/global shape features, information retrieval, feature extraction, query processing, human factors, image recognition, signatures, visual databases, shape similarity, image decomposition, image data, primitives
18	Michael A. Schuette, John Paul Shen	Exploiting Instruction-Level Parallelism for Integrated Control-Flow Monitoring.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	control-flow monitoring, machine parallelism, idle resources, Multiflow TRACE 14/300 processor, TRACE 14/300, available resource-driven control-flow monitoring, parallel architectures, fault tolerant computing, error detection, instruction-level parallelism, concurrent error detection
18	Mark Smotherman, Shuchi Chawla 0002, Stan Cox, Brian A. Malloy	Instruction scheduling for the Motorola 88110.	MICRO	1993	DBLP DOI BibTeX RDF	MC88110, cache alignment, instruction scheduling, superscalar processors
18	Ing-Jer Huang, Alvin M. Despain	An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors.	MICRO	1993	DBLP DOI BibTeX RDF	compiler back-end generation, hardware/software tradeoffs, inter-instruction dependency, pipeline hazard resolution, high level synthesis
18	Wen-mei W. Hwu, Pohua P. Chang	Efficient Instruction Sequencing with Inline Target Insertion.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	instruction sequencing, inline target insertion, delayed branches, squashing, branch slots, program counter, parallel programming, compiler, pipeline, interrupts, program compilers, pipeline processing, exceptions
18	Vicki H. Allan, Bogong Su, Pantung Wijaya, Jian Wang 0046	Foresighted Instruction Scheduling Under Timing Constraints.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	foresighted instruction scheduling, minimum timing information, foresighted compaction, data dependency graph arcs, data dependency information, maximum timing information, greedy compaction algorithms, scheduling, parallel algorithms, parallel programming, graph theory, timing constraints, programming theory, list scheduling, look ahead
18	David B. Whalley	Fast Instruction Cache Performance Evaluation Using Compile-Time Analysis.	SIGMETRICS	1992	DBLP DOI BibTeX RDF	instruction cache, trace analysis, cache simulation, trace generation
18	Norman P. Jouppi	The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	machine performance, first-order estimate, machine parallelism, instruction-level, machine pipelines, MultiTitan, superscalar machine, performance evaluation, parallel architectures, pipeline processing, CRAY-1
18	Michael A. Schuette, John Paul Shen	Processor Control Flow Monitoring Using Signatured Instruction Streams.	IEEE Trans. Computers	1987	DBLP DOI BibTeX RDF	transient and intermittent faults, Control flow monitoring, error detection coverage and latency, fault insertion experiments, roving monitoring, signatured instruction streams, signature analysis
18	Siamak Arya	An Optimal Instruction-Scheduling Model for a Class of Vector Processors.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	instruction loop, scheduling, Computer architecture, integer programming, vector processing
18	Alexandru Nicolau, Joseph A. Fisher	Measuring the Parallelism Available for Very Long Instruction Word Architectures.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	VLIW (very long instruction word) architectures, Memory antialiasing, parallelism, multiprocessors, microcode, trace scheduling
18	Martin De Prycker	Representing the Effect of Instruction Prefetch in a Microprocessor Performance Model.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	Best/worst case, instruction prefetch pipeline, memory speed, performance analysis, clock cycles
18	Peng Chen 0012, Krishna M. Kavi, Robert Akl	Performance Enhancement by Eliminating Redundant Function Execution.	Annual Simulation Symposium	2006	DBLP DOI BibTeX RDF	Function reuse, Basic Block Reuse, SimpleScalar, Instruction Level Parallelism, Speculative Execution, Value Prediction, Instruction Reuse
18	Mats Brorsson, Mikael Collin	Adaptive and flexible dictionary code compression for embedded applications.	CASES	2006	DBLP DOI BibTeX RDF	dictionary code compression, fetch path energy, instruction memory bandwidth, instruction profiling, processor architecture
18	Xia Brustoloni, José Carlos Brustoloni	Hardening Web browsers against man-in-the-middle and eavesdropping attacks.	WWW	2005	DBLP DOI BibTeX RDF	eavesdropping attack, just-in-time instruction, safe staging, well-in-advance instruction, certificate, HTTPS, password, Web browser, SSL, man-in-the-middle attack
18	V. Parthasarathy, S. Aram valartha Bharathi, V. Rhymend Uthariaraj	Performance Analysis of Embedded Media Applications in Newer ARM Architectures.	ICPP Workshops	2005	DBLP DOI BibTeX RDF	ARM v6, DSP Extensions, Instruction set architecture (ISA), Single Instruction Multiple Data (SIMD)
18	Sandra Katz, John M. Aronis, David Allbritton, Christine Wilson, Mary Lou Soffa	A study to identify predictors of achievement in an introductory computer science course.	CPR	2003	DBLP DOI BibTeX RDF	computer science instruction, gender and computer science, programming instruction
18	Michael L. Chu, Kevin Fan, Scott A. Mahlke	Region-based hierarchical operation partitioning for multicluster processors.	PLDI	2003	DBLP DOI BibTeX RDF	multicluster processor, operation partitioning, clustering, instruction-level parallelism, instruction scheduling, region-based compilation
18	Madhavi Gopal Valluri, Lizy Kurian John, Heather Hanson	Exploiting compiler-generated schedules for energy savings in high-performance processors.	ISLPED	2003	DBLP DOI BibTeX RDF	dynamic issue processors, very long instruction word architectures, instruction-level parallelism, low energy
18	C. V. Ramakrishnan, S. Ramesh Kumar	Comparative Performance of Frontal (Direct) and PCG (Iterative) Solver Based Parallel Computations of Finite Element Analysis.	IPDPS	2002	DBLP DOI BibTeX RDF	Finite Element Analysis (FEA), Symmetric Multi-processor (SMP), Preconditioned Conjugate Gradient (PCG), degrees of freedom (dof), maximum bandwidth (mbwd), maximum frontwidth (mfwd), Number of processors (Numprocs), iterations (iter), Message Passing Interface (MPI), Single Instruction Multiple Data (SIMD), Multiple Instruction Multiple Data (MIMD)
18	Thomas M. Conte, Sumedh W. Sathaye	Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	instruction-set encoding, list encoding, VLIW, Microarchitecture, processor architecture, instruction cache
18	Jiannong Cao 0001, Y. Liu, Li Xie 0001, Kang Zhang 0001	Portable Runtime Support for Graph-oriented Parallel and Distributed Programming.	ISPAN	2000	DBLP DOI BibTeX RDF	dynamic speculation of data dependence, instruction reissue, register update unit, Instruction level parallelism, out-of-order execution
18	Carlos Molina, Antonio González 0001, Jordi Tubella	Dynamic removal of redundant computations.	International Conference on Supercomputing	1999	DBLP DOI BibTeX RDF	data-value reuse, instruction-level reuse, instruction-level parallelism
18	Sanjeev Banerjia, Sumedh W. Sathaye, Kishore N. Menezes, Thomas M. Conte	MPS: Miss-Path Scheduling for Multiple-Issue Processors.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	Multiple instruction issue, miss path scheduling, schedule cache, instruction level parallelism
18	Chao-ying Fu, Matthew D. Jennings, Sergei Y. Larin, Thomas M. Conte	Value Speculation Scheduling for High Performance Processors.	ASPLOS	1998	DBLP DOI BibTeX RDF	VLIW instruction schedulings, instruction level parallelism, value prediction, value speculation
18	Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao	A Framework for Resource-Constrained Rate-Optimal Software Pipelining.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	superscalar and VLIW architectures, Instruction-level parallelism, integer linear programming, software pipelining, instruction scheduling
18	Bülent Abali, Craig B. Stunkel	Time synchronization on SP1 and SP2 parallel systems.	IPPS	1995	DBLP DOI BibTeX RDF	SP2 parallel system, SP1 parallel system, experimental time utility, operating system clocks, node clocks, synchronous feature, parallel program performance measurement, parallel program tuning, parallel program tracing, parallel program debugging, parallel processes, interconnection network, multiprocessor interconnection networks, multiprocessor interconnection networks, parallel machines, parallel machines, synchronisation, synchronisation, processor scheduling, processor scheduling, software performance evaluation, software performance evaluation, program debugging, program debugging, clocks, clocks, operating systems (computers), operating systems (computers), time synchronization, gang scheduling, reduced instruction set computing, reduced instruction set computing
18	Sheila A. Brandt, Robert O. Briggs	Exploring the use of EMS in the classroom: two field studies.	HICSS (4)	1995	DBLP DOI BibTeX RDF	reduced evaluation apprehension, classroom settings, student participation, human factors, teleconferencing, cooperative learning, learning theory, classroom, computer aided instruction, computer aided instruction, social aspects of automation, cooperative problem-solving, electronic meeting systems
18	Dan I. Moldovan, Wing Lee, Changhwa Lin	Parallel Knowledge Processing in SNAP.	IEEE Trans. Knowl. Data Eng.	1993	DBLP DOI BibTeX RDF	semantic network array processor, highly parallel architecture, marker propagation architecture, reasoning mechanisms, simulator, classification, knowledge representation, parallel architectures, recognition, inheritance, reasoning, digital simulation, semantic networks, instruction set, instruction sets, Connection Machine, markers
18	Pradeep K. Dubey, Michael J. Flynn	Branch Strategies: Modeling and Optimization.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	branch-delay penalty, instruction bandwidth, i-traffic, wasted instruction fetches, active branch prediction, loop buffers, parallel programming, compilers, program compilers, pipeline processing, pipelined processors, branch-target-buffer
18	Augustus K. Uht	A Theory of Reduced and Minimal Procedural Dependencies.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	reduced procedural dependencies, minimal procedural dependencies, reduced set, reduced data dependencies, minimal semantic dependencies, concurrency control, codes, instruction sets, reduced instruction set computing
18	Veljko M. Milutinovic, David A. Fura, Walter A. Helbig	Pipeline Design Tradeoffs in a 32-bit Gallium Arsenide Microprocessor.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	instruction pipeline design, single-chip GaAs microprocessor, application-related parameters, pipelined memory pipeline, III-V semiconductors, performance evaluation, microprocessor chips, instruction sets, 32 bit, GaAs, gallium arsenide
18	Daniel C. McCrackin, Barna Szabados	Using Horizontal Prefetching to Circumvent the Jump Problem.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	horizontal prefetching, jump problem, independent instruction streams, memory utilization, prototype machine, performance, design, computer architecture, interprocessor communication, instruction sets, context switching, process synchronization, processor utilization, processor performance
18	A. P. Wim Böhm, John R. Gurd	Iterative Instructions in the Manchester Dataflow Computer.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	Manchester Dataflow Computer, iterative instructions, program execution times, function unit array, hardware speedup curves, fine-grain instructions, parallel programming, parallel architectures, iterative methods, parallel machines, tokens, instruction sets, instruction sets, hardware configuration
18	John L. Hennessy	VLSI Processor Architecture.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	instruction issue, processor implementation, VLSI, pipelining, microprocessors, processor architecture, Computer organization, memory mapping, instruction set design
18	Edsger W. Dijkstra	Letters to the editor: go to statement considered harmful.	Commun. ACM	1968	DBLP DOI BibTeX RDF	alternative clause, conditional clause, go to statement, jump instruction, program intelligibility, program sequencing, repetitive clause, branch instruction
18	John R. Rice, Edsger W. Dijkstra	Letters to the editor: The go to statement reconsidered.	Commun. ACM	1968	DBLP DOI BibTeX RDF	algorithm progress, go to, jump instruction, program intelligibility, program sequencing, algorithm analysis, branch instruction
17	Hui Wang, Rama Sangireddy, Sandeep Baldawa	Optimizing Instruction Scheduling through Combined In-Order and O-O-O Execution in SMT Processors.	IEEE Trans. Parallel Distributed Syst.	2009	DBLP DOI BibTeX RDF
17	Min Li 0001, David Novo, Bruno Bougard, Trevor E. Carlson, Liesbet Van der Perre, Francky Catthoor	Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures.	IEEE Trans. Signal Process.	2009	DBLP DOI BibTeX RDF
17	Wallace H. Wulfeck	Adapting Instruction.	HCI (16)	2009	DBLP DOI BibTeX RDF
17	Yusuke Hayashi, Seiji Isotani, Jacqueline Bourdeau, Riichiro Mizoguchi	Toward a Learning/Instruction Process Model for Facilitating the Instructional Design Cycle.	WCCE	2009	DBLP DOI BibTeX RDF	collaborative learning, Ontological engineering, instructional design
17	Farhad Mehdipour, Hamid Noori, Bahman Javadi, Hiroaki Honda, Koji Inoue, Kazuaki J. Murakami	A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor.	ASP-DAC	2009	DBLP DOI BibTeX RDF
17	Mengping Tsuei	The G-Math Peer-Tutoring System for Supporting Effectively Remedial Instruction for Elementary Students.	ICALT	2009	DBLP DOI BibTeX RDF
17	Shi-Jer Lou, Yi-Zhen Zhu, Kuo-Hung Tseng, Yuan-Chang Guo, Ru-Chu Shih	A Study of Computer-Assisted Instruction on Music Appreciation: An Example of Chinese Musical Instruments.	ICALT	2009	DBLP DOI BibTeX RDF
17	Seung Eun Lee, Chris Wilkerson, Ming Zhang, Rajendra S. Yavatkar, Shih-Lien Lu, Nader Bagherzadeh	Low power adaptive pipeline based on instruction isolation.	ISQED	2009	DBLP DOI BibTeX RDF
17	Roger Mailler, Daniel Bryce, Jiaying Shen, Ciaran O'Reilly	MABLE: a framework for learning from natural instruction.	AAMAS (1)	2009	DBLP BibTeX RDF	MABLE, learning, architecture
17	Junzo Kamahara, Takashi Nagamatsu, Yuki Fukuhara, Yohei Kaieda, Yutaka Ishii	Method for Identifying Task Hardships by Analyzing Operational Logs of Instruction Videos.	SAMT	2009	DBLP DOI BibTeX RDF	User Behavior, Multimedia Authoring
17	Sami Khawam, Ioannis Nousias, Mark Milward, Ying Yi, Mark Muir, Tughrul Arslan	The Reconfigurable Instruction Cell Array.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
17	Sebastian de la Chica, Faisal Ahmad, Tamara Sumner, James H. Martin, Kirsten R. Butcher	Computational foundations for personalizing instruction with digital libraries.	Int. J. Digit. Libr.	2008	DBLP DOI BibTeX RDF	Personalization tools, Natural language processing, Educational digital library
17	Tarek M. Taha, D. Scott Wills	An Instruction Throughput Model of Superscalar Processors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Modeling techniques, Pipeline processors, Modeling of computer architecture
17	Tor M. Aamodt, Paul Chow	Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	fractional multiplication, Compilation, digital signal processing, scaling, fixed-point, signal-to-noise ratio
17	Clément Ballabriga, Hugues Cassé	Improving the First-Miss Computation in Set-Associative Instruction Caches.	ECRTS	2008	DBLP DOI BibTeX RDF
17	Lars Bauer, Muhammad Shafique 0001, Stephanie Kreutz, Jörg Henkel	Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set.	DATE	2008	DBLP DOI BibTeX RDF
17	Björn Franke	Fast cycle-approximate instruction set simulation.	SCOPES	2008	DBLP DOI BibTeX RDF
17	Joseph E. Hollingsworth	Teaching query writing: an informed instruction approach.	ITiCSE	2008	DBLP DOI BibTeX RDF	database, course pedagogy
17	David B. Whalley, Gary S. Tyson	Enhancing the effectiveness of utilizing an instruction register file.	IPDPS	2008	DBLP DOI BibTeX RDF
17	Xianzhi Tian	Influences of CAI English Teaching Pattern on the Autonomous Learning -Research on Divided Class Instruction of Independent College.	WKDD	2008	DBLP DOI BibTeX RDF
17	Carlo Galuzzi, Koen Bertels	A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures.	ARC	2008	DBLP DOI BibTeX RDF
17	Luis C. Aparicio, Juan Segarra, Clemente Rodríguez, J. L. Villarroel, Víctor Viñals	Avoiding the WCET Overestimation on LRU Instruction Cache.	RTCSA	2008	DBLP DOI BibTeX RDF