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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 20075 occurrences of 5412 keywords
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Results
Found 25938 publication records. Showing 25938 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Daniel C. McCrackin, Barna Szabados |
Using Horizontal Prefetching to Circumvent the Jump Problem. |
IEEE Trans. Computers |
1991 |
DBLP DOI BibTeX RDF |
horizontal prefetching, jump problem, independent instruction streams, memory utilization, prototype machine, performance, design, computer architecture, interprocessor communication, instruction sets, context switching, process synchronization, processor utilization, processor performance |
16 | Paul D. Stachour, Bhavani Thuraisingham |
Design of LDV: A Multilevel Secure Relational Database Management System. |
IEEE Trans. Knowl. Data Eng. |
1990 |
DBLP DOI BibTeX RDF |
classification level, polyinstantiation, type enforcement, multilevel secure relational database management system, secure database system, LDV, Lock Data Views, LOgical Coprocessing Kernel, assured pipelines, query processor, update processor, relational databases, operating system, aggregation, security policy, inference, security of data, LOCK, metadata management, Trusted Computing Base |
16 | Ashok K. Agrawala, Edward G. Coffman Jr., M. R. Garey, Satish K. Tripathi |
A Stochastic Optimization Algorithm Minimizing Expected Flow Times on Uniform Processors. |
IEEE Trans. Computers |
1984 |
DBLP DOI BibTeX RDF |
uniform processor systems, Consider a set of processors P1, ..., Pm differing only in speed and a set of jobs with exponentially distributed execution times, The rate parameter for the ith processor is given by ?i, 1 =i = m, where we assume the processors are ordered so that ?1 = ?2 = ... = ?m. The problem is to sequence the jobs nonpreemptively so as to minimize expected total flow time (sum of finishing times). We defin, Mean flow time minimization, stochastic optimization, stochastic scheduling, routing problems |
16 | Kuang-Hua Huang, Jacob A. Abraham |
Algorithm-Based Fault Tolerance for Matrix Operations. |
IEEE Trans. Computers |
1984 |
DBLP DOI BibTeX RDF |
checksum matrix, error detection, systolic arrays, error correction, processor arrays, Algorithm-based fault tolerance, transient errors, multiple processor systems, matrix operations |
16 | Dennis Parkinson, Heather M. Liddell |
The Measurement of Performance on a Highly Parallel System. |
IEEE Trans. Computers |
1983 |
DBLP DOI BibTeX RDF |
distributed array processor, parallel algorithms, parallel computation, performance measurement, multiple processor systems, Associative processors, SIMD computers |
16 | David C. van Voorhis, Thomas H. Morrin |
Memory Systems for Image Processing. |
IEEE Trans. Computers |
1978 |
DBLP DOI BibTeX RDF |
array storage, image processing, memory system, Array processor, parallel processor, parallel memory |
15 | Huandong Wang, Xiang Gao, Yunji Chen, Dan Tang, Weiwu Hu |
A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only). |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
loongson, multi-fpga, fpga, evaluation, verification, emulation |
15 | Flavius Gruian, Mark Westmijze |
Investigating hardware micro-instruction folding in a Java embedded processor. |
JTRES |
2010 |
DBLP DOI BibTeX RDF |
BlueJEP, bytecode folding, embedded systems, Java processors, Bluespec |
15 | Omid Azizi, Aqeel Mahesri, Benjamin C. Lee, Sanjay J. Patel, Mark Horowitz |
Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis. |
ISCA |
2010 |
DBLP DOI BibTeX RDF |
co-optimization, design trade-offs, optimization, energy efficiency, design space exploration, microarchitecture |
15 | Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar 0002, John Sartori |
Recovery-driven design: a power minimization methodology for error-tolerant processor modules. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
recovery-driven design, power minimization |
15 | Sascha Uhrig |
Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC. |
SAMOS |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Dina Thomas, Rajesh Bordawekar, Charu C. Aggarwal, Philip S. Yu |
On Efficient Query Processing of Stream Counts on the Cell Processor. |
ICDE |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003 |
Intel® atomTM processor core made FPGA-synthesizable. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
intel atom, synthesizable core, fpga, emulator |
15 | Akiyoshi Wakatani |
Implementation of Recurrence Calculation on a Heterogeneous Multicore Processor. |
ACIS-ICIS |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Balaram Sinharoy |
POWER7 multi-core processor design. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Lide Duan, Bin Li 0008, Lu Peng 0001 |
Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics. |
HPCA |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Dimitris Syrivelis, Spyros Lalis |
Extracting Coarse-Grained Pipelined Parallelism Out of Sequential Applications for Parallel Processor Arrays. |
ARCS |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Darshan Desai, Gerolf Hoflehner, Arun Kejariwal, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum, Cameron McNairy |
Performance Characterization of Itanium® 2-Based Montecito Processor. |
SPEC Benchmark Workshop |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Kiyeon Lee, Shayne Evans, Sangyeun Cho |
Accurately approximating superscalar processor performance from traces. |
ISPASS |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Ge Gan, Xu Wang, Joseph B. Manzano, Guang R. Gao |
Tile Percolation: An OpenMP Tile Aware Parallelization Technique for the Cyclops-64 Multicore Processor. |
Euro-Par |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Yoshihiro Ichinomiya, Shiro Tanoue, Tomoyuki Ishida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi |
Memory Sharing Approach for TMR Softcore Processor. |
ARC |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Daniel Ménard, Emmanuel Casseau, Shafqat Khan, Olivier Sentieys, Stéphane Chevobbe, Stéphane Guyetant, Raphaël David |
Reconfigurable Operator Based Multimedia Embedded Processor. |
ARC |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Martin Sandrieser, Sabri Pllana, Siegfried Benkner |
Evaluation of the SUN UltraSparc T2+ Processor for Computational Science. |
ICCS (1) |
2009 |
DBLP DOI BibTeX RDF |
Sun UltraSparc T2+, Niagara2, Evaluation, Computational Science |
15 | Praveen Kumar, Kannappan Palaniappan, Ankush Mittal, Guna Seetharaman |
Parallel Blob Extraction Using the Multi-core Cell Processor. |
ACIVS |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Qi Wu 0006, Jian-Qiang Lu, Kenneth Rose, Tong Zhang 0002 |
Efficient implementation of decoupling capacitors in 3D processor-dram integrated computing systems. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
three-dimentional integration, dram, decoupling capacitor |
15 | Sang-Kyo Han, SeongHoon Woo, Mun-Ho Jeong, Bum-Jae You |
Improved-Quality Real-Time Stereo Vision Processor. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer |
IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor. |
HiPEAC |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Tomas Tuma, Sean Rooney, Paul Hurley |
On the Applicability of Compressive Sampling in Fine Grained Processor Performance Monitoring. |
ICECCS |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Sergio Ilarri, Ouri Wolfson, Eduardo Mena, Arantza Illarramendi, A. Prasad Sistla |
A query processor for prediction-based monitoring of data streams. |
EDBT |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Hong Lu, A. Forin |
Automatic Processor Customization for Zero-Overhead Online Software Verification. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Jakub Kurzak, Alfredo Buttari, Jack J. Dongarra |
Solving Systems of Linear Equations on the CELL Processor Using Cholesky Factorization. |
IEEE Trans. Parallel Distributed Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Shuenn-Shyang Wang, Chien-Sung Li |
An Area-Efficient Design of Variable-Length Fast Fourier Transform Processor. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
variable length FFT, substructure sharing, Fast Fourier Transform, OFDM |
15 | Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche |
A low-cost concurrent error detection technique for processor control logic. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Jie Zhou 0007, Yong Dou, Yuanwu Lei, Jinbo Xu, Yazhuo Dong |
Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. |
HPCC |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Young-Su Kwon, Bontae Koo, Nak-Woong Eum |
Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
15 | José Luis Núñez-Yáñez, Eddie Hung, Vassilios A. Chouliaras |
A configurable and programmable motion estimation processor for the H.264 video codec. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Yijun Liu, Banghai Wang, Guobo Xie, Pinghua Chen, Zhenkun Li |
Designing a Multi-Processor Education Board for High-Performance Embedded Processing. |
ICYCS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Jianjun Guo, Kui Dai, Ming-che Lai, Zhiying Wang 0003 |
The P2P Communication Model for a Local Memory based Multi-core Processor. |
ICYCS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Yonggang Che |
Evaluating the Data Access Efficiency of Imagine Stream Processor with Scientific Applications. |
ICYCS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Wanessa Pereira Dias, Emilia Colonese |
Performance Analysis of Cache and Scratchpad Memory in an Embedded High Performance Processor. |
ITNG |
2008 |
DBLP DOI BibTeX RDF |
performance, cache, memory |
15 | Farshad Khunjush, Nikitas J. Dimopoulos |
Extended characterization of DMA transfers on the Cell BE processor. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Jie Zhou 0007, Yong Dou, Yuanwu Lei, Yazhuo Dong |
Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. |
ARC |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Duoduo Liao, Simon Y. Berkovich |
A conceptual system for parallel solid voxelization using multi-processor pipelining. |
VRCAI |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Hong Wang 0006, Hiroyuki Takizawa, Hiroaki Kobayashi |
A Performance Study of Secure Data Mining on the Cell Processor. |
CCGRID |
2008 |
DBLP DOI BibTeX RDF |
Security, Performance Evaluation, Data Clustering, Volunteer Computing |
15 | Sibin Mohan, Frank Mueller 0001 |
Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions. |
IEEE Real-Time and Embedded Technology and Applications Symposium |
2008 |
DBLP DOI BibTeX RDF |
hybrid timing anlalysis, hardware/software interactions, real-time systems, embedded systems, computer architecture, timing analysis, worst-case execution time, out-of-order execution |
15 | Nobuaki Kobayashi, Tadayoshi Enomoto |
A low power 90-nm CMOS motion estimation processor implementing dynamic voltage and frequency scaling (DVFS) and fast motion estimation algorithm. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Gang Chen, Guoqiang Bai 0001, Hongyi Chen |
A dual-field elliptic curve cryptographic processor based on a systolic arithmetic unit. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto |
A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mauricio Alvarez 0001, Alex Ramírez |
Analysis of video filtering on the cell processor. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Minhyeok Shin, Hanho Lee |
A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee |
A hybrid self-testing methodology of processor cores. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Syed Waqar Nabi, Cade C. Wells, Wim Vanderbauwhede |
A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Kai Zheng 0005, Yongxin Zhu 0001, Jun Xu |
Evaluation of Partitioning Methods for Stream Applications on a Heterogeneous Multi-core Processor Simulator. |
EUC (2) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Hung-Chuan Lai, Shi-Jinn Horng, Yung-Yuan Chen |
An Online Control Flow Check for VLIW Processor. |
PRDC |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Vamsi Boppana, Rahoul Varma, S. Balajee |
Implementing the Best Processor Cores. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Hiroyuki Takizawa, Katsuto Sato, Hiroaki Kobayashi |
SPRAT: Runtime processor selection for energy-aware computing. |
CLUSTER |
2008 |
DBLP DOI BibTeX RDF |
|
15 | David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, Bruce Edwards, Carl Ramey, Matthew Mattina, Chyi-Chang Miao, John F. Brown III, Anant Agarwal |
On-Chip Interconnection Architecture of the Tile Processor. |
IEEE Micro |
2007 |
DBLP DOI BibTeX RDF |
MIMD processors, parallel architectures, mesh networks, multicore architectures, on-chip interconnection networks |
15 | Andreas Brandt 0001, Manfred Brandt |
On the stability of the multi-queue multi-server processor sharing with limited service. |
Queueing Syst. Theory Appl. |
2007 |
DBLP DOI BibTeX RDF |
Mathematics Subject Classification (2000) 60K25, 60G10, 60G17, 60G55, 68M20 |
15 | Tanya René Beelders, Pieter J. Blignaut, Theo McDonald, Engela Dednam |
The Impact of Different Icon Sets on the Usability of a Word Processor. |
HCI (10) |
2007 |
DBLP DOI BibTeX RDF |
Usability, interface, icons |
15 | Andrew Lines |
The Vortex: A Superscalar Asynchronous Processor. |
ASYNC |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Yong Li 0006, Zhiying Wang 0003, Kui Dai |
A Low-Power Application Specific Instruction Set Processor Using Asynchronous Function Units. |
CIT |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement |
Modeling of Interconnection Networks in Massively Parallel Processor Architectures. |
ARCS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Xiaojun Yang, Dongdong Wu, Ninghui Sun |
Design of NIC Based on I/O Processor for Cluster Interconnect Network. |
IEEE NAS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Robert Ronan, Colm O'hEigeartaigh, Colin C. Murphy, Tim Kerins, Paulo S. L. M. Barreto |
A Reconfigurable Processor for the Cryptographic nT Pairing in Characteristic 3. |
ITNG |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Daniele Paolo Scarpazza, Oreste Villa, Fabrizio Petrini |
Peak-Performance DFA-based String Matching on the Cell Processor. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Guan Yu, Gauthier Lafruit, Peter Schelkens |
Platform-scalable Task Partition and Multilevel Buffering in Multi-processor Plessey Corner Detector. |
ACSD |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Shuifa Sun, Bang Jun Lei, Sheng Zheng, Sam Kwong, Xuejun Zhou |
Design an Aperiodic Stochastic Resonance Signal Processor for Digital Watermarking. |
IWDW |
2007 |
DBLP DOI BibTeX RDF |
signal processing, digital watermarking, stochastic resonance |
15 | Partha Tirumalai, Yonghong Song, Spiros Kalogeropulos |
Performance Evaluation of Evolutionary Multi-core and Aggressively Multi-threaded Processor Architectures. |
Asia-Pacific Computer Systems Architecture Conference |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Yu Deng 0001, Xuejun Yang, Xiaobo Yan, Kun Zeng |
Laplace Transformation on the FT64 Stream Processor. |
Asia-Pacific Computer Systems Architecture Conference |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Yong Li 0006, Zhiying Wang 0003, Xue-mi Zhao, Jian Ruan, Kui Dai |
Design of a Low-Power Embedded Processor Architecture Using Asynchronous Function Units. |
Asia-Pacific Computer Systems Architecture Conference |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Yong Sun, Yu (David) Shi, Fang Chen 0001, Vera Yuk Ying Chung |
An Efficient Multimodal Language Processor for Parallel Input Strings in Multimodal Input Fusion. |
ICSC |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang |
A Low Energy FFT/IFFT Processor for Hearing Aids. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Kota Yamaguchi, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa |
Design of a Massively Parallel Vision Processor based on Multi-SIMD Architecture. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Simon Haene, Andreas Burg, Peter Luethi, Norbert Felber, Wolfgang Fichtner |
FFT Processor for OFDM Channel Estimation. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Lars Bauer, Muhammad Shafique 0001, Dirk Teufel, Jörg Henkel |
A Self-Adaptive Extensible Embedded Processor. |
SASO |
2007 |
DBLP DOI BibTeX RDF |
|
15 | David Robert Wallace Barr, Piotr Dudek, Jonathan M. Chambers, Kevin N. Gurney |
Implementation of multi-layer leaky integrator networks on a cellular processor array. |
IJCNN |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Yuechao Niu, Majid Baghaei Nejad, Hannu Tenhunen, Li-Rong Zheng 0001 |
Design of a Digital Baseband Processor for UWB Transceiver on RFID Tag. |
AINA Workshops (2) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares |
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. |
HiPEAC |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Niranjan Soundararajan, Angshuman Parashar, Anand Sivasubramaniam |
Mechanisms for bounding vulnerabilities of processor structures. |
ISCA |
2007 |
DBLP DOI BibTeX RDF |
redundant threading, microarchitecture, transient faults |
15 | Gustavo A. Ruiz, Juan A. Michell, Angel M. Burón |
High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip. |
J. VLSI Signal Process. |
2006 |
DBLP DOI BibTeX RDF |
inverse discrete cosine transform (IDCT), row column decomposition, parallel pipelined architectures, very large scale integration (VLSI), image compression, discrete cosine transform (DCT) |
15 | Carsten Albrecht, Andreas C. Döring, Frank Penczek, Torben Schneider, Hannes Schulz |
Impact of Coprocessors on a Multithreaded Processor Design Using Prioritized Threads. |
PDP |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Eryk Laskowski, Marek Tudruj |
Assessment of Dynamic Look-Ahead Inter-Processor Connection Reconfiguration for Different Control Paradigms. |
ISPDC |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Frederick Reiss 0001, Joseph M. Hellerstein |
Declarative Network Monitoring with an Underprovisioned Query Processor. |
ICDE |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Martin Schoeberl |
A time predictable Java processor. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
15 | José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López |
Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
15 | P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil |
Construction and use of linear regression models for processor performance analysis. |
HPCA |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Miquel Pericàs, Adrián Cristal, Rubén González 0001, Daniel A. Jiménez, Mateo Valero |
A decoupled KILO-instruction processor. |
HPCA |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Yongjun Wang, Xiaoming Zhang |
A Novel Modeling Method of Network Processor Architecture Based on SystemC. |
CIT |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Ahmed Sherif Zekri, Stanislav G. Sedukhin |
Matrix Transpose on 2D Torus Array Processor. |
CIT |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Satoshi Imai, Atsuki Inoue, Motoaki Matsumura, Kenichi Kawasaki, Atsuhiro Suga |
Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noise. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Morteza Saheb Zamani |
A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Gerrit Saylor, Badriddine Khessib |
Large scale Itanium® 2 processor OLTP workload characterization and optimization. |
DaMoN |
2006 |
DBLP DOI BibTeX RDF |
cache coherency, data partitioning, performance characterization, profile guided optimization, OLTP, software optimization, Itanium, ccNUMA |
15 | Brian F. Veale, John K. Antonio, Monte P. Tull, Sean A. Jones |
Selection of instruction set extensions for an FPGA embedded processor core. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Nick A. Mould, Brian F. Veale, Monte P. Tull, John K. Antonio |
Dynamic configuration steering for a reconfigurable superscalar processor. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis 0001 |
An automated development framework for a RISC processor with reconfigurable instruction set extensions. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Eryk Laskowski, Marek Tudruj |
Efficient Parallel Embedded Computing through Look-Ahead Configured Dynamic Inter-Processor Connections. |
PARELEC |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Jianjun Guo, Kui Dai, Zhiying Wang 0003 |
A Heterogeneous Multi-core Processor Architecture for High Performance Computing. |
Asia-Pacific Computer Systems Architecture Conference |
2006 |
DBLP DOI BibTeX RDF |
TTA, SoC, heterogeneous, multi-core |
15 | Jing Du 0002, Xuejun Yang, Guibin Wang, Fujiang Ao |
Scientific Computing Applications on the Imagine Stream Processor. |
Asia-Pacific Computer Systems Architecture Conference |
2006 |
DBLP DOI BibTeX RDF |
scientific computing application, three level parallelism, multinest, stream, Imagine |
15 | Saad Bani-Mohammad, Mohamed Ould-Khaoua, Ismail Ababneh, Lewis M. Mackenzie |
Non-contiguous Processor Allocation Strategy for 2D Mesh Connected Multicomputers based on Sub-meshes Available for Allocation. |
ICPADS (2) |
2006 |
DBLP DOI BibTeX RDF |
|
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