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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 18662 occurrences of 5027 keywords
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Results
Found 21661 publication records. Showing 21661 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
14 | Hoseok Chang, Wonyong Sung |
Access-Pattern-Aware On-Chip Memory Allocation for SIMD Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1), pp. 158-163, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Ron Gabor, Avi Mendelson, Shlomo Weiss |
Service level agreement for multithreaded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 6(2), pp. 6:1-6:33, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
performance, fairness, throughput, power, Service level agreement |
14 | Alejandro Linares-Barranco, Rafael Paz, Francisco Gomez-Rodriguez, Angel Jiménez-Fernandez, Manuel Rivas, Gabriel Jiménez, Antón Civit |
FPGA Implementations Comparison of Neuro-cortical Inspired Convolution Processors for Spiking Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN (1) ![In: Bio-Inspired Systems: Computational and Ambient Intelligence, 10th International Work-Conference on Artificial Neural Networks, IWANN 2009, Salamanca, Spain, June 10-12, 2009. Proceedings, Part I, pp. 97-105, 2009, Springer, 978-3-642-02477-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Klaus Jansen |
An EPTAS for Scheduling Jobs on Uniform Processors: Using an MILP Relaxation with a Constant Number of Integral Variables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP (1) ![In: Automata, Languages and Programming, 36th International Colloquium, ICALP 2009, Rhodes, Greece, July 5-12, 2009, Proceedings, Part I, pp. 562-573, 2009, Springer, 978-3-642-02926-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Samir Ammenouche, Sid Ahmed Ali Touati, William Jalby |
On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC ![In: 11th IEEE International Conference on High Performance Computing and Communications, HPCC 2009, 25-27 June 2009, Seoul, Korea, pp. 196-205, 2009, IEEE, 978-0-7695-3738-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Anastasios Gounaris |
A Vision for Next Generation Query Processors and an Associated Research Agenda. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Globe ![In: Data Management in Grid and Peer-to-Peer Systems, Second International Conference, Globe 2009, Linz, Austria, September 1-2, 2009, Proceedings, pp. 1-11, 2009, Springer, 978-3-642-03714-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Guoping Long, Dongrui Fan, Junchao Zhang |
Characterizing and Understanding the Bandwidth Behavior of Workloads on Multi-core Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2009 Parallel Processing, 15th International Euro-Par Conference, Delft, The Netherlands, August 25-28, 2009. Proceedings, pp. 110-121, 2009, Springer, 978-3-642-03868-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
phase model, memory bandwidth, multi-core architecture |
14 | Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López 0001 |
Paired ROBs: A Cost-Effective Reorder Buffer Sharing Strategy for SMT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2009 Parallel Processing, 15th International Euro-Par Conference, Delft, The Netherlands, August 25-28, 2009. Proceedings, pp. 309-320, 2009, Springer, 978-3-642-03868-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Paolo Bottoni, Anna Labella, Florin Manea, Victor Mitrana, José M. Sempere |
Filter Position in Networks of Evolutionary Processors Does Not Matter: A Direct Proof. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DNA ![In: DNA Computing and Molecular Programming, 15th International Conference, DNA 15, Fayetteville, AR, USA, June 8-11, 2009, Revised Selected Papers, pp. 1-11, 2009, Springer, 978-3-642-10603-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Nan Wu 0003, Mei Wen, Wei Wu, Ju Ren 0002, Huayou Su, Changqing Xun, Chunyuan Zhang |
Streaming HD H.264 encoder on programmable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Multimedia ![In: Proceedings of the 17th International Conference on Multimedia 2009, Vancouver, British Columbia, Canada, October 19-24, 2009, pp. 371-380, 2009, ACM, 978-1-60558-608-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
1080P HD, H.264 encoder, real-time, stream, programmable |
14 | Peter D. Ungsunan, Chuang Lin 0002, Yang Wang 0018, Yi Gai |
Network processing performability evaluation on heterogeneous reliability multicore processors using SRN model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-6, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Ya-Shuai Lü, Li Shen 0007, Zhiying Wang 0003, Nong Xiao |
Dynamically utilizing computation accelerators for extensible processors in a software approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 51-60, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
computation accelerator, ASIP, dynamic binary translation |
14 | Yinglong Xia, Xiaojun Feng, Viktor K. Prasanna |
Parallel Evidence Propagation on Multicore Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PaCT ![In: Parallel Computing Technologies, 10th International Conference, PaCT 2009, Novosibirsk, Russia, August 31-September 4, 2009. Proceedings, pp. 377-391, 2009, Springer, 978-3-642-03274-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Exact inference, Scheduling, Multicore, Junction tree |
14 | Paolo Bottoni, Anna Labella, Florin Manea, Victor Mitrana, José M. Sempere |
Networks of Evolutionary Picture Processors with Filtered Connections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UC ![In: Unconventional Computation, 8th International Conference, UC 2009, Ponta Delgada, Azores, Portugal, September 7-11, 2009. Proceedings, pp. 70-84, 2009, Springer, 978-3-642-03744-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Michael Kadin, Sherief Reda, Augustus K. Uht |
Central vs. distributed dynamic thermal management for multi-core processors: which one is better? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 137-140, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dfvs, timing, thermal management |
14 | Bart Coppens 0001, Ingrid Verbauwhede, Koen De Bosschere, Bjorn De Sutter |
Practical Mitigations for Timing-Based Side-Channel Attacks on Modern x86 Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SP ![In: 30th IEEE Symposium on Security and Privacy (SP 2009), 17-20 May 2009, Oakland, California, USA, pp. 45-60, 2009, IEEE Computer Society, 978-0-7695-3633-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Sourav Roy |
H-NMRU: A Low Area, High Performance Cache Replacement Policy for Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 553-558, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Rajat Raina, Anand Madhavan, Andrew Y. Ng |
Large-scale deep unsupervised learning using graphics processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICML ![In: Proceedings of the 26th Annual International Conference on Machine Learning, ICML 2009, Montreal, Quebec, Canada, June 14-18, 2009, pp. 873-880, 2009, ACM, 978-1-60558-516-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Talal Bonny, Jörg Henkel |
LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 903-906, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
embedded systems, code compression, Huffman coding |
14 | Jungseob Lee, Nam Sung Kim |
Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 47-50, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
multicore processor, DVFS, power gating |
14 | Jian Chen 0030, Lizy Kurian John |
Efficient program scheduling for heterogeneous multi-core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 927-930, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
program scheduling, heterogeneous multi-core, energy-delay product |
14 | Shafqat Khan, Emmanuel Casseau, Daniel Ménard |
Reconfigurable SWP Operator for Multimedia Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2009, July 7-9, 2009, Boston, MA, USA, pp. 199-202, 2009, IEEE Computer Society, 978-0-7695-3732-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, Heinrich Meyr, Gerd Ascheid |
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(10), pp. 1281-1294, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Paolo Ienne, Peter Petrov |
Guest Editorial Special Section on Application Specific Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(10), pp. 1257-1258, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Lukas Kencl, Jean-Yves Le Boudec |
Adaptive load sharing for network processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 16(2), pp. 293-306, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
load balancing, computer networks, feedback control, load sharing, router architecture, packet processing |
14 | Dongsoo Kang, Chen Liu 0001, Jean-Luc Gaudiot |
The Impact of Speculative Execution on SMT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 36(4), pp. 361-385, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Speculation control, Simultaneous multithreading, Thread scheduling, Confidence estimator |
14 | Euiseong Seo, Jinkyu Jeong, Seon-Yeong Park, Joonwon Lee |
Energy Efficient Scheduling of Real-Time Tasks on Multicore Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 19(11), pp. 1540-1552, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Mahdi Fazeli, Reza Farivar 0003, Seyed Ghassem Miremadi |
Error Detection Enhancement in PowerPC Architecture-based Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 21-33, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Physical fault injection, Power supply disturbances, Concurrent error detection, Control flow checking |
14 | Rajeev Kumar 0004, Dipankar Das 0002 |
Code compression for performance enhancement of variable-length embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 7(3), pp. 35:1-35:36, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
bus switching, code decompression, instruction memory, variable-length ISAs, embedded systems, Code compression, RISC processor |
14 | Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 7(4), pp. 40:1-40:31, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
coarse-grained FPGA, VLIW, ASIP |
14 | Qin Wang 0007, Joseph F. JáJá |
Interactive High-Resolution Isosurface Ray Casting on Multicore Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Vis. Comput. Graph. ![In: IEEE Trans. Vis. Comput. Graph. 14(3), pp. 603-614, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Earl E. Swartzlander Jr. |
Systolic FFT Processors: A Personal Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(1-2), pp. 3-14, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
systolic systems, frequency domain adaptive digital filters, systolic FFT, fast fourier transforms |
14 | Guillermo Talavera, Murali Jayapala, Jordi Carrabina, Francky Catthoor |
Address Generation Optimization for Embedded High-Performance Processors: A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(3), pp. 271-284, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
optimization, embedded, address generation |
14 | Yaoping Ruan, Vivek S. Pai, Erich M. Nahum, John M. Tracey |
Do commodity SMT processors need more OS research? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGOPS Oper. Syst. Rev. ![In: ACM SIGOPS Oper. Syst. Rev. 42(1), pp. 21-25, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Xuejun Yang, Ying Zhang 0032, Jingling Xue, Ian Rogers, Gen Li 0002, Guibin Wang |
Exploiting loop-dependent stream reuse for stream processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, Toronto, Ontario, Canada, October 25-29, 2008, pp. 22-31, 2008, ACM, 978-1-60558-282-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
StreamC, stream professor, stream register file, stream reuse, stream programming model |
14 | Norm Rubin |
Issues and challenges in compiling for graphics processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Sixth International Symposium on Code Generation and Optimization (CGO 2008), April 5-9, 2008, Boston, MA, USA, pp. 2, 2008, ACM, 978-1-59593-978-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
compilers, graphics |
14 | Meeta Sharma Gupta, Krishna K. Rangan, Michael D. Smith 0001, Gu-Yeon Wei, David M. Brooks |
DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA, pp. 381-392, 2008, IEEE Computer Society, 978-1-4244-2070-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Girish Chandramohan, Ramaswamy Govindarajan |
Improving Performance of Digest Caches in Network Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2008, 15th International Conference, Bangalore, India, December 17-20, 2008. Proceedings, pp. 6-17, 2008, Springer, 978-3-540-89893-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf |
A Hardware Packet Re-Sequencer Unit for Network Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2008, 21st International Conference, Dresden, Germany, February 25-28, 2008, Proceedings, pp. 85-97, 2008, Springer, 978-3-540-78152-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Yen-Kuang Chen, Wenlong Li, Jianguo Li, Tao Wang 0003 |
Novel parallel Hough Transform on multi-core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2008, March 30 - April 4, 2008, Caesars Palace, Las Vegas, Nevada, USA, pp. 1457-1460, 2008, IEEE, 1-4244-1484-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Nara Yang, Gilsang Yoon, Jeonghwan Lee, Intae Hwang, Cheol Hong Kim, Jong-Myon Kim |
Loop Detection for Energy-Aware High Performance Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APSCC ![In: Proceedings of the 3rd IEEE Asia-Pacific Services Computing Conference, APSCC 2008, Yilan, Taiwan, 9-12 December 2008, pp. 1578-1583, 2008, IEEE Computer Society, 978-0-7695-3473-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Thilo Pionteck, Roman Koch, Carsten Albrecht, Erik Maehle, Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf |
Network processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 352, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Fernando Latorre, José González 0002, Antonio González 0001 |
Efficient resources assignment schemes for clustered multithreaded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-12, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Julita Corbalán, Jesús Labarta, Mateo Valero |
Balancing HPC applications through smart allocation of resources in MT processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-12, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | William Lundgren |
Gedae's automated management of hierarchical memories on multicore processors Commercial Tutorial. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-2, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Hongzhou Chen, Lingdi Ping, Xuezeng Pan, Kuijun Lu, Xiaoping Chen |
A Dissipative Resource Distribution policy for SMT processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Kevin J. Barker, Kei Davis, Adolfy Hoisie, Darren J. Kerbyson, Michael Lang 0003, Scott Pakin, José Carlos Sancho |
Experiences in scaling scientific applications on current-generation quad-core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | B. V. N. Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, G. S. Visweswaran |
Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 559-564, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Deokwoo Jung, Andreas Savvides |
An Energy Efficiency Evaluation for Sensor Nodes with Multiple Processors, Radios and Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INFOCOM ![In: INFOCOM 2008. 27th IEEE International Conference on Computer Communications, Joint Conference of the IEEE Computer and Communications Societies, 13-18 April 2008, Phoenix, AZ, USA, pp. 439-447, 2008, IEEE, 978-1-4244-2026-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
VESPA: portable, scalable, and flexible FPGA-based vector processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2008 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 61-70, 2008, ACM. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SPREE, VESPA, VIRAM, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor |
14 | Martín Molina, Gemma Blasco |
Human-Readable and Machine-Readable Knowledge Bases Using Specialized Word Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTAI (1) ![In: 20th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2008), November 3-5, 2008, Dayton, Ohio, USA, Volume 1, pp. 103-110, 2008, IEEE Computer Society, 978-0-7695-3440-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Jun Yan 0008, Wei Zhang 0002 |
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real-Time and Embedded Technology and Applications Symposium ![In: Proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2008, April 22-24, 2008, St. Louis, Missouri, USA, pp. 80-89, 2008, IEEE Computer Society, 978-0-7695-3146-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Bo Xu 0018, Yaxuan Qi, Fei He, Zongwei Zhou, Yibo Xue, Jun Li 0003 |
Fast Path Session Creation on Network Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS ![In: 28th IEEE International Conference on Distributed Computing Systems (ICDCS 2008), 17-20 June 2008, Beijing, China, pp. 573-580, 2008, IEEE Computer Society, 978-0-7695-3172-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Mark Muir, Iain Lindsay, Tughrul Arslan, Ioannis Nousias, Sami Khawam, Mark Milward, Nazish Aslam, Adam Major |
Extensible software emulator for reconfigurable instruction cell based processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 35-40, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Xiaodong Zhang 0001 |
Research Issues and Challenges to Advance System Software for Multicore Processors and Data-Intensive Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC (1) ![In: 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), Shanghai, China, December 17-20, 2008, Volume I, pp. 4, 2008, IEEE Computer Society, 978-0-7695-3492-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Kun-Yuan Hsieh, Yen-Chih Liu, Po-Wen Wu, Shou-Wei Chang, Jenq Kuen Lee |
Enabling Streaming Remoting on Embedded Dual-Core Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 2008 International Conference on Parallel Processing, ICPP 2008, September 8-12, 2008, Portland, Oregon, USA, pp. 35-42, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Ali Afzali-Kusha, Zainalabedin Navabi |
Stall Power Reduction in Pipelined Architecture Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 541-546, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem |
Integrated CPU Cache Power Management in Multiple Clock Domain Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings, pp. 209-223, 2008, Springer, 978-3-540-77559-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Laura C. De Giusti, Franco Chichizola, Marcelo R. Naiouf, Armando De Giusti |
Mapping Tasks to Processors in Heterogeneous Multiprocessor Architectures: The MATEHa Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCCC ![In: XXVII International Conference of the Chilean Computer Science Society (SCCC 2008), 10-14 November 2008, Punta Arenas, Chile, pp. 85-91, 2008, IEEE Computer Society, 978-0-7695-3403-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Wei Han 0001, Ying Yi, Mark Muir, Ioannis Nousias, Tughrul Arslan, Ahmet Teyfik Erdogan |
Efficient Implementation of Wireless Applications on Multi-core Platforms Based on Dynamically Reconfigurable Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CISIS ![In: Second International Conference on Complex, Intelligent and Software Intensive Systems (CISIS-2008), March 4th-7th, 2008, Technical University of Catalonia, Barcelona, Spain, pp. 837-842, 2008, IEEE Computer Society, 978-0-7695-3109-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Yves Vanderperren, Wim Dehaene |
A subsampling pulsed UWB demodulator based on a flexible complex SVD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 114-119, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Rajani Pai, R. Govindarajan |
FEADS: A Framework for Exploring the Application Design Space on Network Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 35(1), pp. 1-31, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
performance Evaluation, petri Nets, design space exploration, network processor, programming model, Cyclic scheduling |
14 | Aviral Shrivastava, Sanghyun Park, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek |
Automatic Design Space Exploration of Register Bypasses in Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12), pp. 2102-2115, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
Instruction set synthesis with efficient instruction encoding for configurable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(1), pp. 9:1-9:37, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
ISA customization and specialization, bitwidth-economical, Application-specific instruction set processor (ASIP), configurable processor, instruction encoding |
14 | Amol Ghoting, Gregory Buehrer, Srinivasan Parthasarathy 0001, Daehyun Kim 0001, Anthony D. Nguyen, Yen-Kuang Chen, Pradeep Dubey |
Cache-conscious frequent pattern mining on modern and emerging processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLDB J. ![In: VLDB J. 16(1), pp. 77-96, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Cache-conscious data mining, Architecture-conscious algorithms, Association rule mining, Frequent pattern mining, Frequent itemset mining |
14 | Francesca Palumbo, Danilo Pani, Luigi Raffo, Simone Secchi |
A Surface Tension and Coalescence Model for Dynamic Distributed Resources Allocation in Massively Parallel Processors on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NICSO ![In: Nature Inspired Cooperative Strategies for Optimization (NICSO 2007), pp. 335-345, 2007, Springer, 978-3-540-78986-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Claudio Talarico, Min-Sung Koh, Esteban Rodriguez-Marek |
System Level Performance Assessment of SOC Processors with SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 14th Annual IEEE International Conference and Workshop on Engineering of Computer Based Systems (ECBS 2007), 26-29 March 2007, Tucson, Arizona, USA, pp. 523-530, 2007, IEEE Computer Society, 0-7695-2772-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Jos Huisken |
Integrating VLIW Processors with a Network on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings, pp. 2, 2007, Springer, 978-3-540-73622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Delong Shang, Chi-Hoon Shin, Ping Wang, Fei Xia, Albert Koelmans, Myeong-Hoon Oh, Seongwoon Kim, Alexandre Yakovlev |
Asynchronous Functional Coupling for Low Power Sensor Network Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 53-63, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Alexey L. Lastovetsky |
On Grid-based Matrix Partitioning for Heterogeneous Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPDC ![In: 6th International Symposium on Parallel and Distributed Computing (ISPDC 2007), Hagenberg, Austria, July 5-8, 2007, pp. 383-390, 2007, IEEE Computer Society, 0-7695-2936-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Chin-Long Wey, Wei-Chien Tang, Shin-Yo Lin |
Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 98-106, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Frederico De Faria, Marius Strum, Jiang Chau Wang |
A System-level Performance Evaluation Methodology for Network Processors Based on Network Calculus Analytical Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 265-272, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar |
Optimizing instruction-set extensible processors under data bandwidth constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 588-593, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Laura Pozzi, Pierre G. Paulin |
A future of customizable processors: are we there yet? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1224-1225, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Athanasios Milidonis, Nikolaos Alachiotis 0002, Vasileios Porpodas, Haralambos Michail, Athanasios Kakarountas, Constantinos E. Goutis |
Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 612-617, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Manoj Gupta 0001, Fermín Sánchez, Josep Llosa |
Merge Logic for Clustered Multithreaded VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 353-360, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Gunar Schirner, Andreas Gerstlauer, Rainer Dömer |
Abstract, Multifaceted Modeling of Embedded Processors for System Level Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 384-389, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Juan Castellanos, Florin Manea, Luis Fernando de Mingo López, Victor Mitrana |
Accepting Networks of Splicing Processors with Filtered Connections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCU ![In: Machines, Computations, and Universality, 5th International Conference, MCU 2007, Orléans, France, September 10-13, 2007, Proceedings, pp. 218-229, 2007, Springer, 978-3-540-74592-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Tomas Dedek, Tomas Marek, Tomás Martínek |
High Level Abstraction Language as an Alternative to Embedded Processors for Internet Packet Processing in FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 648-651, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Gustavo Liñán Cembrano |
Focal plane processors & pixel level processing: mimicking natural vision systems to solve image processing problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 8, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
analog image processing, neural networks, CMOS image sensors, focal plane |
14 | Sadaf R. Alam, Pratul K. Agarwal |
On the Path to Enable Multi-scale Biomolecular Simulations on PetaFLOPS Supercomputer with Multi-core Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-8, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Natalia Dowding, Andy M. Tyrrell |
Sliding Algorithm for Reconfigurable Arrays of Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings, pp. 198-209, 2007, Springer, 978-3-540-74625-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Erfu Yang, Ahmet T. Erdogan, Tughrul Arslan, Nick Barton |
System-Level Modeling and Multi-objective Evolutionary Design of Pipelined FFT Processors for Wireless OFDM Receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings, pp. 210-221, 2007, Springer, 978-3-540-74625-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Alexey L. Lastovetsky, Ravi Reddy |
A Novel Algorithm of Optimal Matrix Partitioning for Parallel Dense Factorization on Heterogeneous Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PaCT ![In: Parallel Computing Technologies, 9th International Conference, PaCT 2007, Pereslavl-Zalessky, Russia, September 3-7, 2007, Proceedings, pp. 261-275, 2007, Springer, 978-3-540-73939-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | José A. M. de Holanda, Jecel Assumpcao, Denis F. Wolf, Eduardo Marques, João M. P. Cardoso |
On Adapting Power Estimation Models for Embedded Soft-Core Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIES ![In: IEEE Second International Symposium on Industrial Embedded Systems, SIES 2007, Hotel Costa da Caparica, Lisbon, Portugal, July 4-6, 2007, pp. 345-348, 2007, IEEE, 1-4244-0840-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Jeremy W. Sheaffer, David P. Luebke, Kevin Skadron |
A hardware redundancy and recovery mechanism for reliable scientific computation on graphics processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Graphics Hardware ![In: Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Conference on Graphics Hardware 2007, San Diego, California, USA, August 4-5, 2007, pp. 55-64, 2007, Eurographics Association, 978-1-59593-625-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Ahmad Zmily, Christos Kozyrakis |
A low power front-end for embedded processors using a block-aware instruction set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 267-276, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
instruction re-ordering, low power front-end, software hints, tagless instruction cache, unified instruction cache and BTB, instruction prefetching |
14 | Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 28-30 May 2007, Porto Alegre, RS, Brazil, pp. 189-194, 2007, IEEE Computer Society, 978-0-7695-2834-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau |
Measuring performance, power, and temperature from real processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Experimental Computer Science ![In: Proceedings of the Workshop on Experimental Computer Science, Part of ACM FCRC, San Diego, CA, USA, 13-14 June 2007, pp. 16, 2007, ACM, 978-1-59593-751-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
power and thermal measurements |
14 | Abhishek Pillai, Wei Zhang 0002, Laurence Tianruo Yang |
Exploring Functional Unit Design Space of VLIW Processors for Optimizing Both Performance and Energy Consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA Workshops (1) ![In: 21st International Conference on Advanced Information Networking and Applications (AINA 2007), Workshops Proceedings, Volume 1, May 21-23, 2007, Niagara Falls, Canada, pp. 792-797, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Keith D. Underwood, Michael J. Levenhagen, Ron Brightwell |
Evaluating NIC hardware requirements to achieve high message rate PGAS support on multi-core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, SC 2007, November 10-16, 2007, Reno, Nevada, USA, pp. 36, 2007, ACM Press, 978-1-59593-764-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Saad Bani-Mohammad, Mohamed Ould-Khaoua, Ismail Ababneh, Lewis M. Mackenzie |
An Efficient Processor Allocation Strategy that Maintains a High Degree of Contiguity among Processors in 2D Mesh Connected Multicomputers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICCSA ![In: 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 13-16 May 2007, Amman, Jordan, pp. 934-941, 2007, IEEE Computer Society, 1-4244-1030-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Susanne Albers, Fabian Müller, Swen Schmelzer |
Speed scaling on parallel processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2007: Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures, San Diego, California, USA, June 9-11, 2007, pp. 289-298, 2007, ACM, 978-1-59593-667-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
approximation algorithms, energy efficiency, NP-completeness, online algorithms, multiprocessor scheduling |
14 | Yaxuan Qi, Bo Xu 0018, Fei He, Baohua Yang, Jianming Yu, Jun Li 0003 |
Towards high-performance flow-level packet processing on multi-core network processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2007, Orlando, Florida, USA, December 3-4, 2007, pp. 17-26, 2007, ACM, 978-1-59593-945-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
packet order, classification, hashing, network processor |
14 | Nikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis, Konstantinos Tatas, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis |
Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 44(1-2), pp. 153-171, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Programmable platforms, estimation methodology, instruction complexity, memory transfers |
14 | Ali Fuat Alkaya, Haluk Rahmi Topcuoglu |
A task scheduling algorithm for arbitrarily-connected processors with awareness of link contention. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Clust. Comput. ![In: Clust. Comput. 9(4), pp. 417-431, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Heterogeneous systems, Task graphs, DAG scheduling, Link contention |
14 | Holger Blume, Daniel Becker 0001, Martin Botteck, Jörg Brakensiek, Tobias G. Noll |
Hybrid Functional and Instruction Level Power Modeling for Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings, pp. 216-226, 2006, Springer, 3-540-36410-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Daisuke Takahashi |
An Implementation of Parallel 1-D FFT Using SSE3 Instructions on Dual-Core Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARA ![In: Applied Parallel Computing. State of the Art in Scientific Computing, 8th International Workshop, PARA 2006, Umeå, Sweden, June 18-21, 2006, Revised Selected Papers, pp. 1178-1187, 2006, Springer, 978-3-540-75754-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Heon-Mo Koo, Prabhat Mishra 0001 |
Functional test generation using property decompositions for validation of pipelined processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1240-1245, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Ahmad Zmily, Christos Kozyrakis |
Simultaneously improving code size, performance, and energy in embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 224-229, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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