Search results for "processors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
14	Hoseok Chang, Wonyong Sung	Access-Pattern-Aware On-Chip Memory Allocation for SIMD Processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
14	Ron Gabor, Avi Mendelson, Shlomo Weiss	Service level agreement for multithreaded processors.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	performance, fairness, throughput, power, Service level agreement
14	Alejandro Linares-Barranco, Rafael Paz, Francisco Gomez-Rodriguez, Angel Jiménez-Fernandez, Manuel Rivas, Gabriel Jiménez, Antón Civit	FPGA Implementations Comparison of Neuro-cortical Inspired Convolution Processors for Spiking Systems.	IWANN (1)	2009	DBLP DOI BibTeX RDF
14	Klaus Jansen	An EPTAS for Scheduling Jobs on Uniform Processors: Using an MILP Relaxation with a Constant Number of Integral Variables.	ICALP (1)	2009	DBLP DOI BibTeX RDF
14	Samir Ammenouche, Sid Ahmed Ali Touati, William Jalby	On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors.	HPCC	2009	DBLP DOI BibTeX RDF
14	Anastasios Gounaris	A Vision for Next Generation Query Processors and an Associated Research Agenda.	Globe	2009	DBLP DOI BibTeX RDF
14	Guoping Long, Dongrui Fan, Junchao Zhang	Characterizing and Understanding the Bandwidth Behavior of Workloads on Multi-core Processors.	Euro-Par	2009	DBLP DOI BibTeX RDF	phase model, memory bandwidth, multi-core architecture
14	Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López 0001	Paired ROBs: A Cost-Effective Reorder Buffer Sharing Strategy for SMT Processors.	Euro-Par	2009	DBLP DOI BibTeX RDF
14	Paolo Bottoni, Anna Labella, Florin Manea, Victor Mitrana, José M. Sempere	Filter Position in Networks of Evolutionary Processors Does Not Matter: A Direct Proof.	DNA	2009	DBLP DOI BibTeX RDF
14	Nan Wu 0003, Mei Wen, Wei Wu, Ju Ren 0002, Huayou Su, Changqing Xun, Chunyuan Zhang	Streaming HD H.264 encoder on programmable processors.	ACM Multimedia	2009	DBLP DOI BibTeX RDF	1080P HD, H.264 encoder, real-time, stream, programmable
14	Peter D. Ungsunan, Chuang Lin 0002, Yang Wang 0018, Yi Gai	Network processing performability evaluation on heterogeneous reliability multicore processors using SRN model.	IPDPS	2009	DBLP DOI BibTeX RDF
14	Ya-Shuai Lü, Li Shen 0007, Zhiying Wang 0003, Nong Xiao	Dynamically utilizing computation accelerators for extensible processors in a software approach.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	computation accelerator, ASIP, dynamic binary translation
14	Yinglong Xia, Xiaojun Feng, Viktor K. Prasanna	Parallel Evidence Propagation on Multicore Processors.	PaCT	2009	DBLP DOI BibTeX RDF	Exact inference, Scheduling, Multicore, Junction tree
14	Paolo Bottoni, Anna Labella, Florin Manea, Victor Mitrana, José M. Sempere	Networks of Evolutionary Picture Processors with Filtered Connections.	UC	2009	DBLP DOI BibTeX RDF
14	Michael Kadin, Sherief Reda, Augustus K. Uht	Central vs. distributed dynamic thermal management for multi-core processors: which one is better?	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dfvs, timing, thermal management
14	Bart Coppens 0001, Ingrid Verbauwhede, Koen De Bosschere, Bjorn De Sutter	Practical Mitigations for Timing-Based Side-Channel Attacks on Modern x86 Processors.	SP	2009	DBLP DOI BibTeX RDF
14	Sourav Roy	H-NMRU: A Low Area, High Performance Cache Replacement Policy for Embedded Processors.	VLSI Design	2009	DBLP DOI BibTeX RDF
14	Rajat Raina, Anand Madhavan, Andrew Y. Ng	Large-scale deep unsupervised learning using graphics processors.	ICML	2009	DBLP DOI BibTeX RDF
14	Talal Bonny, Jörg Henkel	LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processors.	DAC	2009	DBLP DOI BibTeX RDF	embedded systems, code compression, Huffman coding
14	Jungseob Lee, Nam Sung Kim	Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating.	DAC	2009	DBLP DOI BibTeX RDF	multicore processor, DVFS, power gating
14	Jian Chen 0030, Lizy Kurian John	Efficient program scheduling for heterogeneous multi-core processors.	DAC	2009	DBLP DOI BibTeX RDF	program scheduling, heterogeneous multi-core, energy-delay product
14	Shafqat Khan, Emmanuel Casseau, Daniel Ménard	Reconfigurable SWP Operator for Multimedia Processing.	ASAP	2009	DBLP DOI BibTeX RDF
14	Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, Heinrich Meyr, Gerd Ascheid	A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
14	Paolo Ienne, Peter Petrov	Guest Editorial Special Section on Application Specific Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
14	Lukas Kencl, Jean-Yves Le Boudec	Adaptive load sharing for network processors.	IEEE/ACM Trans. Netw.	2008	DBLP DOI BibTeX RDF	load balancing, computer networks, feedback control, load sharing, router architecture, packet processing
14	Dongsoo Kang, Chen Liu 0001, Jean-Luc Gaudiot	The Impact of Speculative Execution on SMT Processors.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	Speculation control, Simultaneous multithreading, Thread scheduling, Confidence estimator
14	Euiseong Seo, Jinkyu Jeong, Seon-Yeong Park, Joonwon Lee	Energy Efficient Scheduling of Real-Time Tasks on Multicore Processors.	IEEE Trans. Parallel Distributed Syst.	2008	DBLP DOI BibTeX RDF
14	Mahdi Fazeli, Reza Farivar 0003, Seyed Ghassem Miremadi	Error Detection Enhancement in PowerPC Architecture-based Embedded Processors.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Physical fault injection, Power supply disturbances, Concurrent error detection, Control flow checking
14	Rajeev Kumar 0004, Dipankar Das 0002	Code compression for performance enhancement of variable-length embedded processors.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	bus switching, code decompression, instruction memory, variable-length ISAs, embedded systems, Code compression, RISC processor
14	Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	coarse-grained FPGA, VLIW, ASIP
14	Qin Wang 0007, Joseph F. JáJá	Interactive High-Resolution Isosurface Ray Casting on Multicore Processors.	IEEE Trans. Vis. Comput. Graph.	2008	DBLP DOI BibTeX RDF
14	Earl E. Swartzlander Jr.	Systolic FFT Processors: A Personal Perspective.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	systolic systems, frequency domain adaptive digital filters, systolic FFT, fast fourier transforms
14	Guillermo Talavera, Murali Jayapala, Jordi Carrabina, Francky Catthoor	Address Generation Optimization for Embedded High-Performance Processors: A Survey.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	optimization, embedded, address generation
14	Yaoping Ruan, Vivek S. Pai, Erich M. Nahum, John M. Tracey	Do commodity SMT processors need more OS research?	ACM SIGOPS Oper. Syst. Rev.	2008	DBLP DOI BibTeX RDF
14	Xuejun Yang, Ying Zhang 0032, Jingling Xue, Ian Rogers, Gen Li 0002, Guibin Wang	Exploiting loop-dependent stream reuse for stream processors.	PACT	2008	DBLP DOI BibTeX RDF	StreamC, stream professor, stream register file, stream reuse, stream programming model
14	Norm Rubin	Issues and challenges in compiling for graphics processors.	CGO	2008	DBLP DOI BibTeX RDF	compilers, graphics
14	Meeta Sharma Gupta, Krishna K. Rangan, Michael D. Smith 0001, Gu-Yeon Wei, David M. Brooks	DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors.	HPCA	2008	DBLP DOI BibTeX RDF
14	Girish Chandramohan, Ramaswamy Govindarajan	Improving Performance of Digest Caches in Network Processors.	HiPC	2008	DBLP DOI BibTeX RDF
14	Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf	A Hardware Packet Re-Sequencer Unit for Network Processors.	ARCS	2008	DBLP DOI BibTeX RDF
14	Yen-Kuang Chen, Wenlong Li, Jianguo Li, Tao Wang 0003	Novel parallel Hough Transform on multi-core processors.	ICASSP	2008	DBLP DOI BibTeX RDF
14	Nara Yang, Gilsang Yoon, Jeonghwan Lee, Intae Hwang, Cheol Hong Kim, Jong-Myon Kim	Loop Detection for Energy-Aware High Performance Embedded Processors.	APSCC	2008	DBLP DOI BibTeX RDF
14	Thilo Pionteck, Roman Koch, Carsten Albrecht, Erik Maehle, Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf	Network processors.	FPL	2008	DBLP DOI BibTeX RDF
14	Fernando Latorre, José González 0002, Antonio González 0001	Efficient resources assignment schemes for clustered multithreaded processors.	IPDPS	2008	DBLP DOI BibTeX RDF
14	Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Julita Corbalán, Jesús Labarta, Mateo Valero	Balancing HPC applications through smart allocation of resources in MT processors.	IPDPS	2008	DBLP DOI BibTeX RDF
14	William Lundgren	Gedae's automated management of hierarchical memories on multicore processors Commercial Tutorial.	IPDPS	2008	DBLP DOI BibTeX RDF
14	Hongzhou Chen, Lingdi Ping, Xuezeng Pan, Kuijun Lu, Xiaoping Chen	A Dissipative Resource Distribution policy for SMT processors.	IPDPS	2008	DBLP DOI BibTeX RDF
14	Kevin J. Barker, Kei Davis, Adolfy Hoisie, Darren J. Kerbyson, Michael Lang 0003, Scott Pakin, José Carlos Sancho	Experiences in scaling scientific applications on current-generation quad-core processors.	IPDPS	2008	DBLP DOI BibTeX RDF
14	B. V. N. Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, G. S. Visweswaran	Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors.	ICCAD	2008	DBLP DOI BibTeX RDF
14	Deokwoo Jung, Andreas Savvides	An Energy Efficiency Evaluation for Sensor Nodes with Multiple Processors, Radios and Sensors.	INFOCOM	2008	DBLP DOI BibTeX RDF
14	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	VESPA: portable, scalable, and flexible FPGA-based vector processors.	CASES	2008	DBLP DOI BibTeX RDF	SPREE, VESPA, VIRAM, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor
14	Martín Molina, Gemma Blasco	Human-Readable and Machine-Readable Knowledge Bases Using Specialized Word Processors.	ICTAI (1)	2008	DBLP DOI BibTeX RDF
14	Jun Yan 0008, Wei Zhang 0002	WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches.	IEEE Real-Time and Embedded Technology and Applications Symposium	2008	DBLP DOI BibTeX RDF
14	Bo Xu 0018, Yaxuan Qi, Fei He, Zongwei Zhou, Yibo Xue, Jun Li 0003	Fast Path Session Creation on Network Processors.	ICDCS	2008	DBLP DOI BibTeX RDF
14	Mark Muir, Iain Lindsay, Tughrul Arslan, Ioannis Nousias, Sami Khawam, Mark Milward, Nazish Aslam, Adam Major	Extensible software emulator for reconfigurable instruction cell based processors.	SoCC	2008	DBLP DOI BibTeX RDF
14	Xiaodong Zhang 0001	Research Issues and Challenges to Advance System Software for Multicore Processors and Data-Intensive Applications.	EUC (1)	2008	DBLP DOI BibTeX RDF
14	Kun-Yuan Hsieh, Yen-Chih Liu, Po-Wen Wu, Shou-Wei Chang, Jenq Kuen Lee	Enabling Streaming Remoting on Embedded Dual-Core Processors.	ICPP	2008	DBLP DOI BibTeX RDF
14	Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Ali Afzali-Kusha, Zainalabedin Navabi	Stall Power Reduction in Pipelined Architecture Processors.	VLSI Design	2008	DBLP DOI BibTeX RDF
14	Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem	Integrated CPU Cache Power Management in Multiple Clock Domain Processors.	HiPEAC	2008	DBLP DOI BibTeX RDF
14	Laura C. De Giusti, Franco Chichizola, Marcelo R. Naiouf, Armando De Giusti	Mapping Tasks to Processors in Heterogeneous Multiprocessor Architectures: The MATEHa Algorithm.	SCCC	2008	DBLP DOI BibTeX RDF
14	Wei Han 0001, Ying Yi, Mark Muir, Ioannis Nousias, Tughrul Arslan, Ahmet Teyfik Erdogan	Efficient Implementation of Wireless Applications on Multi-core Platforms Based on Dynamically Reconfigurable Processors.	CISIS	2008	DBLP DOI BibTeX RDF
14	Yves Vanderperren, Wim Dehaene	A subsampling pulsed UWB demodulator based on a flexible complex SVD.	ASAP	2008	DBLP DOI BibTeX RDF
14	Rajani Pai, R. Govindarajan	FEADS: A Framework for Exploring the Application Design Space on Network Processors.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	performance Evaluation, petri Nets, design space exploration, network processor, programming model, Cyclic scheduling
14	Aviral Shrivastava, Sanghyun Park, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek	Automatic Design Space Exploration of Register Bypasses in Embedded Processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
14	Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt	Instruction set synthesis with efficient instruction encoding for configurable processors.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	ISA customization and specialization, bitwidth-economical, Application-specific instruction set processor (ASIP), configurable processor, instruction encoding
14	Amol Ghoting, Gregory Buehrer, Srinivasan Parthasarathy 0001, Daehyun Kim 0001, Anthony D. Nguyen, Yen-Kuang Chen, Pradeep Dubey	Cache-conscious frequent pattern mining on modern and emerging processors.	VLDB J.	2007	DBLP DOI BibTeX RDF	Cache-conscious data mining, Architecture-conscious algorithms, Association rule mining, Frequent pattern mining, Frequent itemset mining
14	Francesca Palumbo, Danilo Pani, Luigi Raffo, Simone Secchi	A Surface Tension and Coalescence Model for Dynamic Distributed Resources Allocation in Massively Parallel Processors on-Chip.	NICSO	2007	DBLP DOI BibTeX RDF
14	Claudio Talarico, Min-Sung Koh, Esteban Rodriguez-Marek	System Level Performance Assessment of SOC Processors with SystemC.	ECBS	2007	DBLP DOI BibTeX RDF
14	Jos Huisken	Integrating VLIW Processors with a Network on Chip.	SAMOS	2007	DBLP DOI BibTeX RDF
14	Delong Shang, Chi-Hoon Shin, Ping Wang, Fei Xia, Albert Koelmans, Myeong-Hoon Oh, Seongwoon Kim, Alexandre Yakovlev	Asynchronous Functional Coupling for Low Power Sensor Network Processors.	PATMOS	2007	DBLP DOI BibTeX RDF
14	Alexey L. Lastovetsky	On Grid-based Matrix Partitioning for Heterogeneous Processors.	ISPDC	2007	DBLP DOI BibTeX RDF
14	Chin-Long Wey, Wei-Chien Tang, Shin-Yo Lin	Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications.	ISVLSI	2007	DBLP DOI BibTeX RDF
14	Frederico De Faria, Marius Strum, Jiang Chau Wang	A System-level Performance Evaluation Methodology for Network Processors Based on Network Calculus Analytical Modeling.	ISVLSI	2007	DBLP DOI BibTeX RDF
14	Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar	Optimizing instruction-set extensible processors under data bandwidth constraints.	DATE	2007	DBLP DOI BibTeX RDF
14	Laura Pozzi, Pierre G. Paulin	A future of customizable processors: are we there yet?	DATE	2007	DBLP DOI BibTeX RDF
14	Athanasios Milidonis, Nikolaos Alachiotis 0002, Vasileios Porpodas, Haralambos Michail, Athanasios Kakarountas, Constantinos E. Goutis	Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy.	DATE	2007	DBLP DOI BibTeX RDF
14	Manoj Gupta 0001, Fermín Sánchez, Josep Llosa	Merge Logic for Clustered Multithreaded VLIW Processors.	DSD	2007	DBLP DOI BibTeX RDF
14	Gunar Schirner, Andreas Gerstlauer, Rainer Dömer	Abstract, Multifaceted Modeling of Embedded Processors for System Level Design.	ASP-DAC	2007	DBLP DOI BibTeX RDF
14	Juan Castellanos, Florin Manea, Luis Fernando de Mingo López, Victor Mitrana	Accepting Networks of Splicing Processors with Filtered Connections.	MCU	2007	DBLP DOI BibTeX RDF
14	Tomas Dedek, Tomas Marek, Tomás Martínek	High Level Abstraction Language as an Alternative to Embedded Processors for Internet Packet Processing in FPGA.	FPL	2007	DBLP DOI BibTeX RDF
14	Gustavo Liñán Cembrano	Focal plane processors & pixel level processing: mimicking natural vision systems to solve image processing problems.	SBCCI	2007	DBLP DOI BibTeX RDF	analog image processing, neural networks, CMOS image sensors, focal plane
14	Sadaf R. Alam, Pratul K. Agarwal	On the Path to Enable Multi-scale Biomolecular Simulations on PetaFLOPS Supercomputer with Multi-core Processors.	IPDPS	2007	DBLP DOI BibTeX RDF
14	Natalia Dowding, Andy M. Tyrrell	Sliding Algorithm for Reconfigurable Arrays of Processors.	ICES	2007	DBLP DOI BibTeX RDF
14	Erfu Yang, Ahmet T. Erdogan, Tughrul Arslan, Nick Barton	System-Level Modeling and Multi-objective Evolutionary Design of Pipelined FFT Processors for Wireless OFDM Receivers.	ICES	2007	DBLP DOI BibTeX RDF
14	Alexey L. Lastovetsky, Ravi Reddy	A Novel Algorithm of Optimal Matrix Partitioning for Parallel Dense Factorization on Heterogeneous Processors.	PaCT	2007	DBLP DOI BibTeX RDF
14	José A. M. de Holanda, Jecel Assumpcao, Denis F. Wolf, Eduardo Marques, João M. P. Cardoso	On Adapting Power Estimation Models for Embedded Soft-Core Processors.	SIES	2007	DBLP DOI BibTeX RDF
14	Jeremy W. Sheaffer, David P. Luebke, Kevin Skadron	A hardware redundancy and recovery mechanism for reliable scientific computation on graphics processors.	Graphics Hardware	2007	DBLP DOI BibTeX RDF
14	Ahmad Zmily, Christos Kozyrakis	A low power front-end for embedded processors using a block-aware instruction set.	CASES	2007	DBLP DOI BibTeX RDF	instruction re-ordering, low power front-end, software hints, tagless instruction cache, unified instruction cache and BTB, instruction prefetching
14	Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
14	Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau	Measuring performance, power, and temperature from real processors.	Experimental Computer Science	2007	DBLP DOI BibTeX RDF	power and thermal measurements
14	Abhishek Pillai, Wei Zhang 0002, Laurence Tianruo Yang	Exploring Functional Unit Design Space of VLIW Processors for Optimizing Both Performance and Energy Consumption.	AINA Workshops (1)	2007	DBLP DOI BibTeX RDF
14	Keith D. Underwood, Michael J. Levenhagen, Ron Brightwell	Evaluating NIC hardware requirements to achieve high message rate PGAS support on multi-core processors.	SC	2007	DBLP DOI BibTeX RDF
14	Saad Bani-Mohammad, Mohamed Ould-Khaoua, Ismail Ababneh, Lewis M. Mackenzie	An Efficient Processor Allocation Strategy that Maintains a High Degree of Contiguity among Processors in 2D Mesh Connected Multicomputers.	AICCSA	2007	DBLP DOI BibTeX RDF
14	Susanne Albers, Fabian Müller, Swen Schmelzer	Speed scaling on parallel processors.	SPAA	2007	DBLP DOI BibTeX RDF	approximation algorithms, energy efficiency, NP-completeness, online algorithms, multiprocessor scheduling
14	Yaxuan Qi, Bo Xu 0018, Fei He, Baohua Yang, Jianming Yu, Jun Li 0003	Towards high-performance flow-level packet processing on multi-core network processors.	ANCS	2007	DBLP DOI BibTeX RDF	packet order, classification, hashing, network processor
14	Nikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis, Konstantinos Tatas, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis	Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	Programmable platforms, estimation methodology, instruction complexity, memory transfers
14	Ali Fuat Alkaya, Haluk Rahmi Topcuoglu	A task scheduling algorithm for arbitrarily-connected processors with awareness of link contention.	Clust. Comput.	2006	DBLP DOI BibTeX RDF	Heterogeneous systems, Task graphs, DAG scheduling, Link contention
14	Holger Blume, Daniel Becker 0001, Martin Botteck, Jörg Brakensiek, Tobias G. Noll	Hybrid Functional and Instruction Level Power Modeling for Embedded Processors.	SAMOS	2006	DBLP DOI BibTeX RDF
14	Daisuke Takahashi	An Implementation of Parallel 1-D FFT Using SSE3 Instructions on Dual-Core Processors.	PARA	2006	DBLP DOI BibTeX RDF
14	Heon-Mo Koo, Prabhat Mishra 0001	Functional test generation using property decompositions for validation of pipelined processors.	DATE	2006	DBLP DOI BibTeX RDF
14	Ahmad Zmily, Christos Kozyrakis	Simultaneously improving code size, performance, and energy in embedded processors.	DATE	2006	DBLP DOI BibTeX RDF