Search results for "45nm"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
59	Kenichi Okada, Takumi Uezono, Kazuya Masu	Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology.	PATMOS	2006	DBLP DOI BibTeX RDF
46	David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat	Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic.	ISLPED	2009	DBLP DOI BibTeX RDF	short-channel effects, subthreshold logic, variability, cmos digital integrated circuits, ultra-low power, gate leakage
46	Dan Bailey, Eric Soenen, Puneet Gupta, Paul G. Villarrubia, Sang H. Dhong	Challenges at 45nm and beyond.	ICCAD	2008	DBLP DOI BibTeX RDF
46	Yu Cao, Colin C. McAndrew	MOSFET modeling for 45nm and beyond.	ICCAD	2007	DBLP DOI BibTeX RDF
46	Philippe Magarshack	Design challenges in 45nm and below: DFM, low-power and design for reliability.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	design for reliability, low-power design, design for manufacturability
46	David J. Frank, Ruchir Puri, Dorel Toma	Design and CAD challenges in 45nm CMOS and beyond.	ICCAD	2006	DBLP DOI BibTeX RDF
39	Jinwen Xi, Peixin Zhong	A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	network-on-chip, SystemC, energy model
36	Stephen P. Kornachuk, Michael C. Smayling	New strategies for gridded physical design for 32nm technologies and beyond.	ISPD	2009	DBLP DOI BibTeX RDF	28nm, 32nm, 45nm, litho, rdr, placement, layout, physical design, manufacturability, lithography, standard cell, vlsi, drc, dfm
33	David Bol, Denis Flandre, Jean-Didier Legat	Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	adaptive circuits, subthreshold logic, variability, CMOS digital integrated circuits, ultra-low power
33	R. Venkatraman, R. Castagnetti, Andres Teene, Benjamin Mbouombouo, S. Ramesh 0004	Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design.	ISQED	2009	DBLP DOI BibTeX RDF
33	David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat	Analysis and minimization of practical energy in 45nm subthreshold logic circuits.	ICCD	2008	DBLP DOI BibTeX RDF
33	Samuel Rodríguez, Bruce L. Jacob	Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm).	ISLPED	2006	DBLP DOI BibTeX RDF	nanometer design, pipelined caches, cache design
26	Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke	ZerehCache: armoring cache architectures in high defect density technologies.	MICRO	2009	DBLP DOI BibTeX RDF	fault-tolerant cache, process variation, manufacturing yield
26	Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri	Low power and high performance sram design using bank-based selective forward body bias.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	low power, high performance, body bias
26	John H. Kelm, Daniel R. Johnson, Matthew R. Johnson 0003, Neal Clayton Crago, William Tuohy, Aqeel Mahesri, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel	Rigel: an architecture and scalable programming interface for a 1000-core accelerator.	ISCA	2009	DBLP DOI BibTeX RDF	low-level programming interface, computer architecture, accelerator
26	Andrew B. Kahng	How to get real mad.	ISPD	2008	DBLP DOI BibTeX RDF	design-aware manufacturing, integrated circuit physical design, manufacturing-aware design, performance analysis, design for manufacturability
26	Shayak Banerjee, Praveen Elakkumanan, Lars Liebmann, Michael Orshansky	Electrically driven optical proximity correction based on linear programming.	ICCAD	2008	DBLP DOI BibTeX RDF
26	Andrew B. Kahng, Chul-Hong Park, Xu Xu 0001, Hailong Yao	Layout decomposition for double patterning lithography.	ICCAD	2008	DBLP DOI BibTeX RDF
26	Jae-sun Seo, Igor L. Markov, Dennis Sylvester, David T. Blaauw	On the decreasing significance of large standard cells in technology mapping.	ICCAD	2008	DBLP DOI BibTeX RDF
26	Srinivasa R. S. T. G, Srivatsava Jandhyala, Narahari Tondamuthuru R	Process Variability Analysis in DSM Through Statistical Simulations and its Implications to Design Methodologies.	ISQED	2008	DBLP DOI BibTeX RDF	Design Methodologies, Random, DSM, Variations, Systematic
26	Shankar Krishnamoorthy	Variation and litho driven physical implementation system.	ISPD	2007	DBLP DOI BibTeX RDF	multi-variation optimization, VLSI, lithography
26	Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu	A Study on Impact of Leakage Current on Dynamic Power.	ISCAS	2007	DBLP DOI BibTeX RDF
26	Chih-Yuan Lu	Non-volatile Semiconductor Memory Technology in Nanotech Era.	MTDT	2006	DBLP DOI BibTeX RDF
20	Kaisarbek Omirzakhov, Firooz Aflatouni	12.1 Monolithically Integrated Sub-63 fJ/b 8-Channel 256Gb/s Optical Transmitter with Autonomous Wavelength Locking in 45nm CMOS SOI.	ISSCC	2024	DBLP DOI BibTeX RDF
20	Alexandre Siligaris, A. Bossuet, L. Barrau, E. Antide, José Luis González-Jiménez, Cédric Dehos, Mykhailo Zarudniev	Fast Chirping 58-64 GHz FMCW Radar Transceiver using D-PROT Multiplier in CMOS 45nm RFSOI for Vital Signs Detection.	ESSCIRC	2023	DBLP DOI BibTeX RDF
20	Mengfu Di, Weiquan Hao, Xunyu Li, Zijin Pan, Runyu Miao, Albert Z. Wang	A 38GHz SPDT Traveling Wave Switch with 5A CDM ESD Protection in 45nm PDSOI for 5G System.	RWS	2023	DBLP DOI BibTeX RDF
20	Mayank Raj, Chuan Xie, Ade Bekele, Adam Chou, Wenfeng Zhang, Ying Cao 0010, Jae Wook Kim, Nakul Narang, Hongyuan Zhao, Yipeng Wang 0003, Kee Hian Tan, Winson Lin, Jay Im, David Mahashin, Santiago Asuncion, Parag Upadhyaya, Yohan Frans	A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies.	ISSCC	2023	DBLP DOI BibTeX RDF
20	Wenli Liao, Chengying Chen, Daifa Gao, Yufei Huang	A 10Gbps High-Speed Low-Noise Optical Receiver Based on CMOS 45nm Technology.	ASICON	2023	DBLP DOI BibTeX RDF
20	Debapriya Sahu, V. Srinivas, Rohit Chatterjee, Meghna Agarwal, P. Agrawal, R. Juluri, M. Mukherjee, Vimal Edayath, A. Yerramsetty, G. Bakalzuk, O. Rahmanony, K. Rajmohan, A Sancheti, R. Anand	A Triple-Band Radio for WLAN 11b/g/n/ax in 45nm CMOS.	A-SSCC	2023	DBLP DOI BibTeX RDF
20	Yuta Sako, Tomohiro Kobayashi, Shinsuke Hara, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima	254-GHz-to-299-GHz Down Conversion Mixer Using 45nm SOI CMOS.	MWSCAS	2022	DBLP DOI BibTeX RDF
20	Abhishek Kumar, Suman Lata Tripathi, Chaman Verma, Maria Simona Raboaca, Florentina-Magda Enescu, Traian Candin Mihaltan	Design and Analysis of Low Power Bio-amplifier with Current Mirror Topology at CMOS 45nm Technology Node.	ECAI	2022	DBLP DOI BibTeX RDF
20	Vincent Lammert, Michael L. Leyrer, Vadim Issakov	A D-Band Transceiver with On-Chip Multi-Port Radiators and Leakage Cancellation in 45nm SOI.	BCICTS	2022	DBLP DOI BibTeX RDF
20	Yahia Z. M. Ibrahim, Mohamed A. Y. Abdalla, Ahmed N. Mohieldin	A 197 FoMT VCO with 34% Tuning Range for 5G Applications in 45nm SOI Technology.	RWS	2022	DBLP DOI BibTeX RDF
20	Cameron Hill, James F. Buckwalter	A 1-to-18GHz Distributed-Stacked-Complementary Triple-Balanced Passive Mixer With up to 33dBm IIP3 and Integrated LO Driver in 45nm CMOS SOI.	ISSCC	2022	DBLP DOI BibTeX RDF
20	Mohamed A. Elgammal, M. Weheiba, Mohamed M. R. Esmael, Mohamed A. Y. Abdalla, Ahmed N. Mohieldin	A 37-43GHz Two Way Current Combining Power Amplifier with 19.6-dBm P1dB for 5G Phased Arrays in 45nm-SOI CMOS.	ICECS	2021	DBLP DOI BibTeX RDF
20	John J. Pekarik, Vibhor Jain, Crystal Kenney, Judson Holt, Shweta Khokale, Sudesh Saroop, Jeffrey B. Johnson, Kenneth J. Stein, Viorel Ontalus, Christopher Durcan, Mona Nafari, Tayel Nesheiwat, Sangameshwar Saudari, Elahe Yarmoghaddam, Saloni Chaurasia, Alvin J. Joseph	SiGe HBTs with ${f_{T}/f_{\max}\, \sim\, 375/510GHz}$ Integrated in 45nm PDSOI CMOS.	BCICTS	2021	DBLP DOI BibTeX RDF
20	Preethi Padmanabhan, Chao Zhang 0019, Marco Cazzaniga, Baris Efe, Augusto Ronchini Ximenes, Myung-Jae Lee, Edoardo Charbon	7.4 A 256×128 3D-Stacked (45nm) SPAD FLASH LiDAR with 7-Level Coincidence Detection and Progressive Gating for 100m Range and 10klux Background Light.	ISSCC	2021	DBLP DOI BibTeX RDF
20	Panagiotis G. Zarkos, Sidney Buchbinder, Christos G. Adamopoulos, Sarika Madhvapathy, Olivia Hsu, Jake Whinnery, Pavan Bhargava, Vladimir Stojanovic	Fully Integrated Electronic-Photonic Ultrasound Receiver Array for Endoscopic Imaging Applications in a Zero-Change 45nm CMOS-SOI Process.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
20	Hayk Gevorgyan, Anatol Khilo, Derek Van Orden, Deniz Onural, Bozhi Yin, Mark T. Wade, Vladimir Marko Stojanovic, Milos A. Popovic	Cryo-Compatible, Silicon Spoked-Ring Modulator in a 45nm CMOS Platform for 4K-to-Room-Temperature Optical Links.	OFC	2021	DBLP BibTeX RDF
20	Sunita M. S, Tejas Somashekhar, Shashidhar Tantry	Adaptive ON - Time Boost Converter in 45nm for Solar Cell Applications.	ISOCC	2021	DBLP DOI BibTeX RDF
20	Sumukh Nitundil, Nihal Singh, Rushabha Balaji, Pankaj Arora	Design and Comparative Analysis of a Two-Stage Ultra-Low-Power Subthreshold Operational Amplifier in 180nm, 90nm, and 45nm technology.	CoRR	2020	DBLP BibTeX RDF
20	Aritra Banerjee, Lei Ding 0001, Rahmi Hezar	A High Efficiency Multi-Mode Outphasing RF Power Amplifier With 31.6 dBm Peak Output Power in 45nm CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2020	DBLP DOI BibTeX RDF
20	Jani K. Jarvenhaara, Igor M. Filanovsky, I. Nevalainen, Nikolay T. Tchamov	A Two-Stage LNA Design for 28GHz Band Of 5G on 45nm CMOS.	MWSCAS	2020	DBLP DOI BibTeX RDF
20	Richard Calusdian, Aaron Stillmaker	Hardware Implementation of HEVC Inverse Transform in 45nm CMOS.	LASCAS	2020	DBLP DOI BibTeX RDF
20	Dongyi Liao, Fa Foster Dai	A 7.7~10.3GHz 5.2mW -247.3dB-FOM Fractional-N Reference Sampling PLL with 2nd Order CDAC Based Fractional Spur Cancellation In 45nm CMOS.	CICC	2020	DBLP DOI BibTeX RDF
20	Farid Uddin Ahmed, Zarin Tasnim Sandhie, Masud H. Chowdhury	An Implementation of External Capacitor-less Low-DropOut Voltage Regulator in 45nm Technology with Output Voltage Ranging from 0.4V-1.2V.	ICCD	2020	DBLP DOI BibTeX RDF
20	Sarah Azimi, Corrado De Sio, Luca Sterpone	In-Circuit Mitigation Approach of Single Event Transients for 45nm Flip-Flops.	IOLTS	2020	DBLP DOI BibTeX RDF
20	Michal Rakowski, Colleen Meagher, Karen Nummy, Abdelsalam Aboketaf, Javier Ayala, Yusheng Bian, Brendan Harris, Kate McLean, Kevin McStay, Asli Sahin, Louis Medina, Bo Peng, Zoey Sowinski, Andy Stricker, Thomas Houghton, Crystal Hedges, Ken Giewont, Ajey P. Jacob, Ted Letavic, Dave Riggs, Anthony Yu, John Pellerin	45nm CMOS - Silicon Photonics Monolithic Technology (45CLO) for Next-Generation, Low Power and High Speed Optical Interconnects.	OFC	2020	DBLP BibTeX RDF
20	Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, B. Naresh Kumar Reddy	A Single BJT 10.2 ppm/°C Bandgap Reference in 45nm CMOS Technology.	ICCCNT	2020	DBLP DOI BibTeX RDF
20	Chia-Heng Lee, Ying-Tuan Hsu, Tsung-Te Liu, Tzi-Dar Chiueh	Design of an 45nm NCFET Based Compute-in-SRAM for Energy-Efficient Machine Learning Applications.	APCCAS	2020	DBLP DOI BibTeX RDF
20	Nandish Mehta, Sidney Buchbinder, Vladimir Stojanovic	Design and Characterization of Monolithic Microring Resonator based Photodetector in 45nm SOI CMOS.	ESSDERC	2019	DBLP DOI BibTeX RDF
20	Mikko Hietanen, Janne Aikio, Alok Sethi, Rehman Akbar, Timo Rahkonen, Aarno Pärssinen	Optimizing Inductorless Static CML Frequency Dividers up to 23GHz Output Using 45nm CMOS PD-SOI.	NORCAS	2019	DBLP DOI BibTeX RDF
20	Wooram Lee	A 48-79 GHz Low-Noise Amplifier with Broadband Phase-Invariant Gain Control in 45nm SOI CMOS.	BCICTS	2019	DBLP DOI BibTeX RDF
20	Zhan Su, Hechen Wang, Haoyi Zhao, Zhenqi Chen, Yanjie Wang, Fa Foster Dai	A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-Range Quantizer in 45nm CMOS.	CICC	2019	DBLP DOI BibTeX RDF
20	Yehya Nasser, Carlo Sau, Jean-Christophe Prévotet, Tiziana Fanni, Francesca Palumbo, Maryline Hélard, Luigi Raffo	NeuPow: artificial neural networks for power and behavioral modeling of arithmetic components in 45nm ASICs technology.	CF	2019	DBLP DOI BibTeX RDF
20	Nandish Mehta, Sen Lin, Bozhi Yin, Sajjad Moazeni, Vladimir Stojanovic	A Laser-forwarded Coherent 10Gb/s BPSK Transceiver using Monolithic Microring Resonators in 45nm SOI CMOS.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
20	Rana Azhar Shaheen, Rehman Akbar, Timo Rahkonen, Janne Aikio, Alok Sethi, Aarno Pärssinen	A Differential Reflection-Type Phase Shifter Based on CPW Coupled-Line Coupler in 45nm CMOS SOI.	ISWCS	2019	DBLP DOI BibTeX RDF
20	Pham-Khoi Dong, Hung K. Nguyen, Xuan-Tu Tran	A 45nm High-Throughput and Low Latency AES Encryption for Real-Time Applications.	ISCIT	2019	DBLP DOI BibTeX RDF
20	Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, B. Naresh Kumar Reddy, B. Seetharamulu	A High Frequency CMRR improvement technique for Differential Amplifiers in 45nm CMOS.	ICCCNT	2019	DBLP DOI BibTeX RDF
20	Debapriya Sahu, Rittu Sachdev-Singh, Harikrishna Parthasarathy, Rohit Chatterjee, Brian P. Ginsburg, Daniel Breen, Karan Bhatia, Sudhir Polarouthu, Vimal Edayath, Bhupendra Sharma, Meghna Agarwal, Karthik Subburaj, Anjan Prasad, Shankar Ram, Cathy Chi, Ross Kulak, Vijay Rentala, Neeraj P. Nayak	A 45nm 76-81GHz CMOS Radar Receiver for Automotive Applications.	A-SSCC	2019	DBLP DOI BibTeX RDF
20	Devon Thomas, Narek Rostomyan, Peter M. Asbeck	A 45 % PAE pMOS Power Amplifier for 28GHz Applications in 45nm SOI.	MWSCAS	2018	DBLP DOI BibTeX RDF
20	Chenkun Wang, Fei Lu 0004, Qi Chen 0008, Feilong Zhang 0001, Cheng Li, Dawn Wang, Albert Z. Wang	A study of impacts of ESD protection on 28/38GHz RF switches in 45nm SOI CMOS for 5G mobile applications.	RWS	2018	DBLP DOI BibTeX RDF
20	Sen Lin, Sajjad Moazeni, Vladimir Stojanovic	A 40GB/S Optical NRZ Transmitter Based on Monolithic Microring Modulators in 45NM SOI CMOS.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
20	Yang Xie, Dan Li 0011, Yiqun Liu 0011, Ming Liu, Yihua Zhang, Xiaoli Wang, Li Geng	Low-Noise High-Linearity 56Gb/s PAM-4 Optical Receiver in 45nm SOI CMOS.	ISCAS	2018	DBLP DOI BibTeX RDF
20	Vishal Gupta 0002, Saurabh Khandelwal, Jimson Mathew, Marco Ottavi	45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control.	DFT	2018	DBLP DOI BibTeX RDF
20	Hyunki Jung, Dzuhri Radityo Utomo, Saebyeok Shin, Seok-Kyun Han, Sang-Gug Lee 0001, Jusung Kim	Ka-band RF Front-End with 5dB NF and 16dB conversion gain in 45nm CMOS technology.	ISOCC	2018	DBLP DOI BibTeX RDF
20	Linga Reddy Cenkeramaddi	Feedback Biasing Based Adjustable Gain Ultrasound Preamplifier for CMUTs in 45nm CMOS.	VLSID	2018	DBLP DOI BibTeX RDF
20	Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai	Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology.	IEICE Trans. Electron.	2017	DBLP DOI BibTeX RDF
20	Vida Orduee Niar, Gholamreza Zareh Fatin	A Low Power Low-Pass Fourth-Order Filter for WiMAX/LTE Receiver in CMOS 45nm Technology.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
20	Aritra Banerjee, Rahmi Hezar, Lei Ding 0001, Baher Haroun	A 29.5 dBm Class-E Outphasing RF Power Amplifier With Efficiency and Output Power Enhancement Circuits in 45nm CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
20	Lohith Kumar Vemula, Nahid M. Hossain, Masud H. Chowdhury	Emerging STT-MRAM circuit and architecture co-design in 45nm technology.	MWSCAS	2017	DBLP DOI BibTeX RDF
20	Rana Azhar Shaheen, Rehman Akbar, Alok Sethi, Janne P. Aikio, Timo Rahkonen, Aarno Pärssinen	A 45nm CMOS SOI, four element phased array receiver supporting two MIMO channels for 5G.	NORCAS	2017	DBLP DOI BibTeX RDF
20	Sajjad Moazeni, Sen Lin, Mark T. Wade, Luca Alloatti, Rajeev J. Ram, Milos A. Popovic, Vladimir Stojanovic	29.3 A 40Gb/s PAM-4 transmitter based on a ring-resonator optical DAC in 45nm SOI CMOS.	ISSCC	2017	DBLP DOI BibTeX RDF
20	Sarfraz Hussain, Rajesh Kumar, Gaurav Trivedi	A Novel Low Power High Speed BEC for 2GHz Sampling Rate Flash ADC in 45nm Technology.	iNIS	2017	DBLP DOI BibTeX RDF
20	Nandish Mehta, Chen Sun 0003, Mark T. Wade, Sen Lin, Milos A. Popovic, Vladimir Stojanovic	A 12Gb/s, 8.6µApp input sensitivity, monolithic-integrated fully differential optical receiver in CMOS 45nm SOI process.	ESSCIRC	2016	DBLP DOI BibTeX RDF
20	Mohammad Sadegh Mehrjoo, James F. Buckwalter	13.4 A microwave injection-locking outphasing modulator with 30dB dynamic range and 22% system efficiency in 45nm CMOS SOI.	ISSCC	2016	DBLP DOI BibTeX RDF
20	Nikolaus Klemmer, S. Akhtar, V. Srinivasan, P. Litmanen, Himanshu Arora, Satish Uppathil, Scott Kaylor, A. Akour, V. Wang, M. Fares, F. Dulger, A. Frank, D. Ghosh, S. Madhavapeddi, H. Safiri, J. Mehta, A. Jain, H. Choo, E. Zhang, Charles K. Sestok, C. Fernando, Rajagopal K. A., S. Ramakrishnan, V. Sinari, V. Baireddy	9.1 A 45nm CMOS RF-to-Bits LTE/WCDMA FDD/TDD 2×2 MIMO base-station transceiver SoC with 200MHz RF bandwidth.	ISSCC	2016	DBLP DOI BibTeX RDF
20	Bohdan Karpinskyy, Yongki Lee, Yunhyeok Choi, Yongsoo Kim, Mijung Noh, Sanghyun Lee	8.7 Physically unclonable function for secure key generation with a key error rate of 2E-38 in 45nm smart-card chips.	ISSCC	2016	DBLP DOI BibTeX RDF
20	Esther Kim, Deokgwan Jeong, Taehyoun Oh	A 4.1mA adaptive duty-cycle corrector loop with background calibration in 45nm CMOS process.	ISOCC	2016	DBLP DOI BibTeX RDF
20	Aritra Banerjee, Lei Ding 0001, Rahmi Hezar	High efficiency multi-mode outphasing RF power amplifier in 45nm CMOS.	ESSCIRC	2015	DBLP DOI BibTeX RDF
20	Ba-Ro-Saim Sung, Dong-Shin Jo, Il-Hoon Jang, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Ho-Jin Park, Seung-Tak Ryu	26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS.	ISSCC	2015	DBLP DOI BibTeX RDF
20	Chen Sun 0003, Mark T. Wade, Michael Georgas, Sen Lin, Luca Alloatti, Benjamin Moss, Rajesh Kumar, Amir Atabaki, Fabio Pavanello, Rajeev J. Ram, Milos A. Popovic, Vladimir Stojanovic	A 45nm SOI monolithic photonics chip-to-chip link with bit-statistics-based resonant microring thermal tuning.	VLSIC	2015	DBLP DOI BibTeX RDF
20	Byung-Jun Jang, Chan-Ho Lee, Sung-Hun Sim, Kyu-Won Choi, Do-Hun Byun, Yeon-Ho Jung, Ki-Man Park, Dong-Yeon Heo, Gyu-Hong Kim, Joon-Sung Yang	Robust via-programmable ROM design based on 45nm process considering process variation and enhancement Vmin and yield.	ISCAS	2015	DBLP DOI BibTeX RDF
20	Krishnendu Dhar	Design of a high speed, low power synchronously clocked NOR-based JK flip-flop using modified GDI technique in 45nm technology.	ICACCI	2014	DBLP DOI BibTeX RDF
20	T. Bhagya Laxmi, S. Rajendar, Y. Pandu Rangaiah	Performance analysis of alternative adder cell structures using clocked and non-clocked logic styles at 45nm technology.	ICACCI	2014	DBLP DOI BibTeX RDF
20	Vladimir Yutsis, Ismail Bustany, David G. Chinnery, Joseph R. Shinnerl, Wen-Hao Liu	ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement.	ISPD	2014	DBLP DOI BibTeX RDF
20	Deepanshu Dheer, Sagar Paliwal, Naved Ali, Mohammad Samar Ansari	A current-mode biquad filter for Zigbee applications using 45nm ±0.75V CMOS CDTA.	ISSPIT	2014	DBLP DOI BibTeX RDF
20	Aritra Banerjee, Rahmi Hezar, Lei Ding 0001, Nathan Schemm, Baher Haroun	A 29.5 dBm class-E outphasing RF power amplifier with performance enhancement circuits in 45nm CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
20	Yunsup Lee, Andrew Waterman, Rimas Avizienis, Henry Cook, Chen Sun 0003, Vladimir Stojanovic, Krste Asanovic	A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators.	ESSCIRC	2014	DBLP DOI BibTeX RDF
20	Yejoong Kim, Wanyeong Jung, Inhee Lee, Qing Dong 0001, Michael B. Henry, Dennis Sylvester, David T. Blaauw	27.8 A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications.	ISSCC	2014	DBLP DOI BibTeX RDF
20	Michael Georgas, Benjamin Moss, Chen Sun 0003, Jeffrey Shainline, Jason Orcutt, Mark T. Wade, Yu-Hsin Chen, Kareem Nammari, Jonathan C. Leu, Aravind Srinivasan, Rajeev J. Ram, Milos A. Popovic, Vladimir Stojanovic	A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process.	VLSIC	2014	DBLP DOI BibTeX RDF
20	Tarek A. Elarabi, Randa Ayoubi, Hanan A. Mahmoud, Magdy A. Bayoumi	Efficient 45nm ASIC Architecture for Full-Search Free Intra Prediction in Real-Time H.264/AVC Decoder.	J. Signal Process. Syst.	2013	DBLP DOI BibTeX RDF
20	Myunghwan Ryu, Youngmin Kim	A high resolution and high linearity 45nm CMOS fully digital voltage sensor for low power applications.	IEICE Electron. Express	2013	DBLP DOI BibTeX RDF
20	Sunghyun Park 0002, Masood Qazi, Li-Shiuan Peh, Anantha P. Chandrakasan	40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS.	DATE	2013	DBLP DOI BibTeX RDF
20	Andres Amaya, Francisco Villota, Guillermo Espinosa	A robust to PVT fully-differential amplifier in 45nm SOI-CMOS technology.	LASCAS	2013	DBLP DOI BibTeX RDF
20	Noël Deferm, Wouter Volkaerts, Juan F. Osorio, Anton de Graauw, Michiel Steyaert, Patrick Reynaert	A 120GHz fully integrated 10Gb/s wireless transmitter with on-chip antenna in 45nm low power CMOS.	ESSCIRC	2013	DBLP DOI BibTeX RDF
20	Yogesh Darwhekar, Evgeniy Braginskiy, Koby Levy, Abhishek Agrawal, Vikas Singh, Ronen Issac, Ofer Blonskey, Ofer Adler, Yoav Benkuzari, Matan Ben-Shachar, Srikanth Manian, Apu Sivadas, Subhashish Mukherjee, Gangadhar Burra, Nir Tal, Yariv Shlivinski, Guy Bitton, Sreekiran Samala	A 45nm CMOS near-field communication radio with 0.15A/m RX sensitivity and 4mA current consumption in card emulation mode.	ISSCC	2013	DBLP DOI BibTeX RDF
20	Weinan Gao, Bill Huff, Kendal Hess, Didier Coulibaly, Costantino Pala, Jiang Cao, Jaspreet Bhatia, Mikko Waltari, Lior Levin, Cyrille Cathelin, Thierry Nouvet, Nitin Nidhi, Rahul M. Kodkani, Ryuji Maeda, Damian Costa, Jason McFee, Reza Moazzam, Herve Vincent, Philippe Durieux	A digital single-wire multiswitch (DSWM) channel-stacking IC in 45nm CMOS for satellite outdoor units.	ISSCC	2013	DBLP DOI BibTeX RDF
20	Seongjong Kim, Inyong Kwon, David Fick, Myungbo Kim, Yen-Po Chen, Dennis Sylvester	Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS.	ISSCC	2013	DBLP DOI BibTeX RDF
20	Kin-Chu Ho, Po-Chao Fang, Hsiang-Pang Li, Cheng-Yuan Michael Wang, Hsie-Chia Chang	A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine.	ISSCC	2013	DBLP DOI BibTeX RDF