Search results for "ATM-switch"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
178	Jin Li, Chuan-lin Wu	A modular growth architecture for an ATM switch.	ICCCN	1995	DBLP DOI BibTeX RDF	modular growth architecture, growable ATM switch architecture, large scale ATM switch, switch size, nonuniform modular growth ATM switch, knockout switch, internal traffic, nonuniform concentration, connection pattern, performance, delay, throughput, telecommunication traffic
133	Jin Li, Chuan-lin Wu	A novel architecture for an ATM switch.	ICCD	1995	DBLP DOI BibTeX RDF	multicast function, shared-buffer ATM switch, first-in and first-out shared buffer, FIFO address queue, cell-loss performance, performance evaluation, asynchronous transfer mode, ATM switch, B-ISDN, control logic, buffer utilization
128	Jin Li	An output-shared buffer ATM switch.	ICCD	1996	DBLP DOI BibTeX RDF	buffer ATM switch, output-shared, lower bandwidth, asynchronous transfer mode, ATM switch, buffer utilization
123	Parimal Patel, Saad Zahid	Design Considerations in an ATM Switch Design.	ICCCN	1998	DBLP DOI BibTeX RDF	ATM switch design, packet switching, ATM Switch, Switch architecture
108	Jin Li, Chuan-lin Wu	Design and implementation of a multicast-buffer ATM switch.	ICNP	1995	DBLP DOI BibTeX RDF
105	Stephen Dempsey, Eric Fryland, Brian Hazzard, David Cyganski	Performance of Asynchronous, Variable Bit Rate Communications over ATM: A Comparison with FDDI.	LCN	1997	DBLP DOI BibTeX RDF	Classical IP, AAL 3/4, Performance, Real Time, ATM, TCP, Latency, WAN, LAN, UDP, FDDI
104	Chris Plate, Jack Tan	Performance Analysis of a Fault-Tolerant B-Tree ATM Switch.	LCN	1996	DBLP DOI BibTeX RDF	fault-tolerant B-tree ATM switch, ATM switching fabrics, buffering methods, simulation, performance analysis, asynchronous transfer mode, asynchronous transfer mode, routing algorithm, ATM networks, traffic models, multiplexing, real-time traffic, computer industry, telecommunications industry, data packets
101	Joseph Kee-Yin Ng, Shibin Song, Wei Zhao 0001	Integrated delay analysis of regulated ATM switch.	RTSS	1997	DBLP DOI BibTeX RDF	integrated delay analysis, regulated ATM switch, worst case delay, hard real-time connection, real-time connection traffic, arrival functions, priority driven scheduling, FIFO scheduling, admission probability, cell delay estimation, performance, asynchronous transfer mode, deadline, simulation experiments, service functions, piecewise linear functions
83	Sushil Aryal, James S. Meditch	Design of a large ATM switch with trunk grouping.	ICCCN	1995	DBLP DOI BibTeX RDF	load throughput value, dense VLSI implementation, large ATM switch with trunk grouping, LAST switch, IBSS, ideal bit by bit self routing switch, delay, topology, throughput, interconnections, communication complexity, modules, circuit complexity, cell loss
82	A. Sriram, Fadi J. Kurdahi	Behavioral Modeling of an ATM Switch using SpecCharts.	VLSI Design	1996	DBLP DOI BibTeX RDF
80	Robert R. Henry 0002	A multicast ATM switch with slotted ring fabric.	ICCCN	1997	DBLP DOI BibTeX RDF	multicast ATM switch, slotted ring fabric, slotted ring ATM switch architecture, optical fiber switch, deterministic performance analysis equations, delay performance, zero blocking performance, 150 Mbit/s, asynchronous transfer mode, switching fabric
79	Sreeranga P. Rajan, Masahiro Fujita, K. Yuan, Mike Tien-Chien Lee	ATM switch design by high-level modeling, formal verification and high-level synthesis.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	verification, synthesis, ATM switch, high-level design
79	Hea-Sook Park, Sung-Jin Moon, Man-Sik Park, Boseob Kwon, Kwang-Suk Song	Design of inter processor communication controller using ATM switch and analysis of its optimal message length considering retransmission.	RTCSA	1997	DBLP DOI BibTeX RDF	inter processor communication controller, optimal message length, distributed large-scale multiprocessors, ATM adaptation layer, message error rate, message retransmission rate, asynchronous transfer mode, ATM switch, asynchronous transfer mode switches
77	Edson L. Horta, Sergio Takeo Kofuji	A Run-Time Reconfigurable ATM Switch.	IPDPS	2002	DBLP DOI BibTeX RDF	Partial RTR, ATM Switch, Reconfigurable Logic
77	Steven E. Butner, David A. Skirmont	Architecture and design of a 40 gigabit per second ATM switch.	ICCD	1995	DBLP DOI BibTeX RDF	ATM links, buffering scheme, 40 Gbit/s, asynchronous transfer mode, multiprocessor interconnection networks, optical interconnections, ATM switch, optical communication, switch architecture
74	Sreeranga P. Rajan, Masahiro Fujita	Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design.	VLSI Design	1998	DBLP DOI BibTeX RDF	Modeling, Formal Verification, ATM, Validation, High-Level Synthesis, VHDL
70	Y. Chang, Nada Golmie, David H. Su	Study of interoperability between EFCI and ER switch mechanisms for ABR traffic in an ATM network.	ICCCN	1995	DBLP DOI BibTeX RDF	ABR traffic, rate-based flow control, transmission rate control, feedback information, resource management cells, network switching nodes, ATM Forum Traffic Management Specification, network switch mechanism, ATM switch vendor, bandwidth allocation fairness, explicit forward congestion indication, explicit rate mechanism, end system behavior, congestion notification, algorithms, interoperability, asynchronous transfer mode, asynchronous transfer mode, ATM network, simulation results, network performance, simulation study, performance characteristics, available bit rate, destination nodes
70	Youngbok Choi, Hideki Tode, Hiromi Okada, Hiromasa Ikeda	A Large Capacity Photonic ATM Switch for Wavelength Division Multiplexing Networks.	ICCCN	1995	DBLP DOI BibTeX RDF	Electronic Control, WDM Optical Buffer, ATM Switching, WDM Optical Networks, Photonic Switch
69	Pierre Plaza, Luis A. Merayo, Juan Carlos Diaz, José Luis Conesa	A 2.5 Gb/s ATM switch chip set.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
69	Greg Minshall, Robert M. Hinden, Eric Hoffman, FongChing Liaw, Thomas L. Lyon, Peter Newman	Flow labelled IP over ATM: design and rationale.	Comput. Commun. Rev.	2006	DBLP DOI BibTeX RDF	GSMP, IFMP, IP switching, flow labelled IP, ipsilon, ATM, IP
65	Syed Sohel Hussain, Yih-Chyun Jenq	Analysis and Optimization of a Banyan-Based ATM Switch by Simulations.	LCN	1996	DBLP DOI BibTeX RDF	Banyan based ATM switch, switch optimization, switch analysis, delay variance, performanc analysis, uniform traffic, three-state model, nonblocking first stage, packet blocking, enhanced priority scheme, single buffer Banyan network, double buffer switching element, delay sensitive voice packet, asynchronous transfer mode, asynchronous transfer mode, delay, throughput, bandwidth, simulation results, voice traffic, data traffic
64	Byoung-Seok Park, Sung-Chun Kim	Design and Analysis of a New Fast Packet Switching Fabric Supporting Multimedia Traffic.	LCN	1996	DBLP DOI BibTeX RDF	fast packet switching fabric, ATM switch architecture, output queueing, switch analysis, FAB Banyan switching fabrics, Batcher sorter, double shuffle network, packet distributors, FAB networks, output buffer modules, compressed video data, performance evaluation, throughput, packet switching, hardware implementation, voice, multimedia traffic, packet delay, switch design, packet loss probability, text data
63	Joseph Kee-Yin Ng, Ge Nong	Multimedia applications on FDDI networks connected by an ATM switch.	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	high-speed local area network, internetwork multimedia applications, ATM switch interconnected networks, asynchronous transfer mode, video, local area networks, images, audio, graphics, digital simulation, multimedia communication, multimedia applications, text, ATM switch, data transfer, FDDI, broadband networks, B-ISDN, B-ISDN, simulation experiments, LAN interconnection, FDDI networks, network parameters
63	Aditya Agrawal, Magdy A. Bayoumi, Amr Elchouemi	A new ATM congestion control scheme for shared buffer switch architectures.	ICCCN	1995	DBLP DOI BibTeX RDF	pre-emptive congestion control scheme, shared buffer switch architectures, rate-based feedback scheme, guaranteed service traffic, continuous bit-rate traffic, leaky bucket mechanism, backward explicit congestion notification feedback scheme, mean inter-arrival time, buffer threshold throttle factor, cell reject throttle factor, rate reduction delta, transient behaviour, filter time, asynchronous transfer mode, ATM networks, simulation model, ATM switch, dynamic bandwidth allocation, best-effort traffic, variable bit-rate traffic, predictive scheme
63	Gerd Keiser, David Freeman, Carrie Carter	ATM test traffic generation algorithms.	ICCCN	1995	DBLP DOI BibTeX RDF	ATM test traffic generation algorithms, ATM traffic analyzer, user-selectable statistical distribution, ATM network performance, ATM switch performance, cell delay, cell error, variable-bit-rate traffic patterns, constant-bit-rate traffic patterns, asynchronous transfer mode, asynchronous transfer mode, performance metrics, video traffic, voice traffic, cell loss, data traffic
62	Seow S. Lim, Yoke K. Pang, H. S. Cheng, Yeow M. Loh	An ATM Network Test Bench over a C-Band Satellite System.	SAINT Workshops	2003	DBLP DOI BibTeX RDF
61	Ge Nong, Jogesh K. Muppala, Mounir Hamdi	A Performance Model for ATM Switches with Multiple Input Queues.	ICCCN	1997	DBLP DOI BibTeX RDF	performance evaluation, analytical modeling, computer simulation, ATM switch
60	Qin Zheng	An Enhanced Timed-Round-Robin Traffic Control Scheme for ATM Networks.	LCN	1996	DBLP DOI BibTeX RDF	timed round robin traffic control, guaranteed bandwidth, dynamic bandwidth sharing, bursty data traffic, integrated digital networks, cell transmission scheduling algorithm, feedback flow control, link bandwidth, ATM switch design, asynchronous transfer mode, asynchronous transfer mode, ATM networks, real-time communications, switch architectures
60	Apostolos Dollas, Nikolaos Aslanides, Stamatios Kavvadias, Euripides Sotiriades, Kyprianos Papademetriou, Dionisios N. Pnevmatikatos	Rapid Prototyping of a Reusable 4x4 Active ATM Switch Core with the PCI Pamette.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF	design core, reconfigurable computing, rapid prototyping, Active networks, ATM switch
60	Sofiène Tahar, Zijian Zhou 0001, Xiaoyu Song, Eduard Cerny, Michel Langevin	Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	ATM Switch Fabric, Safety Property Checking, Abstract State Machines, Hardware Verification, Multiway Decision Graphs
60	Joan García-Haro, Rocío Marín-Sillué, José Luis Melús-Moreno	ATMSWSIM An Efficient, Portable and Expandable ATM SWitch SIMulator Tool.	Computer Performance Evaluation	1994	DBLP DOI BibTeX RDF
58	George Kornaros, Christoforos E. Kozyrakis, Panagiota Vatsolaki, Manolis Katevenis	Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control.	ARVLSI	1997	DBLP DOI BibTeX RDF	single-chip ATM switch, VLSI router, pipelined queue management, credit-based flow control
55	Sema F. Oktug	A Multicast ATM Switch Based on PIPN.	ICN (2)	2001	DBLP DOI BibTeX RDF
54	Byoung Seob Park, Sung Chun Kim	FBSF: a new fast packet switching fabric based-on multistage interconnection network with multiple outlets.	ISPAN	1996	DBLP DOI BibTeX RDF	packet switching fabric, FBSF, multiple outlets, ATM switch architecture, FAB Banyan Switching Fabrics, Batcher sorter, radix-r double shuffle network, r-packet distributors, parallel architectures, packet switching, multistage interconnection networks, multistage interconnection network, switch fabrics
53	Victor C. S. Lee, Joseph Kee-Yin Ng, Kam-yiu Lam, Sheung-lun Hung	Performance Studies of Transmitting Real-Time MPEG-I Video in ATM Networks.	LCN	1996	DBLP DOI BibTeX RDF	real-time MPEG-I video, real video programmes, workload characteristics, cell miss ratio, deadline missing, burst loss ratio, first-come-first-serve scheduling algorithm, virtual path bandwidth, simulation, asynchronous transfer mode, ATM networks, buffer overflow, ATM switch, gateways, performance studies, video data, video clips, cell loss ratio
53	Chie Dou, Ming-Der Shieh	A CAM-Based VLSI Architecture for Shared Buffer ATM Switch with Fuzzy Controlled Buffer Management.	ICCD	1996	DBLP DOI BibTeX RDF	Shared Buffer ATM Switch, VLSI, Fuzzy Control, Buffer Management, CAM
53	Robert Chen-Hao Chang, Lung-Chih Kuo, Chih-Yuan Hsieh	VLSI implementation of a multicast ATM switch.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
53	Derek C. W. Pao, W. N. Chau	Design of ATM switch using hypercube with distributed shared input buffers and dedicated output buffers.	ICNP	1995	DBLP DOI BibTeX RDF
53	Magnus Karlsson 0002, Per Stenström	Performance Evaluation of a Cluster-Based Multiprocessor Built from ATM Switches and Bus-Based Multiprocessor Servers.	HPCA	1996	DBLP DOI BibTeX RDF
53	Mengjou Lin, Jenwei Hsieh, David Hung-Chang Du, Joseph P. Thomas, James A. MacDonald	Distributed network computing over local ATM networks.	SC	1994	DBLP DOI BibTeX RDF	distributed network computing, Asynchronous Transfer Mode, performance measurement, application programming interface
52	Hea-Sook Park, Sung-Jin Moon, Man-Sik Park, Boseob Kwon, Kwang-Suk Song	The Design of Reliable Controller for Interprocessor Communication Network Using ATM Switch.	HICSS (3)	1998	DBLP DOI BibTeX RDF
52	Manolis Katevenis, Panagiota Vatsolaki, Dimitrios N. Serpanos, Evangelos P. Markatos	ATLAS: A Single-Chip ATM Switch for NOWs.	CANPC	1997	DBLP DOI BibTeX RDF
51	Carlos Roberto dos Santos, Shusaburo Motoyama	A QoS Provisioned CIOQ ATM Switch with m Internal Links.	ICT	2004	DBLP DOI BibTeX RDF
51	Rajgopal Kannan, Sibabrata Ray	A Fair and Efficient Multicast ATM Switch based on Deflection Routing.	ISCC	2000	DBLP DOI BibTeX RDF	Multicasting, ATM Networks, Deflection Routing
50	Allyn Romanow, Sally Floyd	Dynamics of TCP Traffic Over ATM Networks.	SIGCOMM	1994	DBLP DOI BibTeX RDF
50	Haralambos Laskaridis, Georgios I. Papadimitriou, Andreas S. Pomportsis	Applying Optical Reconfiguration on ATM Switch Fabrics.	IPDPS	2003	DBLP DOI BibTeX RDF	ATM, reconfiguration, correlation, switch fabric
48	Sofiène Tahar, Xiaoyu Song, Eduard Cerny, Zijian Zhou 0001, Michel Langevin, Otmane Aït Mohamed	Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
48	Moustafa A. Youssef 0001, Mohamed N. El-Derini, Hussein H. Aly	Structure and Performance Evaluation of a Replicated Banyan Network Based ATM Switch.	ISCC	1999	DBLP DOI BibTeX RDF	replicated networks, ATM switching, banyan networks
48	Mike Parks	A Modular Element for Shared Buffer ATM Switch Fabrics.	ASAP	1997	DBLP DOI BibTeX RDF
48	Hasan Cam	LAN-ATM Internetworking over a Priority-Based Slotted-Ring Network.	LCN	1997	DBLP DOI BibTeX RDF
47	Abhijit M. Lele, S. K. Nandy 0001	Architecture of Reconfigurable a Low Power Gigabit AT Switch.	VLSI Design	2001	DBLP DOI BibTeX RDF
47	Terry Bearly, Jagan P. Agrawal	A split input sunshine switch architecture.	IPCCC	1999	DBLP DOI BibTeX RDF
46	Hideaki Yamashita	Discrete-time analysis of a classified multi-server queue with burst arrivals and a shared buffer.	Queueing Syst. Theory Appl.	1994	DBLP DOI BibTeX RDF	burst arrival, Markov chain, ATM switch, Discrete-time queue, shared buffer
46	Sandeep Agarwal, Fayez El Guibaly	Modeling of Shift Register-based ATM Switch.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF
46	Jaesup Lee, Kyou-Ho Lee, Jong Hyup Lee, Jin-Ho Hahm, Young Sun Kim	Design and Analysis of MPLS-based ATM Switching System for Differentiated Services.	ISCC	2003	DBLP DOI BibTeX RDF
45	Lotfi Benmohamed, Joseph G. Kneuer, Murali S. Kodialam, Yung-Terng Wang	Connection Admission Control for the Real-Time VBR Service in an ATM Switch with per-VC Queueing.	ISCC	2001	DBLP DOI BibTeX RDF
41	Samir Chatterjee, Wen Xiao	Selective discarding with FEC for ATM-based internetwork.	LCN	1997	DBLP DOI BibTeX RDF	selective discarding, ATM based internetworks, flow control systems, retransmission based schemes, ARQ based closed loop techniques, time sensitive information, interactive web, redundant information, fragmentation effects, legacy networks, buffer management techniques, block loss rates, gatekeeping operation, janitor routine, ATM switch buffers, no loss transport, CSCW, asynchronous transfer mode, FEC, forward error correction, simulation study, videophones, real time information
41	Jae-Hyun Park, Hyunsoo Yoon, Heung-Kyu Lee	The deflection self-routing Banyan network: a large-scale ATM switch using the fully adaptive self-routing and its performance analyses.	IEEE/ACM Trans. Netw.	1999	DBLP DOI BibTeX RDF	algecraic formalism, deflection self-routing Banyan network, unbuffered Banyan network, performance evaluation, ATM switch, topological properties
41	Feihong Chen, Bülent Yener, Ali N. Akansu, Sirin Tekinay	A Novel Performance Analysis for the Copy Network in a Multicast ATM Switch.	ICCCN	1998	DBLP DOI BibTeX RDF	Copy Network, Multicast, ATM switch
41	Keun-Bae Kim, Hyup Jong Kim	Back-Pressure Buffering Scheme to Improve the Cell Loss Property on the Output Buffered ATM Switch.	LCN	1996	DBLP DOI BibTeX RDF	back-pressure buffering, cell loss property, output buffered ATM switch, input cells, push-out mechanism, selective pressure mechanism, small sized memory, asynchronous transfer mode, shared memory, queueing theory, simulation results, computer simulation, performance comparison, FIFO, switch fabric, output buffer
41	Muh-ong Yang, GinKou Ma	Universal Packet Time Slot - A New Paradigm of Designing an ATM Switch.	LCN	1996	DBLP DOI BibTeX RDF	universal packet time slot, ATM switch design, high speed packet switching, transmission speed, lightwave technology, electronic switching device, FDM, frequency division multiplexing, bit-sliced techniques, output contention, ATM cells, asynchronous transfer mode, bandwidth, time division multiplexing, transmission line, hardware complexity, TDM, processing speed
41	Derek Chi-Wai Pao, S. C. Leung	Sharing Buffer in an Input-Output Buffered ATM Switch without Scaling up Memory Bandwidth Requirement.	ICCCN	1995	DBLP DOI BibTeX RDF	cells recirculation, ATM switch, shared buffer
41	Aditya Agrawal, Anand Raju, Sachidanand Varadarajan, Magdy A. Bayoumi	A scalable shared buffer ATM switch architecture.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	electronic switching systems, field effect transistor switches, scalable shared buffer ATM switch architecture, memory bandwidth requirement, maximum crosspoint switch size, buffer memory size, access time reduction, multiple buffer memories, 8/spl times/8 switch, 1 mum, 622 Mbit/s, asynchronous transfer mode, asynchronous transfer mode, shared memory systems, buffer storage, CMOS technology, CMOS digital integrated circuits, B-ISDN, B-ISDN, switching circuits, parallel access
41	Mohamed Escheikh, Kamel Barkaoui, Ammar Bouallegue	Performance Analysis of an N(N ATM Switch with Markov Modulated Poisson Process under Back-Pressure Mechanism.	MASCOTS	2000	DBLP DOI BibTeX RDF
41	Byungho Kim, Boseob Kwon, Jinchun Kim, Hyunsoo Yoon, Jung Wan Cho	Performance analysis of an ATM switch with multiple paths.	ICNP	1995	DBLP DOI BibTeX RDF
41	Masato Oguchi, Takahiko Shintani, Takayuki Tamura, Masaru Kitsuregawa	Optimizing Protocol Parameters to Large Scale PC Cluster and Evaluation of its Effectiveness with Parallel Data Mining.	HPDC	1998	DBLP DOI BibTeX RDF	TCP retransmission, data mining, parallel processing, ATM network, PC cluster
41	Moon-Kyun Oh, Dae Young Kim, Sung-Woong Ra, Chi-Moon Han, Han-Kyung Kim	A Study on Point-to-Multipoint Connection Control in ATM Switching System.	LCN	1996	DBLP DOI BibTeX RDF	point-to-multipoint connection control, ATM switching system, ATM switching nodes, distributed ATM switching system, burst traffic, cell replication function, broadcasting, asynchronous transfer mode, asynchronous transfer mode, ATM network, real time processing, dynamic bandwidth allocation, B-ISDN, signaling protocol, distribution services, multicasting services, ITU-T
39	Erol Basturk, Alexander Birman, G. Delp, Roch Guérin, R. Haas, Sanjay Kamat, Dilip D. Kandlur, P. Pan, Dimitrios E. Pendarakis, Vinod G. J. Peris, Raju Rajan, Debanjan Saha, Doug Williams	Design and implementation of a QoS capable switch-router.	ICCCN	1997	DBLP DOI BibTeX RDF	QoS capable switch-router, core ATM switch fabric, intelligent adapters, RSVP signalling, prototype network, UNIX hosts, network performance measurements, Internet, Internet, design, architecture, resource management, implementation, service differentiation, high throughput, IETF, control engine
39	Pertti Raatikainen, Teleste Oy, Juha Zidbeck	Performance Comparison of Experimented Switching Architectures for ATM.	EUROMICRO	1996	DBLP DOI BibTeX RDF	broadband switching, transfer delay performance, Frame Synchronized Ring, switch structures, multidrop bus, multistage banyan network, interconnection networks, ATM, multiprocessor interconnection networks, ATM-switch, crossbar
36	Hyunseung Choo, Youngsong Mun	Improving the Performance of Multistage Interconnection Networks under Nonuniform Traffic Pattern on Shorter Cycles.	International Conference on Computational Science	2003	DBLP DOI BibTeX RDF
36	Mohsen Guizani, Ala I. Al-Fuqaha	New Queuing Strategy for Large Scale ATM Switches.	Annual Simulation Symposium	2001	DBLP DOI BibTeX RDF
36	Yoon-Hwa Choi, Pong-Gyou Lee	Concurrent Error Detection and Fault Location in a Fast ATM Switch.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
34	Young Wook Keum, Sung Chun Kim	Design and Analysis of the High-Performance Interconnected Banyan Switching Fabric(IBSF).	ISPAN	1996	DBLP DOI BibTeX RDF	parallel processing, MIN, ATM switch, banyan network
34	Mohsen Guizani	Design and analysis of all-optical ATM switching elements for high speed networks.	LCN	1995	DBLP DOI BibTeX RDF	optical logic, ATM switching elements, all-optical ATM switch, asynchronous transfer mode, high speed networks, optical switches, switching circuits
34	Slobodan S. Petrovic	ABR Service in ATM Networks: Performance Comparison Between BECN and Adaptive Stochastic Congestion Control Schemes with Guaranteed Minimum Cell Rate.	Multimedia Information Systems	1998	DBLP DOI BibTeX RDF
34	Paul Shipley, Sherif Sayed, Magdy A. Bayoumi	A High Speed VLSI Architecture for Scaleable ATM Switches.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
33	Daniel Won-Kyu Hong, Choong Seon Hong, Dong-Sik Yun	A Configuration Algorithm for Provisioning of Cell-Based MPLS Network.	International Conference on Computational Science	2003	DBLP DOI BibTeX RDF
33	Shibin Song, Joseph Kee-Yin Ng, Bihai Tang	Efficient Delay Computation Methods for an ATM Network with Real-Time Video Traffic.	RTSS	1999	DBLP DOI BibTeX RDF	Real-Time ATM Networks, Worst Case Delay Analysis, Efficient Delay Computation, Performance Evaluation
33	Jonathan S. Turner	Extending ATM Networks for Efficient Reliable Multicast.	CANPC	1997	DBLP DOI BibTeX RDF
31	Mayez A. Al-Mouhamed, Mohammad Kaleemuddin	Evaluation of Pipelined Banyan Switch Architectures for ATM Networks.	ISCC	1999	DBLP DOI BibTeX RDF
31	Shibin Song, Joseph Kee-Yin Ng, Bihai Tang	On the Self-Similarity Property of the Output Process from a Network Server with Self-Similar Input Traffic.	RTCSA	1999	DBLP DOI BibTeX RDF	Real-Time ATM Networks, Performance Evaluation, Self-similar Traffic
31	Young-Wook Cha, Jong-Oh Kim, Kyou-Ho Lee, Ki Jun Han	Multiaccess ATM Network for Residential and Small Business Subscribers.	LCN	1996	DBLP DOI BibTeX RDF	OAM reference model, small business subscribers, residential subscribers, shared medium-based multiaccess technology, switch port granularity, multiaccess ATM customer network, asynchronous transfer mode, switches, network architecture, connection management, connection control
31	Euripides Zervanos, Georgios I. Stassinopoulos	Design and Implementation of an ABR Server in a Shared-Bus ATM Switch.	ISCC	2000	DBLP DOI BibTeX RDF	Networks, ATM, Switching, ABR
31	Masahiro Fujita, Sreeranga P. Rajan, Alan J. Hu	Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol.	FM-Trends	1998	DBLP DOI BibTeX RDF
31	Jean-Michel Fourneau, Lynda Mokdad, Nihal Pekergin	Bounding the Loss Rates in a Multistage ATM Switch.	Computer Performance Evaluation	1997	DBLP DOI BibTeX RDF
31	Arthur Y. M. Lin, John A. Silvester	Queueing Analysis of an ATM Switch with Multichannel Transmission Groups.	SIGMETRICS	1990	DBLP DOI BibTeX RDF
29	Youngsong Mun, Hyunseung Choo	Modeling and Performance Evaluation of Multistage Interconnection Networks with Nonuniform Traffic Pattern.	International Conference on Computational Science (3)	2002	DBLP DOI BibTeX RDF
29	Debashis Basak, Abhijit K. Choudhury, Ellen L. Hahne	Sharing memory in multistage ATM switches.	ICCCN	1995	DBLP DOI BibTeX RDF	multistage ATM switches, shared-memory switching elements, banyan topology, output queueing, local cell buffer memory, buffer management technique, delayed pushout, backpressure mechanism, telecommunication traffic, bursty traffic, load conditions
29	Manolis Katevenis, Dimitrios N. Serpanos, Emmanuel Spyridakis	Credit-Flow-Controlled ATM for MP Interconnection: The ATLAS I Single-Chip ATM Switch.	HPCA	1998	DBLP DOI BibTeX RDF
29	H. Jonathan Chao, Necdet Uzun	An ATM routing and concentration chip for a scalable multicast ATM switch.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
29	Kouichi Genda, Naoaki Yamanaka	TORUS: Terabit-per-Second ATM Switching System Architecture Based on Distributed Internal Speed-Up ATM Switch.	IEEE J. Sel. Areas Commun.	1997	DBLP DOI BibTeX RDF
29	Malathi Veeraraghavan, Pramod Pancha, Gopal Dommety	Connectionless ATM Using an ATM Switch Router.	ECMAST	1997	DBLP DOI BibTeX RDF
29	David M. Drury	ATM Traffic Management and the Impact of ATM Switch Design.	Comput. Networks ISDN Syst.	1996	DBLP DOI BibTeX RDF
28	Haralambos Laskaridis, Andreas A. Veglis, Andreas S. Pombortsis	Grid-Based ATM Switch Architecture: A New Minimalistic Switch Fabric.	Applied Informatics	1999	DBLP BibTeX RDF
28	Daniel Weil, Alain Botta, Alain Chemarin, Philippe Gallay, Jacques Majos, Michel Servel	A 16×622 Mb/s ATM switch: PRELUDE switch architecture integrated into a 6-million transistor monochip.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
28	H. Jonathan Chao, Byeong-Seog Choe, Jin-Soo Park, Necdet Uzun	Design and Implementation of Abacus Switch: A Scalable Multicast ATM Switch.	IEEE J. Sel. Areas Commun.	1997	DBLP DOI BibTeX RDF
28	Christos Kolias, Leonard Kleinrock	The Dual-Banyan (DB) Switch: A High-Performance Buffered-Banyan ATM Switch.	ICC (2)	1997	DBLP DOI BibTeX RDF
28	Robert J. Simcoe, Tong-Bi Pei	Perspectives on ATM switch architecture and the influence of traffic pattern assumptions on switch design.	Comput. Commun. Rev.	1995	DBLP DOI BibTeX RDF
28	Hyong S. Kim	Design and performance of Multinet switch a multistage ATM switch architecture with partially shared buffers.	IEEE/ACM Trans. Netw.	1994	DBLP DOI BibTeX RDF
28	Indra Widjaja, Alberto Leon-Garcia	The helical switch: a multipath ATM switch which preserves cell sequence.	IEEE Trans. Commun.	1994	DBLP DOI BibTeX RDF