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Found 418 publication records. Showing 418 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
82Arash Reyhani-Masoleh A New Bit-Serial Architecture for Field Multiplication Using Polynomial Bases. Search on Bibsonomy CHES The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Finite or Galois field, Mastrovito multiplier, polynomial basis, bit-serial multiplier
67Soonhak Kwon, Heuisu Ryu Efficient Bit Serial Multiplication Using Optimal Normal Bases of Type II in GF (2m). Search on Bibsonomy ISC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF bit serial multiplication, optimal normal basis of type II, Finite field, dual basis
64Dan Cyca, Laurence E. Turner Bit-Serial Digital Filter Implementation using a Custom C Compiler. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
62Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor FPGA-Based Structures for On-Line FFT and DCT. Search on Bibsonomy FCCM The full citation details ... 1999 DBLP  DOI  BibTeX  RDF FPGA, interconnect, MAC, FFT, signal processing, DCT, online, on-line, distributed arithmetic, bit-serial, xilinx, on-line arithmetic
62Leilei Song, Keshab K. Parhi Efficient Finite Field Serial/Parallel Multiplication. Search on Bibsonomy ASAP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF finite field serial/parallel multiplication, finite field arithmetic architectures, bit-serial/parallel finite field multiplier, standard basis representation, optimal primitive polynomials, minimum hardware complexity, semi-systolic architecture, computational complexity, cryptography, cryptography, encoding, digital arithmetic, polynomials, multiplying circuits, VLSI implementation, coding theory
58Yong Ho Hwang, Sang Gyoo Sim, Pil Joong Lee Bit-Serial Multipliers for Exponentiation and Division in GF(2m) Using Irreducible AOP. Search on Bibsonomy ICCSA (1) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Irreducible AOP, Finite field, Exponentiation, Bit-serial multiplier
58Johann Großschädl A Bit-Serial Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m). Search on Bibsonomy CHES The full citation details ... 2001 DBLP  DOI  BibTeX  RDF iterative modulo multiplication, polynomial basis representation, bit-serial multiplier architecture, smart card crypto-coprocessor, Elliptic curve cryptography, finite field arithmetic
58S. A. Rahim, Laurence E. Turner A Field Programmable Bit-Serial Digital Signal Processor. Search on Bibsonomy IWSOC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
56Priyadarsan Patra, Donald S. Fussell Fully asynchronous, robust, high-throughput arithmetic structures. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF fully asynchronous structures, high-throughput arithmetic structures, bit serial adders, scaleability, VLSI, digital arithmetic, asynchronous circuits, adders, integrated logic circuits, multiplying circuits, RSA cryptosystems, delay-insensitive, bit serial multipliers
55Akihisa Ohta, Tsuyoshi Isshiki, Hiroaki Kunieda New FPGA Architecture for Bit-Serial Pipeline Datapath. Search on Bibsonomy FCCM The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
52Gert Cauwenberghs Bit-serial bidirectional A/D/A conversio. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF digital-analogue conversion, bidirectional bit-serial convertor, algorithmic DAC conversion, successive approximation ADC, D/A conversion, fault-tolerant VLSI architecture, matched monotonic characteristics, 200 muW, 20 mus, VLSI, CMOS integrated circuits, analogue-digital conversion, integrated circuit reliability, A/D conversion, 2 micron, CMOS process
52S. M. Mortazavi Zanjani, Somayyeh Rahimian Omam, Seid Mehdi Fakhraie, Omid Shoaei Experimental Evaluation of Different Realizations of Recursive CIC Filters. Search on Bibsonomy CCECE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
52Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang A bit-serial approximate min-sum LDPC decoder and FPGA implementation. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
52Alex Carreira, Trevor W. Fox, Laurence E. Turner A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBitsTM. Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
50Florian Dittmann 0001, Achim Rettberg, Raphael Weber Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture. Search on Bibsonomy SBCCI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF optimization, high-level synthesis, bit-serial architecture
50Soonhak Kwon, Heuisu Ryu Efficient Bit Serial Multiplication in GF(2m) for a Class of Finite Fields. Search on Bibsonomy ICOIN The full citation details ... 2003 DBLP  DOI  BibTeX  RDF bit serial multiplication, optimal normal basis of type II, Finite field, dual basis, all one polynomial
49Richard C. North, Walter H. Ku beta-bit serial/parallel multipliers. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
46Makoto Motegi, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi 0001 Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis. Search on Bibsonomy PPSN The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
44Brian M. H. Li, Philip Heng Wai Leong Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF FPGA, motion estimation, video compression, bit serial, systolic
44Jae-Jin Lee, Gi-Yong Song Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
43Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann 0001, Christophe Bobda A New Approach of a Self-Timed Bit-Serial Synchronous Pipeline Architecture. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
43Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. Search on Bibsonomy IOLTW The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
43Tsuyoshi Isshiki, Akihisa Ohta, T. Watanabe, T. Nakada, K. Akahane, I. Sisla, Dongju Li, Hiroaki Kunieda High density bit-serial FPGA with LUT embedding shift register function. Search on Bibsonomy APCCAS (1) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
43Richard I. Hartley, Jeffrey R. Jasica Behavioral to structural translation in a bit-serial silicon compiler. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
41R. S. Hogg, W. I. Hughes, David W. Lloyd A Novel Asynchronous ALU for Massively Parallel Architectures. Search on Bibsonomy PDP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF novel asynchronous ALU, self timed asynchronous bit serial massively parallel architecture, fixed word length, small magnitude data, self timed communication techniques, self timed single instruction systolic array, ST-SISA, self timed delay insensitive techniques, parallel architectures, systolic arrays, asynchronous circuits, clock skew, massively parallel architectures, clocked control, arithmetic logic unit
41Mohammad Reza Hosseiny Fatemi, Hasan F. Ates, Rosli Salleh A Cost-Efficient Bit-Serial Architecture for Sub-pixel Motion Estimation of H.264/AVC. Search on Bibsonomy IIH-MSP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Sub-pixel Motion estimation, VLSI, Video Compression, Bit-serial Architecture
41Heiner Giefers, Achim Rettberg Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture. Search on Bibsonomy SBCCI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF high-level synthesis, low power design, voltage scaling, bit-serial architecture
41Bing Bing Zhou A New Bit-Serial Systolic Multiplier Over GF(2m). Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1988 DBLP  DOI  BibTeX  RDF bit-serial systolic multiplier, VLSI, logic design, cellular arrays, linear systolic array
41In-Shek Hsu, Irving S. Reed, Trieu-Kien Truong, Ke Wang, Chiunn-Shyong Ye, Leslie J. Deutsch The VLSI Implementation of a Reed-Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1984 DBLP  DOI  BibTeX  RDF Berlekamp's bit-serial multiplier, VLSI, trace, Reed-Solomon code, dual basis
41Kenneth E. Batcher Bit-Serial Parallel Processing Systems. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1982 DBLP  DOI  BibTeX  RDF radar processing, Airborne processors, bit-serial processors, custom VLSI chips, multidimensional access, image processing, parallel processors
41Yun-Chen Lo, Ren-Shuo Liu Bit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference. Search on Bibsonomy DAC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
40Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong A systolic multiplier with LSB first algorithm over GF(2m) which is as efficient as the one with MSB first algorithm. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
37Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. Search on Bibsonomy ASYNC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
35Ocean Y. H. Cheung, Kuen Hung Tsoi, Philip Heng Wai Leong, Monk-Ping Leong Tradeoffs in Parallel and Serial Implementations of the International Data Encryption Algorithm IDEA. Search on Bibsonomy CHES The full citation details ... 2001 DBLP  DOI  BibTeX  RDF performance-tradeoffs, reconfigurable-computing, digital-design, Cryptographic hardware
35Florian Dittmann 0001, Achim Rettberg, Raphael Weber Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture. Search on Bibsonomy EUC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
35Kiyoshi Oguri, Yuichiro Shibata, Akira Nagoya Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
35Chang Hoon Kim, Soonhak Kwon, Chun Pyo Hong, In-Gil Nam Efficient bit-serial systolic array for division over GF(2m). Search on Bibsonomy ISCAS (2) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
35Soonhak Kwon Low Complexity Bit Serial Systolic Multipliers over GF(2m) for Three Classes of Finite Fields. Search on Bibsonomy ICICS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF systolic multiplier, finite field, basis, all one polynomial
35Johann Großschädl A low-power bit-serial multiplier for finite fields GF(2m). Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
35Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos On Accumulator-Based Bit-Serial Test Response Compaction Schemes. Search on Bibsonomy ISQED The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
35Monk-Ping Leong, Ocean Y. H. Cheung, Kuen Hung Tsoi, Philip Heng Wai Leong A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA. Search on Bibsonomy FCCM The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
35Katsuharu Suzuki, Michael X. Wang, Zhao Fang, Wayne Wei-Ming Dai Design of C++ Class Library and Bit-Serial Compiler for Variable-Precision Datapath Synthesis on Adaptive Computing Systems. Search on Bibsonomy FCCM The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
34Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny Fast Asynchronous Shift Register for Bit-Serial Communication. Search on Bibsonomy ASYNC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Sorin Cotofana, Stamatis Vassiliadis delta-Bit serial binary addition with linear threshold networks. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
34R. Gnanasekaran On a Bit-Serial Input and Bit-Serial Output Multiplier. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1983 DBLP  DOI  BibTeX  RDF two's complement number representation, Add-shift multiplier, bit-sequential multiplier, on-line multiplication, carry-save addition
33Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph. Search on Bibsonomy ISVLSI The full citation details ... 2002 DBLP  DOI  BibTeX  RDF FPGA, Reconfigurable processor, Two-dimensional array, Bit-serial architecture
33Ross Smith, Karl Fant, Dave Parker, Rick Stephani, Ching-Yi Wang An Asynchronous 2-D Discrete Cosine Transform Chip. Search on Bibsonomy ASYNC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF DCT, asynchronous, threshold logic, bit-serial
33R. S. Hogg, David W. Lloyd, W. I. Hughes Self-Timed Communication Strategies for Massively Parallel Systolic Architectures. Search on Bibsonomy CONPAR The full citation details ... 1994 DBLP  DOI  BibTeX  RDF Scalable, Elastic, Massively-Parallel, Self-timing, Bit-serial
33Hussein M. Alnuweiri, Viktor K. Prasanna Fast Image Labeling Using Local Operators on Mesh-Connected Computers. Search on Bibsonomy IEEE Trans. Pattern Anal. Mach. Intell. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF bit-serial processors, local operators, asymptotic time complexity, very fast shift registers, parallel algorithm, parallel algorithms, computational complexity, computational complexity, parallel architectures, parallel architectures, computerised picture processing, computerised picture processing, stacks, communication links, mesh-connected computers, image labeling
30Siqi He, Hongyi Zhang, Mengjie Li, Haozhe Zhu, Chixiao Chen, Qi Liu 0010, Xiaoyang Zeng Bit-Offsetter: A Bit-serial DNN Accelerator with Weight-offset MAC for Bit-wise Sparsity Exploitation. Search on Bibsonomy AICAS The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
30Sora Isobe, Yoichi Tomioka Low-bit Quantized CNN Acceleration based on Bit-serial Dot Product Unit with Zero-bit Skip. Search on Bibsonomy CANDAR The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
29Victor Y. Pan, John H. Reif On the Bit-Complexity of Discrete Solutions of PDEs: Compact Multigrid. Search on Bibsonomy ICALP The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
29Zih-Heng Chen, Ming-Haw Jing, Jian-Hong Chen, Yaotsu Chang New viewpoint of bit-serial/parallel normal basis multipliers using irreducible all-one polynomial. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
27Miguel Morales-Sandoval, Claudia Feregrino Uribe, Paraskevas Kitsos Bit-serial and digit-serial GF(2m)Montgomery multipliers using linear feedback shift registers. Search on Bibsonomy IET Comput. Digit. Tech. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
27Paraskevas Kalivas, Kiamal Z. Pekmestzi, Paul Bougas, Andreas Tsirikos, Kostas Gotsis Low-latency and high-efficiency bit serial-serial multipliers. Search on Bibsonomy EUSIPCO The full citation details ... 2004 DBLP  BibTeX  RDF
26Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann 0001, Ulrich Dierkes, Carsten Rustemeier Control Development for Mechatronic Systems with a Fully Reconfigurable Pipeline Architecture. Search on Bibsonomy SBCCI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
26Oscar Gustafsson, Lars Wanhammar Implementation of maximally fast ladder wave digital filters using a numerically equivalent state-space representation. Search on Bibsonomy ISCAS (3) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
26Raphael Weber, Achim Rettberg Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture. Search on Bibsonomy ARC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
26Tim Kaulmann, Deniz Dikmen, Ulrich Rückert 0001 A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation. Search on Bibsonomy HIS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
26Pawel Garstecki, Adam Luczak, Marta Stepniewska A bit-serial implementation of mode decision algorithm for AVC encoders. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
26Amir K. Daneshbeh, M. Anwarul Hasan A Class of Unidirectional Bit Serial Systolic Architectures for Multiplicative Inversion and Division over GF(2m). Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF field arithmetic, finite fields, systolic arrays, Division, inversion, extended Euclidean algorithm
26E. Chaniotakis, Paraskevas Kalivas, Kiamal Z. Pekmestzi Long Number Bit-Serial Squarers. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
26Kenny Johansson, Oscar Gustafsson, Lars Wanhammar Low-complexity bit-serial constant-coefficient multipliers. Search on Bibsonomy ISCAS (3) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
26Florian Dittmann 0001, Achim Rettberg, Thomas Lehmann 0001, Mauro Cesar Zanella Invariants for Distributed Local Control Elements of a New Synchronous Bit-Serial Architecture. Search on Bibsonomy DELTA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
26Achim Rettberg, Florian Dittmann 0001, Mauro Cesar Zanella, Thomas Lehmann 0001 Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures. Search on Bibsonomy SBCCI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
26Amir K. Daneshbeh, M. Anwarul Hasan A Unidirectional Bit Serial Systolic Architecture for Double-Basis Division over GF(2m). Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
26Hyun-Sung Kim 0001, Kee-Young Yoo Bit-Serial AOP Arithmetic Architectures over GF (2m). Search on Bibsonomy InfraSec The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
26Shoji Kawahito, Tatsuya Eki, Yoshiaki Tadokoro A bit-serial column parallel processing architecture for on-sensor discrete Fourier transform. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
26Sebastian T. J. Fenn, Michael Gössel, Mohammed Benaissa, David Taylor On-Line Error Detection for Bit-Serial Multipliers in GF(2m). Search on Bibsonomy J. Electron. Test. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF finite fields, multipliers, parity checking, on-line error detection
25Ciaran Toal, Sakir Sezer The Implementation of Scalable ATM Frame Delineation Circuits. Search on Bibsonomy ICT The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
24Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing
24Johann Großschädl, Erkay Savas, Kazim Yumbul Realizing Arbitrary-Precision Modular Multiplication with a Fixed-Precision Multiplier Datapath. Search on Bibsonomy ReConFig The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Bit-serial multiplier architecture, Scalability, Montgomery modular multiplication
24Nobuaki Okada, Michitaka Kameyama Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells. Search on Bibsonomy ISMVL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Field-programmable VLSI, Multiple-valued source-coupled logic, Differential-Pair circuit, Bit-serial architecture
24Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck A self-organizing defect tolerant SIMD architecture. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Self-organizing, SIMD, data parallel, DNA, defect tolerance, nanocomputing, bit-serial
24Sandeep S. Kumar, Thomas J. Wollinger, Christof Paar Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF least significant digit multiplier, elliptic/hyperelliptic curve cryptography, public key cryptography, digit serial multiplier, Bit serial multiplier
24Jaidev P. Patwardhan, Vijeta Johri, Chris Dwyer, Alvin R. Lebeck A defect tolerant self-organizing nanoscale SIMD architecture. Search on Bibsonomy ASPLOS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF self-organizing, SIMD, data parallel, DNA, defect tolerance, nanocomputing, bit-serial
24A. S. Nepomniaschaya An Associative Parallel Algorithm for Finding a Critical Cycle in Directed Graphs. Search on Bibsonomy ICPADS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Directed weighted graph, critical cycle, optimum branching, bit-serial processing, associative parallel processor, time complexity
24Adger E. Harvin III, José G. Delgado-Frias A Dictionary Machine Emulation on a VLSI Computing Tree System. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1998 DBLP  DOI  BibTeX  RDF tree architectures, VLSI, data structure, pipeline computing, bit-serial, Dictionary machines
24Alain Mérigot Associative Nets: A Graph-Based Parallel Computing Net. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1997 DBLP  DOI  BibTeX  RDF bit-serial arithmetic, graph processing, parallel algorithms, SIMD, fine grain parallelism, Parallel programming models, asynchronous logic
24M. Anwarul Hasan, Vijay K. Bhargava Architecture for a Low Complexity Rate-Adaptive Reed-Solomon Encoder. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Bit-serial structure, rate-adaptive Reed-Solomon encoder, triangular basis, finite field multiplication, generator polynomial
24Jean Vuillemin On Circuits and Numbers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF PROM, 2-adic integers, synchronous decision diagrams, BDD constructs, bit-serial circuits, reset signals, 2Z, arithmetic synthesis f, periodic binary constants, deeply binding synchronous enable, combinational circuit semantics, arbitrary precision, programmable active memories, specification languages, sequential circuits, combinational circuits, digital arithmetic, logic CAD, adders, digital circuits, arithmetic, combinatorial circuits, synchronous circuits, continuous functions, rational numbers
24Veljko M. Milutinovic, Mark Bettinger, Walter A. Helbig Multiplier/Shifter Design Tradeoffs in a 32-bit Microprocessor. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1989 DBLP  DOI  BibTeX  RDF full barrel shifter, large register file, GaAs microprocessor, logic design, microprocessors, microprocessor chips, design tradeoffs, 32 bits, single chip, bit-serial multiplier
24Alok Parmar, Kailash Prasad, Nanditha P. Rao, Joycee Mekie An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory Computing for DNNs. Search on Bibsonomy ISCAS The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
24Khalid Al-Hawaj, Olalekan Afuye, Shady Agwa, Alyssa B. Apsel, Christopher Batten Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM. Search on Bibsonomy ISCAS The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
24Mojtaba Gholamnia Roshan, Mohammad Gholami 4-Bit serial shift register with reset ability and 4-bit LFSR in QCA technology using minimum number of cells and delay. Search on Bibsonomy Comput. Electr. Eng. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
24Jérémy Jean, Amir Moradi 0001, Thomas Peyrin, Pascal Sasdrich Bit-Sliding: A Generic Technique for Bit-Serial Implementations of SPN-based Primitives - Applications to AES, PRESENT and SKINNY. Search on Bibsonomy IACR Cryptol. ePrint Arch. The full citation details ... 2017 DBLP  BibTeX  RDF
24Jérémy Jean, Amir Moradi 0001, Thomas Peyrin, Pascal Sasdrich Bit-Sliding: A Generic Technique for Bit-Serial Implementations of SPN-based Primitives - Applications to AES, PRESENT and SKINNY. Search on Bibsonomy CHES The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
24Kazuya Tanigawa, Ken'ichi Umeda, Tetsuo Hironaka Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor. Search on Bibsonomy ARC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
24Arash Hariri, Arash Reyhani-Masoleh Bit-Serial and Bit-Parallel Montgomery Multiplication and Squaring over GF(2^m). Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
24Krishna M. Sivalingam A Comparison of Bit-Parallel and Bit-Serial Architectures for WDM Networks. Search on Bibsonomy Photonic Netw. Commun. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
24Anders Åström, Michael Hall, Anders Edman A comparison of bit-serial and multi-bit processor elements in a real-time signal processing SIMD architecture. Search on Bibsonomy HiPC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
24David Crook, John Fulcher A Comparison of Bit Serial and Bit Parallel DCT Designs. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
23Vijay Sundararajan, Keshab K. Parhi Reducing bus transition activity by limited weight coding with codeword slimming. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
23Huy T. Nguyen, Abhijit Chatterjee, Rabindra K. Roy Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
23Siavash Bayat Sarmadi, M. Anwar Hasan On Concurrent Detection of Errors in Polynomial Basis Multiplication. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
23Tamás Szabó, Lörinc Antoni, Gábor Horváth 0001, Béla Fehér A Full-Parallel Digital Implementation for Pre-Trained NNs. Search on Bibsonomy IJCNN (2) The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
23M. Yan, John V. McCanny, Yi Hu VLSI architectures for vector quantization. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
23Alex Fit-Florea, Lun Li, Mitchell A. Thornton, David W. Matula A Discrete Logarithm Number System for Integer Arithmetic Modulo 2k: Algorithms and Lookup Structures. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
21Junfeng Fan, Lejla Batina, Ingrid Verbauwhede Light-weight implementation options for curve-based cryptography: HECC is also ready for RFID. Search on Bibsonomy ICITST The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
21Magnus Karlsson, Mark Vesterbacka Digit-serial/parallel multipliers with improved throughput and latency. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
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