Search results for "CDFG"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
142	Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate	CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL.	ISVLSI	2006	DBLP DOI BibTeX RDF
90	Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui	Control and Data Flow Graph Extraction for High-Level Synthesis.	ISVLSI	2004	DBLP DOI BibTeX RDF
73	Johnny Öberg, Jouni Isoaho, Peeter Ellervee, Axel Jantsch, Ahmed Hemani	A Rule-Based Approach for Improving Allocation of Filter Structures in HLS.	VLSI Design	1996	DBLP DOI BibTeX RDF	CDFG, CDFG Transformations, Filter structures, Optimisations, High-Level Synthesis, Allocation, Rule-Based
72	Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy	Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
52	Euiseok Kim, Jeong-Gun Lee, Dong-Ik Lee	Building a Distributed Asynchronous Control Unit through Automatic Derivation of Hierarchically Decomposed AFSMs from a CDFG.	ARVLSI	2001	DBLP DOI BibTeX RDF
45	Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi	Low test application time resource binding for behavioral synthesis.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	CDFG, high-level synthesis, Testability, test synthesis
36	Zhengting He, Cheng Peng, Aloysius K. Mok	A Performance Estimation Tool for Video Applications.	IEEE Real Time Technology and Applications Symposium	2006	DBLP DOI BibTeX RDF
36	GuangWei Zou, Xiang Liu	An Efficient Approach to Custom Instruction Set Generation.	RTCSA	2005	DBLP DOI BibTeX RDF	Major Block, Profiling, Hardware Acceleration, ASIPs, Custom Instruction
36	Renqiu Huang, Ranga Vemuri	Forward-Looking Macro Generation and Relational Placement During High Level Synthesis to FPGAs.	IPDPS	2004	DBLP DOI BibTeX RDF	critical net, performance, placement, Behavioral synthesis, macro
36	Ming Zhu, Jinian Bian, Weimin Wu, Hongxi Xue	Property Classification for Functional Verification Based.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
36	Katalin Pásztor-Varga	A Number Theoretical Approach to the Allocation Problem of a Pipelined Dataflow Model.	PARELEC	2002	DBLP DOI BibTeX RDF	control data flow graph, High level synthesis, pipeline, allocation, time diagram
36	Miodrag Potkonjak, Mani B. Srivastava	Behavioral optimization using the manipulation of timing constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
36	Ulrich Holtmann, Rolf Ernst	Experiments with low-level speculative computation based on multiple branch prediction.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
34	Satyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi, Luca Benini	Efficient mapping of CDFG onto coarse-grained reconfigurable array architectures.	ASP-DAC	2017	DBLP DOI BibTeX RDF
34	Zhongda Yuan, Yuchun Ma, Jinian Bian, Kang Zhao	Automatic enhanced CDFG generation based on runtime instrumentation.	CSCWD	2013	DBLP DOI BibTeX RDF
34	Rajdeep Mukherjee, Priyankar Ghosh, N. Sravan Kumar, Pallab Dasgupta, Ajit Pal	Multi-objective Low-Power CDFG Scheduling Using Fine-Grained DVS Architecture in Distributed Framework.	ISED	2012	DBLP DOI BibTeX RDF
34	Toshiyuki Kato, Takaaki Miyauchi, Yoshizo Osumi, Hironori Yamauchi, Hideto Nishikado, Takaaki Miyake, Shiro Kobayashi	A CDFG generating method from C program for LSI design.	APCCAS	2008	DBLP DOI BibTeX RDF
34	Mohammad Hosseinabady, Pejman Lotfi-Kamran, Fabrizio Lombardi, Zainalabedin Navabi	Low overhead DFT using CDFG by modifying controller.	IET Comput. Digit. Tech.	2007	DBLP DOI BibTeX RDF
34	Somsubhra Mondal, Seda Ogrenci Memik	Resource sharing in pipelined CDFG synthesis.	ASP-DAC	2005	DBLP DOI BibTeX RDF
34	Paulo Sérgio B. do Nascimento, Manoel Eusébio de Lima, Paulo Maciel 0001	CDFG -Petri Net Temporal Partitioning for Switching Context Applications.	SBCCI	2002	DBLP BibTeX RDF
27	Andrew Stone, Elias S. Manolakos	Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis.	ASAP	2000	DBLP DOI BibTeX RDF	Optimal VHDL, DG2VHDL, Hierarchical CDFG, High Level Synthesis, Dependence Graph, Signal Flow Graph, Design Complexity
27	Peter F. A. Middelhoek, Sreeranga P. Rajan	From VHDL to efficient and first-time-right designs: a formal approach.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	CDFG, SFG, rapid system prototyping, VHDL, VHDL, design methodology, correctness by construction, transformational design
27	Youngsoo Shin, Kiyoung Choi	Software synthesis through task decomposition by dependency analysis.	ICCAD	1996	DBLP DOI BibTeX RDF	CDFG, scheduler, dependency, C, VHDL, thread, Software synthesis
18	Nagaraju Pothineni, Anshul Kumar, Kolin Paul	A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions.	VLSI Design	2008	DBLP DOI BibTeX RDF
18	Ana Fuentes Martinez, Krzysztof Kuchcinski	Graph Matching Constraints for Synthesis with Complex Components.	DSD	2007	DBLP DOI BibTeX RDF
18	Achim Rettberg, Franz-Josef Rammig	Integration of Energy Reduction into High-Level Synthesis by Partitioning.	DIPES	2006	DBLP DOI BibTeX RDF
18	Achim Rettberg, Franz J. Rammig	A new Design Partitioning Approach for Low Power High-Level Synthesis.	DELTA	2006	DBLP DOI BibTeX RDF
18	Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski	Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths.	ICCD	2005	DBLP DOI BibTeX RDF
18	David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee	Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code.	LCPC	2005	DBLP DOI BibTeX RDF
18	Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	A cosynthesis algorithm for application specific processors with heterogeneous datapaths.	ASP-DAC	2004	DBLP DOI BibTeX RDF
18	David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee	Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	scheduling, optimizations, FPGAs, compilers, binary translation, chaining, hardware synthesis
18	Youngsik Kim, Shekhar Kopuri, Nazanin Mansouri	Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD).	ISQED	2004	DBLP DOI BibTeX RDF
18	Michèl A. J. Rosien, Yuanqing Guo, Gerard J. M. Smit, Thijs Krol	Mapping Applications to an FPFA Tile.	DATE	2003	DBLP DOI BibTeX RDF
18	Reinaldo A. Bergamaschi	Bridging the domains of high-level and logic synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
18	Elie Torbey, John P. Knight	Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
18	V. Srinivasan, Sriram Govindarajan, Ranga Vemuri	Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
18	Sandhya Seshadri, Michael S. Hsiao	Formal Value-Range and Variable Testability Techniques for High-Level Design-For-Testability.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	behavioral level, value range, SSA representation, design for testability
18	Dirk Herrmann, Rolf Ernst	Improved interconnect sharing by identity operation insertion.	ICCAD	1999	DBLP DOI BibTeX RDF
18	Frank F. Hsu, Janak H. Patel	High-Level Controllability and Observability Analysis for Test Synthesis.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	controllability, observability, high-level test synthesis, behavioral modification
18	Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha	Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions.	ICCAD	1997	DBLP DOI BibTeX RDF	control-flow intensive, scheduling, parallelism, pipelining, loop unrolling
18	Yunn Yen Chen, Yu-Chin Hsu, Chung-Ta King	MULTIPAR: behavioral partition for synthesizing multiprocessor architectures.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
18	John A. Nestor, Ganesh Krishnamoorthy	SALSA: a new approach to scheduling with timing constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF