Search results for "CMOS-SOI"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
70	Rajiv V. Joshi, Kaushik Roy 0001	Design of Deep Sub-Micron CMOS Circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF
46	Cédric Majek, Yann Deval, Hervé Lapuyade, Jean-Baptiste Bégueret	Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO.	SBCCI	2009	DBLP DOI BibTeX RDF	CMOS-SOI, factorial delay locked loop, multi-standard frequency synthesizer, quadrature phase signals, voltage controlled delay element
35	Devesh Nema, Thomas Toifl	Active compensation of supply noise for a 5-GHz VCO in 45-nm CMOS SOI technology.	ISCAS	2008	DBLP DOI BibTeX RDF
31	Alexandre Valentian, Olivier Thomas, Andrei Vladimirescu, Amara Amara	Modeling subthreshold SOI logic for static timing analysis.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
27	Selim J. Abou-Samra, P. A. Aisa, Alain Guyot, Bernard Courtois	3D CMOS SOL for high performance computing.	ISLPED	1998	DBLP DOI BibTeX RDF
23	Toshiro Akino, Takashi Hamahata	A Clock Generator Driven by a Unified-CBiCMOS Buffer Driver for High Speed and Low Energy Operation.	PATMOS	2006	DBLP DOI BibTeX RDF
20	Kaisarbek Omirzakhov, Firooz Aflatouni	12.1 Monolithically Integrated Sub-63 fJ/b 8-Channel 256Gb/s Optical Transmitter with Autonomous Wavelength Locking in 45nm CMOS SOI.	ISSCC	2024	DBLP DOI BibTeX RDF
20	Panagiotis G. Zarkos, Sidney Buchbinder, Christos G. Adamopoulos, Sarika Madhvapathy, Olivia Hsu, Jake Whinnery, Pavan Bhargava, Vladimir Stojanovic	Fully Integrated Electronic-Photonic Ultrasound Receiver Array for Endoscopic Applications in a Zero-Change 45-nm CMOS-SOI Process.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
20	Tristan Lecocq, Olivier Mazouffre, Eric Kerhervé, Jean-Marie Pham	NB-IoT Wideband Power Amplifier and Diode-Based Antenna Switch co-Integration in 130 nm CMOS SOI.	NEWCAS	2023	DBLP DOI BibTeX RDF
20	Yangyang Zhou, Hao Zhang, Lei Zhu, Yuan Zhao, Tian Zhang	A Fully Integrated S-Band Phase-Array Receiver in 0.13 μm CMOS SOI.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
20	Michael Yampolsky, Evgeny Pikhay, Yakov Roizin	Embedded UV Sensors in CMOS SOI Technology.	Sensors	2022	DBLP DOI BibTeX RDF
20	Peter M. Asbeck, Sravya Alluri, Narek Rostomyan, Jefy Alex Jayamon	Reliability of CMOS-SOI power amplifiers for millimeter-wave 5G: the case for pMOS (Invited).	IRPS	2022	DBLP DOI BibTeX RDF
20	Cameron Hill, James F. Buckwalter	A 1-to-18GHz Distributed-Stacked-Complementary Triple-Balanced Passive Mixer With up to 33dBm IIP3 and Integrated LO Driver in 45nm CMOS SOI.	ISSCC	2022	DBLP DOI BibTeX RDF
20	Elisabetta Moisello, Michele Vaiana, Maria Eloisa Castagna, Antonella La Malfa, Giuseppe Bruno, Edoardo Bonizzoni, Piero Malcovati	A Novel CMOS-SOI High-Responsivity Thermopile for Thermal Sensing Applications.	ISCAS	2022	DBLP DOI BibTeX RDF
20	Min-Su Kim, Hee-Sauk Jhon	An ESD and Interference-Robust Protection Circuit for Cascode Low-Noise Amplifier in CMOS-SOI Technology.	IEEE Access	2021	DBLP DOI BibTeX RDF
20	Toshihiko Yoshimasu, Mengchu Fang, Tsuyoshi Sugiura	A 26-GHz-Band High Back-Off Efficiency Stacked-FET Power Amplifier IC with Adaptively Controlled Bias and Load Circuits in 45-nm CMOS SOI.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2021	DBLP BibTeX RDF
20	Christos G. Adamopoulos, Sidney Buchbinder, Panagiotis G. Zarkos, Pavan Bhargava, Asmaysinh Gharia, Ali M. Niknejad, Mekhail Anwar, Vladimir Stojanovic	Fully Integrated Electronic-Photonic Sensor for Label-Free Refractive Index Sensing in Advanced Zero-Change CMOS-SOI Process.	CICC	2021	DBLP DOI BibTeX RDF
20	Panagiotis G. Zarkos, Sidney Buchbinder, Christos G. Adamopoulos, Sarika Madhvapathy, Olivia Hsu, Jake Whinnery, Pavan Bhargava, Vladimir Stojanovic	Fully Integrated Electronic-Photonic Ultrasound Receiver Array for Endoscopic Imaging Applications in a Zero-Change 45nm CMOS-SOI Process.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
20	Kang Ning 0002, Yihao Fang, Navid Hosseinzadeh, James F. Buckwalter	A 30-GHz CMOS SOI Outphasing Power Amplifier With Current Mode Combining for High Backoff Efficiency and Constant Envelope Operation.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
20	Hussam AlShammary, Ahmed Hamza 0004, Cameron Hill, James F. Buckwalter	A Reconfigurable Spectrum-Compressing Receiver for Non-Contiguous Carrier Aggregation in CMOS SOI.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
20	Soroush Moallemi, Payam Mehr, Kevin Grout, Trevor J. Thornton, Jennifer Kitchen	Adaptive Power Control Using Current Adjustment for Watt-Level Power Amplifiers in CMOS SOI.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
20	Mannem Naga Sasikanth, Min-Yu Huang, Tzu-Yuan Huang, Sensen Li, Hua Wang 0006	24.2 A Reconfigurable Series/Parallel Quadrature-Coupler-Based Doherty PA in CMOS SOI with VSWR Resilient Linearity and Back-Off PAE for 5G MIMO Arrays.	ISSCC	2020	DBLP DOI BibTeX RDF
20	Omar El-Aassar, Gabriel M. Rebeiz	A DC-to-108-GHz CMOS SOI Distributed Power Amplifier and Modulator Driver Leveraging Multi-Drive Complementary Stacked Cells.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
20	Rana Azhar Shaheen, Rehman Akbar, Timo Rahkonen, Janne Aikio, Alok Sethi, Aarno Pärssinen	A Differential Reflection-Type Phase Shifter Based on CPW Coupled-Line Coupler in 45nm CMOS SOI.	ISWCS	2019	DBLP DOI BibTeX RDF
20	Maria Malits, Igor Brouk, Yael Nemirovsky	Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.	Sensors	2018	DBLP DOI BibTeX RDF
20	Rui Ma, Martin Kreißig, Frank Ellinger	A Fast Switchable and Band-Tunable 5-7.5 GHz LNA in 45 nm CMOS SOI Technology for Multi-Standard Wake-up Radios.	ICECS	2018	DBLP DOI BibTeX RDF
20	Hamed Gheidi, Toshifumi Nakatani, Vincent W. Leung, Peter M. Asbeck	A 1-3 GHz Delta-Sigma-Based Closed-Loop Fully Digital Phase Modulator in 45-nm CMOS SOI.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
20	Maria Malits, Yael Nemirovsky	Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology.	Sensors	2017	DBLP DOI BibTeX RDF
20	Jen-Chieh Hsueh, Vanessa H.-C. Chen, Jean-Olivier Plouchart	An ultra-high bandwidth sub-ranging ADC with programmable dynamic range in 32nm CMOS SOI.	MWSCAS	2017	DBLP DOI BibTeX RDF
20	Rana Azhar Shaheen, Rehman Akbar, Alok Sethi, Janne P. Aikio, Timo Rahkonen, Aarno Pärssinen	A 45nm CMOS SOI, four element phased array receiver supporting two MIMO channels for 5G.	NORCAS	2017	DBLP DOI BibTeX RDF
20	Janne P. Aikio, Alok Sethi, Rana Azhar Shaheen, Rehman Akbar, Timo Rahkonen, Aarno Pärssinen	A fully integrated 13 GHz CMOS SOI stacked power amplifier for 5G wireless systems.	NORCAS	2017	DBLP DOI BibTeX RDF
20	Chen Sun 0003, Mark T. Wade, Michael Georgas, Sen Lin, Luca Alloatti, Benjamin Moss, Rajesh Kumar, Amir H. Atabaki, Fabio Pavanello, Jeffrey Shainline, Jason Orcutt, Rajeev J. Ram, Milos A. Popovic, Vladimir Stojanovic	A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
20	Mohammad Sadegh Mehrjoo, James F. Buckwalter	13.4 A microwave injection-locking outphasing modulator with 30dB dynamic range and 22% system efficiency in 45nm CMOS SOI.	ISSCC	2016	DBLP DOI BibTeX RDF
20	Sergey V. Rylov, Troy J. Beukema, Zeynep Toprak Deniz, Thomas Toifl, Yong Liu 0023, Ankur Agrawal, Peter Buchmann, Alexander V. Rylyakov, Michael P. Beakes, Benjamin D. Parker, Mounir Meghelli	3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI.	ISSCC	2016	DBLP DOI BibTeX RDF
20	Kexu Sun, Zheng Gao, Ping Gui, Rui Wang 0035, Ismail Oguzman, Xiaochen Xu, Karthik Vasanth, Qifa Zhou, K. Kirk Shung	A 180-Vpp Integrated Linear Amplifier for Ultrasonic Imaging Applications in a High-Voltage CMOS SOI Technology.	IEEE Trans. Circuits Syst. II Express Briefs	2015	DBLP DOI BibTeX RDF
20	Vanessa Hung-Chu Chen, Lawrence T. Pileggi	A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
20	Jonas Lindstrand, Ivaylo Vasilev, Henrik Sjöland	A low band cellular terminal antenna impedance tuner in 130nm CMOS-SOI technology.	ESSCIRC	2014	DBLP DOI BibTeX RDF
20	Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel	A DDR3/4 memory link TX supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI.	ESSCIRC	2014	DBLP DOI BibTeX RDF
20	Vanessa Hung-Chu Chen, Lawrence T. Pileggi	22.2 A 69.5mW 20GS/s 6b time-interleaved ADC with embedded time-to-digital calibration in 32nm CMOS SOI.	ISSCC	2014	DBLP DOI BibTeX RDF
20	Jing-Hwa Chen, S. R. Helmi, R. Azadegan, F. Aryanfar, S. Mohammadi	A Broadband Stacked Power Amplifier in 45-nm CMOS SOI Technology.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
20	Mihai A. T. Sanduleanu, Alberto Valdes-Garcia, Y. Liu, Benjamin D. Parker, Shlomo Shlafman, Benny Sheinman, Danny Elad, Scott K. Reynolds, Daniel J. Friedman	A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI.	CICC	2013	DBLP DOI BibTeX RDF
20	Florence Sonnerat, Romain Pilard, Frederic Gianesello, Sebastien Jan, François Le Pennec, Christian Person, Cedric Durand, Daniel Gloria	30 dBm P1dB and 4 dB insertion losses optimized 4G antenna tuner fully integrated in a 130 nm CMOS SOI technology.	RWS	2013	DBLP DOI BibTeX RDF
20	Yong Liu 0023, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert K. Montoye, Leland Chang, José A. Tierno, Daniel J. Friedman	A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.	ISSCC	2013	DBLP DOI BibTeX RDF
20	Xuebei Yang, Aydin Babakhani	Optical waveguides and photodiodes in 0.18µm CMOS SOI with no post-processing.	OFC/NFOEC	2013	DBLP BibTeX RDF
20	James F. Buckwalter, Xuezhe Zheng, Guoliang Li 0003, Kannan Raj, Ashok V. Krishnamoorthy	A Monolithic 25-Gb/s Transceiver With Photonic Ring Modulators and Ge Detectors in a 130-nm CMOS SOI Process.	IEEE J. Solid State Circuits	2012	DBLP DOI BibTeX RDF
20	Maria Malits, Dan Corcos, Alexander Svetlitza, Danny Elad, Yael Nemirovsky	Thermal performance of CMOS-SOI transistors from weak to strong inversion.	IEEE Instrum. Meas. Mag.	2012	DBLP DOI BibTeX RDF
20	Hayg-Taniel Dabag, Peter M. Asbeck, James F. Buckwalter	Linear operation of high-power millimeter-wave stacked-FET PAs in CMOS SOI.	MWSCAS	2012	DBLP DOI BibTeX RDF
20	Christian Menolfi, Juergen Hertle, Thomas Toifl, Thomas Morf, Daniele Gardellini, Matthias Braendli, Peter Buchmann, Marcel A. Kossel	A 28Gb/s source-series terminated TX in 32nm CMOS SOI.	ISSCC	2012	DBLP DOI BibTeX RDF
20	Mehmet Parlak, James F. Buckwalter	A 2.9-dB noise figure, Q-band millimeter-wave CMOS SOI LNA.	CICC	2011	DBLP DOI BibTeX RDF
20	Mihai A. T. Sanduleanu, Scott K. Reynolds, Jean-Olivier Plouchart	A 4GS/s, 8.45 ENOB and 5.7fJ/conversion, digital assisted, sampling system in 45nm CMOS SOI.	CICC	2011	DBLP DOI BibTeX RDF
20	Christian Menolfi, Thomas Toifl, Michael Ruegg, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Morf	A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI.	ISSCC	2011	DBLP DOI BibTeX RDF
20	Alessandro Fonte, Sergio Saponara, Giancarlo Pinto, Bruno Neri	Feasibility study and on-chip antenna for fully integrated μRFID tag at 60 GHz in 65 nm CMOS SOI.	RFID-TA	2011	DBLP DOI BibTeX RDF
20	Erik Öjefors, Neda Baktash, Yan Zhao 0002, Richard Al Hadi, Hani Sherry, Ullrich R. Pfeiffer	Terahertz imaging detectors in a 65-nm CMOS SOI technology.	ESSCIRC	2010	DBLP DOI BibTeX RDF
20	Wayne D. Dettloff, John C. Eble, Lei Luo 0006, Pravin Kumar Venkatesan, Fred Heaton, Teva Stone, Barry Daly	A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI.	ISSCC	2010	DBLP DOI BibTeX RDF
20	Nicolas Deparis, Alexandre Siligaris, Pierre Vincent, Nathalie Rolland	Ultra low consumption UWB pulsed-ILO RF front-end transmitter at 60 GHz in 65-nm CMOS-SOI.	PIMRC	2009	DBLP DOI BibTeX RDF
20	Yusuke Ohtomo, Hiroshi Koizumi, Kazuyoshi Nishimura, Masafumi Nogawa	A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI.	IEICE Trans. Electron.	2008	DBLP DOI BibTeX RDF
20	Gilles Jacquemod, Lionel Geynet, Benjamin Nicolle, Emeric de Foucauld, William Tatinian, Pierre Vincent	Design and modelling of a multi-standard fractional PLL in CMOS/SOI technology.	Microelectron. J.	2008	DBLP DOI BibTeX RDF
20	S. Robinet, B. Gomez, N. Delorme	A CMOS-SOI 2.45GHz Remote-Powered Sensor Tag.	ISSCC	2008	DBLP DOI BibTeX RDF
20	Adithyaram Narasimha, Behnam Analui, Yi Liang, Thomas J. Sleboda, Sherif Abdalla, Erwin Balmater, Steffen Gloeckner, Drew Guckenberger, Mark Harrison, Roger G. M. P. Koumans, Daniel Kucharski, Attila Mekis, Sina Mirsaidi, Dan Song, Thierry Pinguet	A Fully Integrated 4 × 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 µm CMOS SOI Technology.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
20	Michael G. Khazhinsky	ESD protection strategies in advanced CMOS SOI ICs.	Microelectron. Reliab.	2007	DBLP DOI BibTeX RDF
20	Baudouin Martineau, Andreia Cathelin, François Danneville, Andreas Kaiser, Gilles Dambrine, Sylvie Lépilliet, Frederic Gianesello, Didier Belot	80 GHz low noise amplifiers in 65nm CMOS SOI.	ESSCIRC	2007	DBLP DOI BibTeX RDF
20	Adithyaram Narasimha, Behnam Analui, Yi Liang, Thomas J. Sleboda, Cary Gunn	A Fully Integrated 4ÿ10Gb/s DWDM Optoelectronic Transceiver in a standard 0.13μm CMOS SOI.	ISSCC	2007	DBLP DOI BibTeX RDF
20	Christian Menolfi, Thomas Toifl, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz	A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI.	ISSCC	2007	DBLP DOI BibTeX RDF
20	Behnam Analui, Drew Guckenberger, Daniel Kucharski, Adithyaram Narasimha	A Fully Integrated 20-Gb/s Optoelectronic Transceiver Implemented in a Standard 0.13- $\mu{\hbox {m}}$ CMOS SOI Technology.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
20	Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz	A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
20	Babak Vakili-Amini, Reza Abdolvand, Farrokh Ayazi	A 4.5-mW Closed-Loop $\Delta\Sigma$ Micro-Gravity CMOS SOI Accelerometer.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
20	Babak Vakili-Amini, Reza Abdolvand, Farrokh Ayazi	A 4.5mW Closed-Loop ΔΣ Micro-Gravity CMOS-SOI Accelerometer.	ISSCC	2006	DBLP DOI BibTeX RDF
20	Takakuni Douseki, Toshishige Shimamura, Nobutaro Shibata	A Sub-0.5 V Differential ED-CMOS/SOI Circuit with Over-1-GHz Operation.	IEICE Trans. Electron.	2005	DBLP DOI BibTeX RDF
20	Mihai A. T. Sanduleanu, Razvan Ionita, Andrei Vladimirescu	A 34GHz/1V prescaler in 90nm CMOS SOI.	ESSCIRC	2005	DBLP DOI BibTeX RDF
20	Markus P. J. Mergens, Olivier Marichal, Steven Thijs, Benjamin Van Camp, Christian C. Russ	Advanced SCR ESD protection circuits for CMOS/SOI nanotechnologies.	CICC	2005	DBLP DOI BibTeX RDF
20	Jinsook Kim, Weiping Ni, Edwin C. Kan	Resistive Loss and Trans-Impedance Characterization of Nonlinear Transmission Lines on CMOS SOI Substrate.	SoCC	2005	DBLP DOI BibTeX RDF
20	Babak Vakili-Amini, Farrokh Ayazi	A 2.5-V 14-bit ΣΔ CMOS SOI capacitive accelerometer.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
20	Igor Brouk, Yael Nemirovsky	CMOS SOI image sensor.	ICECS	2004	DBLP DOI BibTeX RDF
20	Erik Säll, Mark Vesterbacka	Design of a Comparator in CMOS SOI.	IWSOC	2004	DBLP DOI BibTeX RDF
20	Carlo Tinella, Jean-Michel Fournier, Didier Belot, Vincent Knopik	A high-performance CMOS-SOI antenna switch for the 2.5-5-GHz band.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
20	Daniela De Venuto, Michael J. Ohletz	Floating body effects model for fault simulation of fully depleted CMOS/SOI circuits.	Microelectron. J.	2003	DBLP DOI BibTeX RDF
20	Mamoru Ugajin, Tsuneo Tsukahara	A 1-V 2.4-GHz FSK receiver with a complex BPF and a frequency doubler in CMOS/SOI.	CICC	2003	DBLP DOI BibTeX RDF
20	Jader A. De Lima, Sidnei F. Silva, Adriano S. Cordeiro, Michel Verleysen	A CMOS/SOI Single-input PWM Discriminator for Low-voltage Body-implanted Applications.	VLSI Design	2002	DBLP DOI BibTeX RDF
20	Carlo Tinella, Jean-Michel Fournier, J. Haidar	Noise contribution in a fully integrated 1-V, 2.5-GHz LNA in CMOS-SOI technology.	ICECS	2001	DBLP DOI BibTeX RDF
20	Srinivasa R. Banna, Philip C. H. Chan, Mansun Chan, Samuel K. H. Fung, Ping K. Ko	Fully depleted CMOS/SOI device design guidelines for low power applications.	ISLPED	1997	DBLP DOI BibTeX RDF
15	Sheng Li 0007, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi	McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures.	MICRO	2009	DBLP DOI BibTeX RDF
15	O. Katz, D. A. Ramon, Israel A. Wagner	A Robust Random Number Generator Based on a Differential Current-Mode Chaos.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
15	Xiao Liu 0001, Andreas Demosthenous, Nick Donaldson	A Fully Integrated Fail-safe Stimulator Output Stage Dedicated to FES Stimulation.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Nicolas Mäding, Jens Leenstra, Jürgen Pille, Rolf Sautter, Stefan Büttner, Sebastian Ehrenreich, W. Haller	The vector fixed point unit of the synergistic processor element of the cell architecture processor.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
15	Jean-Luc Rebourg, Jean-Denis Muller, Manuel Samuelides	SPIKE_4096: A Neural Integrated Circuit for Image Segmentation.	ICES	1998	DBLP DOI BibTeX RDF