Search results for "CMPS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
99	Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar	Optimizing Replication, Communication, and Capacity Allocation in CMPs.	ISCA	2005	DBLP DOI BibTeX RDF
80	Ian M. Bell, Nabil Hasasneh, Chris R. Jesshope	Supporting Microthread Scheduling and Synchronisation in CMPs.	Int. J. Parallel Program.	2006	DBLP DOI BibTeX RDF	Microgrids, microthreads, schedulers, CMPs, register files
80	James Laudon, Lawrence Spracklen	The Coming Wave of Multithreaded Chip Multiprocessors.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	performance, parallel programming, multithreading, Chip multiprocessing
68	Sungjune Youn, Hyunhee Kim, Jihong Kim 0001	A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches.	ISLPED	2007	DBLP DOI BibTeX RDF	chip multiprocessors (CMPS), performance, embedded systems, architecture, low-power, L2 cache
68	Dmitry G. Korzun, Andrei V. Gurtov	A local equilibrium model for P2P resource ranking.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
68	Bill Lin 0001, Jun (Jim) Xu, Nan Hua, Hao Wang 0006, Haiquan (Chuck) Zhao	A randomized interleaved DRAM architecture for the maintenance of exact statistics counters.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
68	Sipat Triukose, Zhihua Wen, Michael Rabinovich	Content delivery networks: how big is big enough?	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
68	Alma Riska, Erik Riedel	Evaluation of disk-level workloads at different time scales.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
61	Jianwei Chen, Murali Annavaram, Michel Dubois 0001	SlackSim: a platform for parallel simulations of CMPs on CMPs.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
57	José L. Abellán, Juan Fernández 0001, Manuel E. Acacio	Efficient and scalable barrier synchronization for many-core CMPs.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	g-line-based barrier synchronization, global interconnection lines, many-core cmps, s-csma technique
57	Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar 0002	A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors.	ITC	2002	DBLP DOI BibTeX RDF
53	Hongbo Zeng, Kun Huang, Ming Wu, Weiwu Hu	Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
53	Chun Liu 0001, Anand Sivasubramaniam, Mahmut T. Kandemir, Mary Jane Irwin	Enhancing L2 organization for CMPs with a center cell.	IPDPS	2006	DBLP DOI BibTeX RDF
45	Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan	Compiler directed network-on-chip reliability enhancement for chip multiprocessors.	LCTES	2010	DBLP DOI BibTeX RDF	reliability, compiler, noc, chip multiprocessors
45	Hyunhee Kim, Jung Ho Ahn, Jihong Kim 0001	Replication-aware leakage management in chip multiprocessors with private L2 cache.	ISLPED	2010	DBLP DOI BibTeX RDF	leakage power management, chip multiprocessors, L2 caches
45	Seung Woo Son 0001, Mahmut T. Kandemir, Mustafa Karaköy, Dhruva R. Chakrabarti	A compiler-directed data prefetching scheme for chip multiprocessors.	PPoPP	2009	DBLP DOI BibTeX RDF	compiler, chip multiprocessors, prefetching, helper thread
45	Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, Russ Joseph	Process variation characterization of chip-level multiprocessors.	DAC	2009	DBLP DOI BibTeX RDF	software, process variation, characterization
45	Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger	Multitasking workload scheduling on flexible-core chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	flexible cores, multitask scheduling, multicore architectures
45	Mario Donato Marino	L2-Cache Hierarchical Organizations for Multi-core Architectures.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
45	Vasileios Liaskovitis, Shimin Chen, Phillip B. Gibbons, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Michael Kozuch, Todd C. Mowry, Chris Wilkerson	Parallel depth first vs. work stealing schedulers on CMP architectures.	SPAA	2006	DBLP DOI BibTeX RDF	scheduling, caches, chip multiprocessors
45	Julia Chen, Philo Juang, Kevin Ko, Gilberto Contreras, David Penry, Ram Rangan, Adam Stoler, Li-Shiuan Peh, Margaret Martonosi	Hardware-modulated parallelism in chip multiprocessors.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
45	Bradford M. Beckmann, David A. Wood 0001	Managing Wire Delay in Large Chip-Multiprocessor Caches.	MICRO	2004	DBLP DOI BibTeX RDF
45	David P. Anderson, Ron Kuivila	A System for Computer Music Performance.	ACM Trans. Comput. Syst.	1990	DBLP DOI BibTeX RDF
42	Dan Gibson, David A. Wood 0001	Forwardflow: a scalable core for power-constrained CMPs.	ISCA	2010	DBLP DOI BibTeX RDF	scalable core, chip multiprocessor (cmp), power
42	Gilles Pokam, Cristiano Pereira, Klaus Danne, Rolf Kassa, Ali-Reza Adl-Tabatabai	Architecting a chunk-based memory race recorder in modern CMPs.	MICRO	2009	DBLP DOI BibTeX RDF	memory race recorder, determinism, deterministic replay
42	Guangyu Sun 0003, Xiangyu Dong, Yuan Xie 0001, Jian Li 0059, Yiran Chen 0001	A novel architecture of the 3D stacked MRAM L2 cache for CMPs.	HPCA	2009	DBLP DOI BibTeX RDF
42	Alberto Ros 0001, Manuel E. Acacio, José M. García 0001	Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs.	APPT	2009	DBLP DOI BibTeX RDF
42	Major Bhadauria, Vincent M. Weaver, Sally A. McKee	Accomodating Diversity in CMPs with Heterogeneous Frequencies.	HiPEAC	2009	DBLP DOI BibTeX RDF
42	Mahmut T. Kandemir, Ozcan Ozturk 0001, Sai Prashanth Muralidhara	Dynamic thread and data mapping for NoC based CMPs.	DAC	2009	DBLP DOI BibTeX RDF	mapping, dynamic, CMP, thread, NoC, data
42	Christian Fensch, Marcelo Cintra	An OS-based alternative to full hardware coherence on tiled CMPs.	HPCA	2008	DBLP DOI BibTeX RDF
42	Jaehyuk Huh 0001, Doug Burger, Stephen W. Keckler	Exploring the Design Space of Future CMPs.	IEEE PACT	2001	DBLP DOI BibTeX RDF
39	Jianwei Chen, Lakshmi Kumar Dabbiru, Daniel Wong 0001, Murali Annavaram, Michel Dubois 0001	Adaptive and Speculative Slack Simulations of CMPs on CMPs.	MICRO	2010	DBLP DOI BibTeX RDF
39	Jianwei Chen, Murali Annavaram, Michel Dubois 0001	SlackSim: a platform for parallel simulations of CMPs on CMPs.	SIGARCH Comput. Archit. News	2009	DBLP DOI BibTeX RDF
34	Xiang Zhang, Ahmed Louri	A multilayer nanophotonic interconnection network for on-chip many-core communications.	DAC	2010	DBLP DOI BibTeX RDF	interconnection networks, CMP, 3D, silicon photonics
34	Shekhar Srikantaiah, Mahmut T. Kandemir, Qian Wang	SHARP control: controlled shared cache management in chip multiprocessors.	MICRO	2009	DBLP DOI BibTeX RDF
34	Mahmut T. Kandemir, Sai Prashanth Muralidhara, Sri Hari Krishna Narayanan, Yuanrui Zhang, Ozcan Ozturk 0001	Optimizing shared cache behavior of chip multiprocessors.	MICRO	2009	DBLP DOI BibTeX RDF
34	Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick, Russ Joseph	Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
34	Sevin Fide, Stephen F. Jenks	Architecture optimizations for synchronization and communication on chip multiprocessors.	IPDPS	2008	DBLP DOI BibTeX RDF
34	Lars Arge, Michael T. Goodrich, Michael J. Nelson 0002, Nodari Sitchinava	Fundamental parallel algorithms for private-cache chip multiprocessors.	SPAA	2008	DBLP DOI BibTeX RDF	parallel external memory, pem, private-cache cmp
34	Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo	Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
34	John Cieslewicz, Kenneth A. Ross, Ioannis Giannakakis	Parallel buffers for chip multiprocessors.	DaMoN	2007	DBLP DOI BibTeX RDF
34	Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya	Power reduction of chip multi-processors using shared resource control cooperating with DVFS.	ICCD	2007	DBLP DOI BibTeX RDF
34	Weiwu Hu, Rui Hou, Jun-Hua Xiao, Long-Bin Zhang	High Performance General-Purpose Microprocessors: Past and Future.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	high performance general-purpose microprocessor, Godson processor, chip multiprocessors, instruction level parallelism, thread level parallelism, data level parallelism
34	Gregory Buehrer, Srinivasan Parthasarathy 0001, Yen-Kuang Chen	Adaptive Parallel Graph Mining for CMP Architectures.	ICDM	2006	DBLP DOI BibTeX RDF
34	Bradford M. Beckmann, Michael R. Marty, David A. Wood 0001	ASR: Adaptive Selective Replication for CMP Caches.	MICRO	2006	DBLP DOI BibTeX RDF
34	Hee Seo, Seon Wook Kim	OpenMP Directive Extension for BlackFin 561 Dual Core Processor.	CIT	2006	DBLP DOI BibTeX RDF
34	Mario Donato Marino	32-core CMP with multi-sliced L2: 2 and 4 cores sharing a L2 slice.	SBAC-PAD	2006	DBLP DOI BibTeX RDF
34	Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz, T. N. Vijaykumar	Transient-Fault Recovery for Chip Multiprocessors.	ISCA	2003	DBLP DOI BibTeX RDF
31	Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das	Coordinated power management of voltage islands in CMPs.	SIGMETRICS	2010	DBLP DOI BibTeX RDF	chip multiprocessors (CMP), control theory, GALs, DVFs
31	Jingtong Hu, Chun Jason Xue, Wei-Che Tseng, Yi He 0001, Meikang Qiu, Edwin Hsing-Mean Sha	Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation.	DAC	2010	DBLP DOI BibTeX RDF	data recomputation, CMP, flash memory, data migration, phase change memory, SPM, non-volatile memory
31	Moinuddin K. Qureshi	Adaptive Spill-Receive for robust high-performance caching in CMPs.	HPCA	2009	DBLP DOI BibTeX RDF
31	Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das	Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs.	HPCA	2009	DBLP DOI BibTeX RDF
31	Chris R. Jesshope, Mike Lankamp, Li Zhang 0034	Evaluating CMPs and Their Memory Architecture.	ARCS	2009	DBLP DOI BibTeX RDF
31	Suk-Bok Lee, Sai-Wang Tam, Ioannis Pefkianakis, Songwu Lu, M. Frank Chang, Chuanxiong Guo, Glenn Reinman, Chunyi Peng 0001, Mishali Naik, Lixia Zhang 0001, Jason Cong	A scalable micro wireless interconnect structure for CMPs.	MobiCom	2009	DBLP DOI BibTeX RDF	on-chip wireless interconnection network, chip multiprocessors
31	Daniel Sánchez 0004, Juan L. Aragón, José M. García 0001	REPAS: Reliable Execution for Parallel ApplicationS in Tiled-CMPs.	Euro-Par	2009	DBLP DOI BibTeX RDF
31	Joseph Sloan, Rakesh Kumar 0002	Towards scalable reliability frameworks for error prone CMPs.	CASES	2009	DBLP DOI BibTeX RDF	dynamic constitution, in-network fault tolerance
31	Matthew A. Watkins, Mark J. Cianchetti, David H. Albonesi	Shared reconfigurable architectures for CMPS.	FPL	2008	DBLP DOI BibTeX RDF
31	Cor Meenderinck, Ben H. H. Juurlink	(When) Will CMPs Hit the Power Wall?.	Euro-Par Workshops	2008	DBLP DOI BibTeX RDF
31	Mahmut T. Kandemir, Ozcan Ozturk 0001	Software-directed combined cpu/link voltage scaling fornoc-based cmps.	SIGMETRICS	2008	DBLP DOI BibTeX RDF	compiler, CMP, NoC, voltage scaling, cpu, communication link
31	Yang Ding, Mahmut T. Kandemir, Padma Raghavan, Mary Jane Irwin	A helper thread based EDP reduction scheme for adapting application execution in CMPs.	IPDPS	2008	DBLP DOI BibTeX RDF
31	Hongbo Zeng, Jun Wang, Ge Zhang 0007, Weiwu Hu	An interconnect-aware power efficient cache coherence protocol for CMPs.	IPDPS	2008	DBLP DOI BibTeX RDF
31	Antonio Flores, Manuel E. Acacio, Juan L. Aragón	Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs.	ICPP	2008	DBLP DOI BibTeX RDF
31	M. Aater Suleman, Moinuddin K. Qureshi, Yale N. Patt	Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs.	ASPLOS	2008	DBLP DOI BibTeX RDF	synchronization, CMP, bandwidth, multi-threaded
31	Mahmut T. Kandemir	Data locality enhancement for CMPs.	ICCAD	2007	DBLP DOI BibTeX RDF
31	Ozcan Ozturk 0001, Mahmut T. Kandemir, Seung Woo Son 0001	An ilp based approach to reducing energy consumption in nocbased CMPS.	ISLPED	2007	DBLP DOI BibTeX RDF	power aware compiler and operating system design
31	Shimin Chen, Phillip B. Gibbons, Michael Kozuch, Vasileios Liaskovitis, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Todd C. Mowry, Chris Wilkerson	Scheduling threads for constructive cache sharing on CMPs.	SPAA	2007	DBLP DOI BibTeX RDF	constructive cache sharing, parallel depth first, thread granularity, working set profiling, chip multiprocessors, scheduling algorithms, work stealing
31	Lisa R. Hsu, Steven K. Reinhardt, Ravishankar R. Iyer 0001, Srihari Makineni	Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource.	PACT	2006	DBLP DOI BibTeX RDF	performance, cache, multiprocessor, partitioning
31	Lisa R. Hsu, Ravishankar R. Iyer 0001, Srihari Makineni, Steven K. Reinhardt, Donald Newell	Exploring the cache design space for large scale CMPs.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
31	Chun Liu 0001, Anand Sivasubramaniam, Mahmut T. Kandemir, Mary Jane Irwin	Exploiting Barriers to Optimize Power Consumption of CMPs.	IPDPS	2005	DBLP DOI BibTeX RDF
26	Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su	A hyperscalar multi-core architecture.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	cmps, dynamic multi-core chips, reconfigurable multi-core architectures, chip multiprocessors
26	Ke Pei, Gang Zhang, Chang Qing	OS-Level IPC Implementation in Complementary Multi-processor Systems.	APWCS	2010	DBLP DOI BibTeX RDF	IPC Interface, HPI, CMPS, TMS320DM642
26	Dawid Zydek, Henry Selvaraj	Processor Allocation Problem for NoC-Based Chip Multiprocessors.	ITNG	2009	DBLP DOI BibTeX RDF	allocation algorithms, CMPs, NoC, hardware implementation, scheduling techniques
26	Michael R. Marty, Mark D. Hill	Virtual Hierarchies.	IEEE Micro	2008	DBLP DOI BibTeX RDF	virtual hierarchies, virtual machines, partitioning, chip multiprocessors (CMPs), multicore, cache coherence, server consolidation, space sharing
26	Michael R. Marty, Mark D. Hill	Virtual hierarchies to support server consolidation.	ISCA	2007	DBLP DOI BibTeX RDF	virtual machines, partitioning, chip multiprocessors (CMPs), multicore, memory hierarchies, cache coherence, server consolidation
23	Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson	Energy-efficient redundant execution for chip multiprocessors.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	redundant execution, microarchitecture, transient faults, permanent faults
23	Abhishek Bhattacharjee, Margaret Martonosi	Inter-core cooperative TLB for chip multiprocessors.	ASPLOS	2010	DBLP DOI BibTeX RDF	parallelism, prefetching, translation lookaside buffer
23	Xiaoxia Wu, Guangyu Sun 0003, Xiangyu Dong, Reetuparna Das, Yuan Xie 0001, Chita R. Das, Jian Li 0059	Cost-driven 3D integration with interconnect layers.	DAC	2010	DBLP DOI BibTeX RDF	interconnect service layer, three-dimensional integrated circuit, network-on-chip
23	Cor Meenderinck, Arnaldo Azevedo, Ben H. H. Juurlink, Mauricio Alvarez 0001, Alex Ramírez	Parallel Scalability of Video Decoders.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Scalability, Parallel processing, Chip multiprocessors, H.264, Video codecs
23	Andrew DeOrio, Ilya Wagner, Valeria Bertacco	Dacota: Post-silicon validation of the memory subsystem in multi-core designs.	HPCA	2009	DBLP DOI BibTeX RDF
23	Magnus Jahre, Marius Grannæs, Lasse Natvig	A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures.	HPCC	2009	DBLP DOI BibTeX RDF
23	Shirish Bahirat, Sudeep Pasricha	Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	photonic interconnect, network-on-chip, chip multiprocessor
23	Young Hoon Kang, Jeff Sondeen, Jeffrey T. Draper	Multicast routing with dynamic packet fragmentation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	on-chip router, interconnection network, NoC
23	Assaf Shacham, Keren Bergman, Luca P. Carloni	Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
23	Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon C. Steely Jr., Joel S. Emer	Adaptive insertion policies for managing shared caches.	PACT	2008	DBLP DOI BibTeX RDF	set dueling, shared cache, replacement, cache partitioning
23	Noel Eisley, Li-Shiuan Peh, Li Shang	Leveraging on-chip networks for data cache migration in chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	network-driven computing, interconnection network, CMP, chip-multiprocessor, migration
23	Ricardo Fernández Pascual, José M. García 0001, Manuel E. Acacio, José Duato	A fault-tolerant directory-based cache coherence protocol for CMP architectures.	DSN	2008	DBLP DOI BibTeX RDF
23	Ramazan Bitirgen, Engin Ipek, José F. Martínez	Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach.	MICRO	2008	DBLP DOI BibTeX RDF
23	Easwaran Raman, Guilherme Ottoni, Arun Raman, Matthew J. Bridges, David I. August	Parallel-stage decoupled software pipelining.	CGO	2008	DBLP DOI BibTeX RDF	doall, dswp, tlp, automatic parallelization, multi-core architectures, pipelined parallelism
23	Rui Gong, Kui Dai, Zhiying Wang 0003	Transient Fault Recovery on Chip Multiprocessor based on Dual Core Redundancy and Context Saving.	ICYCS	2008	DBLP DOI BibTeX RDF
23	Rajdeep Bhowmik, Chaitali Gupta, Madhusudhan Govindaraju, Aneesh Aggarwal	Optimizing XML processing for grid applications using an emulation framework.	IPDPS	2008	DBLP DOI BibTeX RDF
23	Christian Bienia, Sanjeev Kumar, Kai Li 0001	PARSEC vs. SPLASH-2: A quantitative comparison of two multithreaded benchmark suites on Chip-Multiprocessors.	IISWC	2008	DBLP DOI BibTeX RDF
23	Abu Saad Papa, Madhu Mutyam	Power management of variation aware chip multiprocessors.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	chipmulti-processor, process variation, power-aware, adaptive voltage scaling
23	Rui Gong, Kui Dai, Zhiying Wang 0003	Transient Fault Tolerance on Chip Multiprocessor Based on Dual and Triple Core Redundancy.	PRDC	2008	DBLP DOI BibTeX RDF
23	Hui Wang, Sandeep Baldawa, Rama Sangireddy	Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures.	VLSI Design	2008	DBLP DOI BibTeX RDF
23	Michele Petracca, Benjamin G. Lee, Keren Bergman, Luca P. Carloni	Design Exploration of Optical Interconnection Networks for Chip Multiprocessors.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	Networks-on-Chip, Interconnection, Chip Multiprocessors, Optics
23	Shekhar Srikantaiah, Mahmut T. Kandemir, Mary Jane Irwin	Adaptive set pinning: managing shared caches in chip multiprocessors.	ASPLOS	2008	DBLP DOI BibTeX RDF	inter-processor, intra-processor, set pinning, CMP, shared cache
23	Chen-Yong Cher, Michael Gschwind	Cell GC: using the cell synergistic processor as a garbage collection coprocessor.	VEE	2008	DBLP DOI BibTeX RDF	BDW, SPU, explicitly managed memory hierarchies, local store, garbage collection, accelerator, SPE, coprocessor, cell, mark-sweep
23	Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun	A practical FPGA-based framework for novel CMP research.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA-based emulation, transactional memory, chip multi-processor
23	Guilherme Ottoni, David I. August	Global Multi-Threaded Instruction Scheduling.	MICRO	2007	DBLP DOI BibTeX RDF
23	Antonio Flores, Juan L. Aragón, Manuel E. Acacio	Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network.	HiPC	2007	DBLP DOI BibTeX RDF	Heterogeneus On-Chip Interconnection Network, Chip-Multiprocessor, Energy-Efficient Architectures, Parallel Scientific Applications