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Publication years (Num. hits)
1988-2004 (18) 2005 (20) 2006 (38) 2007 (61) 2008 (58) 2009 (61) 2010 (43) 2011 (34) 2012 (24) 2013 (23) 2014 (19) 2015-2016 (33) 2017-2018 (20) 2019-2022 (16) 2023 (1)
Publication types (Num. hits)
article(100) inproceedings(365) phdthesis(4)
Venues (Conferences, Journals, ...)
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The graphs summarize 391 occurrences of 212 keywords

Results
Found 469 publication records. Showing 469 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
99Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar Optimizing Replication, Communication, and Capacity Allocation in CMPs. Search on Bibsonomy ISCA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
80Ian M. Bell, Nabil Hasasneh, Chris R. Jesshope Supporting Microthread Scheduling and Synchronisation in CMPs. Search on Bibsonomy Int. J. Parallel Program. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Microgrids, microthreads, schedulers, CMPs, register files
80James Laudon, Lawrence Spracklen The Coming Wave of Multithreaded Chip Multiprocessors. Search on Bibsonomy Int. J. Parallel Program. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF performance, parallel programming, multithreading, Chip multiprocessing
68Sungjune Youn, Hyunhee Kim, Jihong Kim 0001 A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches. Search on Bibsonomy ISLPED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF chip multiprocessors (CMPS), performance, embedded systems, architecture, low-power, L2 cache
68Dmitry G. Korzun, Andrei V. Gurtov A local equilibrium model for P2P resource ranking. Search on Bibsonomy SIGMETRICS Perform. Evaluation Rev. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
68Bill Lin 0001, Jun (Jim) Xu, Nan Hua, Hao Wang 0006, Haiquan (Chuck) Zhao A randomized interleaved DRAM architecture for the maintenance of exact statistics counters. Search on Bibsonomy SIGMETRICS Perform. Evaluation Rev. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
68Sipat Triukose, Zhihua Wen, Michael Rabinovich Content delivery networks: how big is big enough? Search on Bibsonomy SIGMETRICS Perform. Evaluation Rev. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
68Alma Riska, Erik Riedel Evaluation of disk-level workloads at different time scales. Search on Bibsonomy SIGMETRICS Perform. Evaluation Rev. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
61Jianwei Chen, Murali Annavaram, Michel Dubois 0001 SlackSim: a platform for parallel simulations of CMPs on CMPs. Search on Bibsonomy SIGMETRICS Perform. Evaluation Rev. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
57José L. Abellán, Juan Fernández 0001, Manuel E. Acacio Efficient and scalable barrier synchronization for many-core CMPs. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2010 DBLP  DOI  BibTeX  RDF g-line-based barrier synchronization, global interconnection lines, many-core cmps, s-csma technique
57Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar 0002 A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
53Hongbo Zeng, Kun Huang, Ming Wu, Weiwu Hu Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
53Chun Liu 0001, Anand Sivasubramaniam, Mahmut T. Kandemir, Mary Jane Irwin Enhancing L2 organization for CMPs with a center cell. Search on Bibsonomy IPDPS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
45Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan Compiler directed network-on-chip reliability enhancement for chip multiprocessors. Search on Bibsonomy LCTES The full citation details ... 2010 DBLP  DOI  BibTeX  RDF reliability, compiler, noc, chip multiprocessors
45Hyunhee Kim, Jung Ho Ahn, Jihong Kim 0001 Replication-aware leakage management in chip multiprocessors with private L2 cache. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF leakage power management, chip multiprocessors, L2 caches
45Seung Woo Son 0001, Mahmut T. Kandemir, Mustafa Karaköy, Dhruva R. Chakrabarti A compiler-directed data prefetching scheme for chip multiprocessors. Search on Bibsonomy PPoPP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF compiler, chip multiprocessors, prefetching, helper thread
45Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, Russ Joseph Process variation characterization of chip-level multiprocessors. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF software, process variation, characterization
45Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger Multitasking workload scheduling on flexible-core chip multiprocessors. Search on Bibsonomy PACT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF flexible cores, multitask scheduling, multicore architectures
45Mario Donato Marino L2-Cache Hierarchical Organizations for Multi-core Architectures. Search on Bibsonomy ISPA Workshops The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
45Vasileios Liaskovitis, Shimin Chen, Phillip B. Gibbons, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Michael Kozuch, Todd C. Mowry, Chris Wilkerson Parallel depth first vs. work stealing schedulers on CMP architectures. Search on Bibsonomy SPAA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF scheduling, caches, chip multiprocessors
45Julia Chen, Philo Juang, Kevin Ko, Gilberto Contreras, David Penry, Ram Rangan, Adam Stoler, Li-Shiuan Peh, Margaret Martonosi Hardware-modulated parallelism in chip multiprocessors. Search on Bibsonomy SIGARCH Comput. Archit. News The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
45Bradford M. Beckmann, David A. Wood 0001 Managing Wire Delay in Large Chip-Multiprocessor Caches. Search on Bibsonomy MICRO The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
45David P. Anderson, Ron Kuivila A System for Computer Music Performance. Search on Bibsonomy ACM Trans. Comput. Syst. The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
42Dan Gibson, David A. Wood 0001 Forwardflow: a scalable core for power-constrained CMPs. Search on Bibsonomy ISCA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF scalable core, chip multiprocessor (cmp), power
42Gilles Pokam, Cristiano Pereira, Klaus Danne, Rolf Kassa, Ali-Reza Adl-Tabatabai Architecting a chunk-based memory race recorder in modern CMPs. Search on Bibsonomy MICRO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF memory race recorder, determinism, deterministic replay
42Guangyu Sun 0003, Xiangyu Dong, Yuan Xie 0001, Jian Li 0059, Yiran Chen 0001 A novel architecture of the 3D stacked MRAM L2 cache for CMPs. Search on Bibsonomy HPCA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
42Alberto Ros 0001, Manuel E. Acacio, José M. García 0001 Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs. Search on Bibsonomy APPT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
42Major Bhadauria, Vincent M. Weaver, Sally A. McKee Accomodating Diversity in CMPs with Heterogeneous Frequencies. Search on Bibsonomy HiPEAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
42Mahmut T. Kandemir, Ozcan Ozturk 0001, Sai Prashanth Muralidhara Dynamic thread and data mapping for NoC based CMPs. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF mapping, dynamic, CMP, thread, NoC, data
42Christian Fensch, Marcelo Cintra An OS-based alternative to full hardware coherence on tiled CMPs. Search on Bibsonomy HPCA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
42Jaehyuk Huh 0001, Doug Burger, Stephen W. Keckler Exploring the Design Space of Future CMPs. Search on Bibsonomy IEEE PACT The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
39Jianwei Chen, Lakshmi Kumar Dabbiru, Daniel Wong 0001, Murali Annavaram, Michel Dubois 0001 Adaptive and Speculative Slack Simulations of CMPs on CMPs. Search on Bibsonomy MICRO The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
39Jianwei Chen, Murali Annavaram, Michel Dubois 0001 SlackSim: a platform for parallel simulations of CMPs on CMPs. Search on Bibsonomy SIGARCH Comput. Archit. News The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
34Xiang Zhang, Ahmed Louri A multilayer nanophotonic interconnection network for on-chip many-core communications. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF interconnection networks, CMP, 3D, silicon photonics
34Shekhar Srikantaiah, Mahmut T. Kandemir, Qian Wang SHARP control: controlled shared cache management in chip multiprocessors. Search on Bibsonomy MICRO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
34Mahmut T. Kandemir, Sai Prashanth Muralidhara, Sri Hari Krishna Narayanan, Yuanrui Zhang, Ozcan Ozturk 0001 Optimizing shared cache behavior of chip multiprocessors. Search on Bibsonomy MICRO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
34Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick, Russ Joseph Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
34Sevin Fide, Stephen F. Jenks Architecture optimizations for synchronization and communication on chip multiprocessors. Search on Bibsonomy IPDPS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
34Lars Arge, Michael T. Goodrich, Michael J. Nelson 0002, Nodari Sitchinava Fundamental parallel algorithms for private-cache chip multiprocessors. Search on Bibsonomy SPAA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF parallel external memory, pem, private-cache cmp
34Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
34John Cieslewicz, Kenneth A. Ross, Ioannis Giannakakis Parallel buffers for chip multiprocessors. Search on Bibsonomy DaMoN The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
34Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya Power reduction of chip multi-processors using shared resource control cooperating with DVFS. Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
34Weiwu Hu, Rui Hou, Jun-Hua Xiao, Long-Bin Zhang High Performance General-Purpose Microprocessors: Past and Future. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF high performance general-purpose microprocessor, Godson processor, chip multiprocessors, instruction level parallelism, thread level parallelism, data level parallelism
34Gregory Buehrer, Srinivasan Parthasarathy 0001, Yen-Kuang Chen Adaptive Parallel Graph Mining for CMP Architectures. Search on Bibsonomy ICDM The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Bradford M. Beckmann, Michael R. Marty, David A. Wood 0001 ASR: Adaptive Selective Replication for CMP Caches. Search on Bibsonomy MICRO The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Hee Seo, Seon Wook Kim OpenMP Directive Extension for BlackFin 561 Dual Core Processor. Search on Bibsonomy CIT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Mario Donato Marino 32-core CMP with multi-sliced L2: 2 and 4 cores sharing a L2 slice. Search on Bibsonomy SBAC-PAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz, T. N. Vijaykumar Transient-Fault Recovery for Chip Multiprocessors. Search on Bibsonomy ISCA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
31Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das Coordinated power management of voltage islands in CMPs. Search on Bibsonomy SIGMETRICS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF chip multiprocessors (CMP), control theory, GALs, DVFs
31Jingtong Hu, Chun Jason Xue, Wei-Che Tseng, Yi He 0001, Meikang Qiu, Edwin Hsing-Mean Sha Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF data recomputation, CMP, flash memory, data migration, phase change memory, SPM, non-volatile memory
31Moinuddin K. Qureshi Adaptive Spill-Receive for robust high-performance caching in CMPs. Search on Bibsonomy HPCA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
31Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. Search on Bibsonomy HPCA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
31Chris R. Jesshope, Mike Lankamp, Li Zhang 0034 Evaluating CMPs and Their Memory Architecture. Search on Bibsonomy ARCS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
31Suk-Bok Lee, Sai-Wang Tam, Ioannis Pefkianakis, Songwu Lu, M. Frank Chang, Chuanxiong Guo, Glenn Reinman, Chunyi Peng 0001, Mishali Naik, Lixia Zhang 0001, Jason Cong A scalable micro wireless interconnect structure for CMPs. Search on Bibsonomy MobiCom The full citation details ... 2009 DBLP  DOI  BibTeX  RDF on-chip wireless interconnection network, chip multiprocessors
31Daniel Sánchez 0004, Juan L. Aragón, José M. García 0001 REPAS: Reliable Execution for Parallel ApplicationS in Tiled-CMPs. Search on Bibsonomy Euro-Par The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
31Joseph Sloan, Rakesh Kumar 0002 Towards scalable reliability frameworks for error prone CMPs. Search on Bibsonomy CASES The full citation details ... 2009 DBLP  DOI  BibTeX  RDF dynamic constitution, in-network fault tolerance
31Matthew A. Watkins, Mark J. Cianchetti, David H. Albonesi Shared reconfigurable architectures for CMPS. Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
31Cor Meenderinck, Ben H. H. Juurlink (When) Will CMPs Hit the Power Wall?. Search on Bibsonomy Euro-Par Workshops The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
31Mahmut T. Kandemir, Ozcan Ozturk 0001 Software-directed combined cpu/link voltage scaling fornoc-based cmps. Search on Bibsonomy SIGMETRICS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF compiler, CMP, NoC, voltage scaling, cpu, communication link
31Yang Ding, Mahmut T. Kandemir, Padma Raghavan, Mary Jane Irwin A helper thread based EDP reduction scheme for adapting application execution in CMPs. Search on Bibsonomy IPDPS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
31Hongbo Zeng, Jun Wang, Ge Zhang 0007, Weiwu Hu An interconnect-aware power efficient cache coherence protocol for CMPs. Search on Bibsonomy IPDPS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
31Antonio Flores, Manuel E. Acacio, Juan L. Aragón Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs. Search on Bibsonomy ICPP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
31M. Aater Suleman, Moinuddin K. Qureshi, Yale N. Patt Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs. Search on Bibsonomy ASPLOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF synchronization, CMP, bandwidth, multi-threaded
31Mahmut T. Kandemir Data locality enhancement for CMPs. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
31Ozcan Ozturk 0001, Mahmut T. Kandemir, Seung Woo Son 0001 An ilp based approach to reducing energy consumption in nocbased CMPS. Search on Bibsonomy ISLPED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF power aware compiler and operating system design
31Shimin Chen, Phillip B. Gibbons, Michael Kozuch, Vasileios Liaskovitis, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Todd C. Mowry, Chris Wilkerson Scheduling threads for constructive cache sharing on CMPs. Search on Bibsonomy SPAA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF constructive cache sharing, parallel depth first, thread granularity, working set profiling, chip multiprocessors, scheduling algorithms, work stealing
31Lisa R. Hsu, Steven K. Reinhardt, Ravishankar R. Iyer 0001, Srihari Makineni Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource. Search on Bibsonomy PACT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF performance, cache, multiprocessor, partitioning
31Lisa R. Hsu, Ravishankar R. Iyer 0001, Srihari Makineni, Steven K. Reinhardt, Donald Newell Exploring the cache design space for large scale CMPs. Search on Bibsonomy SIGARCH Comput. Archit. News The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
31Chun Liu 0001, Anand Sivasubramaniam, Mahmut T. Kandemir, Mary Jane Irwin Exploiting Barriers to Optimize Power Consumption of CMPs. Search on Bibsonomy IPDPS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
26Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su A hyperscalar multi-core architecture. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2010 DBLP  DOI  BibTeX  RDF cmps, dynamic multi-core chips, reconfigurable multi-core architectures, chip multiprocessors
26Ke Pei, Gang Zhang, Chang Qing OS-Level IPC Implementation in Complementary Multi-processor Systems. Search on Bibsonomy APWCS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF IPC Interface, HPI, CMPS, TMS320DM642
26Dawid Zydek, Henry Selvaraj Processor Allocation Problem for NoC-Based Chip Multiprocessors. Search on Bibsonomy ITNG The full citation details ... 2009 DBLP  DOI  BibTeX  RDF allocation algorithms, CMPs, NoC, hardware implementation, scheduling techniques
26Michael R. Marty, Mark D. Hill Virtual Hierarchies. Search on Bibsonomy IEEE Micro The full citation details ... 2008 DBLP  DOI  BibTeX  RDF virtual hierarchies, virtual machines, partitioning, chip multiprocessors (CMPs), multicore, cache coherence, server consolidation, space sharing
26Michael R. Marty, Mark D. Hill Virtual hierarchies to support server consolidation. Search on Bibsonomy ISCA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF virtual machines, partitioning, chip multiprocessors (CMPs), multicore, memory hierarchies, cache coherence, server consolidation
23Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson Energy-efficient redundant execution for chip multiprocessors. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF redundant execution, microarchitecture, transient faults, permanent faults
23Abhishek Bhattacharjee, Margaret Martonosi Inter-core cooperative TLB for chip multiprocessors. Search on Bibsonomy ASPLOS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF parallelism, prefetching, translation lookaside buffer
23Xiaoxia Wu, Guangyu Sun 0003, Xiangyu Dong, Reetuparna Das, Yuan Xie 0001, Chita R. Das, Jian Li 0059 Cost-driven 3D integration with interconnect layers. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF interconnect service layer, three-dimensional integrated circuit, network-on-chip
23Cor Meenderinck, Arnaldo Azevedo, Ben H. H. Juurlink, Mauricio Alvarez 0001, Alex Ramírez Parallel Scalability of Video Decoders. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Scalability, Parallel processing, Chip multiprocessors, H.264, Video codecs
23Andrew DeOrio, Ilya Wagner, Valeria Bertacco Dacota: Post-silicon validation of the memory subsystem in multi-core designs. Search on Bibsonomy HPCA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
23Magnus Jahre, Marius Grannæs, Lasse Natvig A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures. Search on Bibsonomy HPCC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
23Shirish Bahirat, Sudeep Pasricha Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors. Search on Bibsonomy CODES+ISSS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF photonic interconnect, network-on-chip, chip multiprocessor
23Young Hoon Kang, Jeff Sondeen, Jeffrey T. Draper Multicast routing with dynamic packet fragmentation. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF on-chip router, interconnection network, NoC
23Assaf Shacham, Keren Bergman, Luca P. Carloni Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
23Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon C. Steely Jr., Joel S. Emer Adaptive insertion policies for managing shared caches. Search on Bibsonomy PACT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF set dueling, shared cache, replacement, cache partitioning
23Noel Eisley, Li-Shiuan Peh, Li Shang Leveraging on-chip networks for data cache migration in chip multiprocessors. Search on Bibsonomy PACT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF network-driven computing, interconnection network, CMP, chip-multiprocessor, migration
23Ricardo Fernández Pascual, José M. García 0001, Manuel E. Acacio, José Duato A fault-tolerant directory-based cache coherence protocol for CMP architectures. Search on Bibsonomy DSN The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
23Ramazan Bitirgen, Engin Ipek, José F. Martínez Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach. Search on Bibsonomy MICRO The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
23Easwaran Raman, Guilherme Ottoni, Arun Raman, Matthew J. Bridges, David I. August Parallel-stage decoupled software pipelining. Search on Bibsonomy CGO The full citation details ... 2008 DBLP  DOI  BibTeX  RDF doall, dswp, tlp, automatic parallelization, multi-core architectures, pipelined parallelism
23Rui Gong, Kui Dai, Zhiying Wang 0003 Transient Fault Recovery on Chip Multiprocessor based on Dual Core Redundancy and Context Saving. Search on Bibsonomy ICYCS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
23Rajdeep Bhowmik, Chaitali Gupta, Madhusudhan Govindaraju, Aneesh Aggarwal Optimizing XML processing for grid applications using an emulation framework. Search on Bibsonomy IPDPS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
23Christian Bienia, Sanjeev Kumar, Kai Li 0001 PARSEC vs. SPLASH-2: A quantitative comparison of two multithreaded benchmark suites on Chip-Multiprocessors. Search on Bibsonomy IISWC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
23Abu Saad Papa, Madhu Mutyam Power management of variation aware chip multiprocessors. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF chipmulti-processor, process variation, power-aware, adaptive voltage scaling
23Rui Gong, Kui Dai, Zhiying Wang 0003 Transient Fault Tolerance on Chip Multiprocessor Based on Dual and Triple Core Redundancy. Search on Bibsonomy PRDC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
23Hui Wang, Sandeep Baldawa, Rama Sangireddy Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
23Michele Petracca, Benjamin G. Lee, Keren Bergman, Luca P. Carloni Design Exploration of Optical Interconnection Networks for Chip Multiprocessors. Search on Bibsonomy Hot Interconnects The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Networks-on-Chip, Interconnection, Chip Multiprocessors, Optics
23Shekhar Srikantaiah, Mahmut T. Kandemir, Mary Jane Irwin Adaptive set pinning: managing shared caches in chip multiprocessors. Search on Bibsonomy ASPLOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF inter-processor, intra-processor, set pinning, CMP, shared cache
23Chen-Yong Cher, Michael Gschwind Cell GC: using the cell synergistic processor as a garbage collection coprocessor. Search on Bibsonomy VEE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF BDW, SPU, explicitly managed memory hierarchies, local store, garbage collection, accelerator, SPE, coprocessor, cell, mark-sweep
23Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun A practical FPGA-based framework for novel CMP research. Search on Bibsonomy FPGA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF FPGA-based emulation, transactional memory, chip multi-processor
23Guilherme Ottoni, David I. August Global Multi-Threaded Instruction Scheduling. Search on Bibsonomy MICRO The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
23Antonio Flores, Juan L. Aragón, Manuel E. Acacio Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network. Search on Bibsonomy HiPC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Heterogeneus On-Chip Interconnection Network, Chip-Multiprocessor, Energy-Efficient Architectures, Parallel Scientific Applications
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