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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 391 occurrences of 212 keywords
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Results
Found 469 publication records. Showing 469 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
99 | Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar |
Optimizing Replication, Communication, and Capacity Allocation in CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005, Madison, Wisconsin, USA, pp. 357-368, 2005, IEEE Computer Society, 978-0-7695-2270-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
80 | Ian M. Bell, Nabil Hasasneh, Chris R. Jesshope |
Supporting Microthread Scheduling and Synchronisation in CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 34(4), pp. 343-381, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Microgrids, microthreads, schedulers, CMPs, register files |
80 | James Laudon, Lawrence Spracklen |
The Coming Wave of Multithreaded Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 35(3), pp. 299-330, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
performance, parallel programming, multithreading, Chip multiprocessing |
68 | Sungjune Youn, Hyunhee Kim, Jihong Kim 0001 |
A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 56-61, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
chip multiprocessors (CMPS), performance, embedded systems, architecture, low-power, L2 cache |
68 | Dmitry G. Korzun, Andrei V. Gurtov |
A local equilibrium model for P2P resource ranking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS Perform. Evaluation Rev. ![In: SIGMETRICS Perform. Evaluation Rev. 37(2), pp. 27-29, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
68 | Bill Lin 0001, Jun (Jim) Xu, Nan Hua, Hao Wang 0006, Haiquan (Chuck) Zhao |
A randomized interleaved DRAM architecture for the maintenance of exact statistics counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS Perform. Evaluation Rev. ![In: SIGMETRICS Perform. Evaluation Rev. 37(2), pp. 53-54, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
68 | Sipat Triukose, Zhihua Wen, Michael Rabinovich |
Content delivery networks: how big is big enough? ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS Perform. Evaluation Rev. ![In: SIGMETRICS Perform. Evaluation Rev. 37(2), pp. 59-60, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
68 | Alma Riska, Erik Riedel |
Evaluation of disk-level workloads at different time scales. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS Perform. Evaluation Rev. ![In: SIGMETRICS Perform. Evaluation Rev. 37(2), pp. 67-68, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
61 | Jianwei Chen, Murali Annavaram, Michel Dubois 0001 |
SlackSim: a platform for parallel simulations of CMPs on CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS Perform. Evaluation Rev. ![In: SIGMETRICS Perform. Evaluation Rev. 37(2), pp. 77-78, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
57 | José L. Abellán, Juan Fernández 0001, Manuel E. Acacio |
Efficient and scalable barrier synchronization for many-core CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 73-74, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
g-line-based barrier synchronization, global interconnection lines, many-core cmps, s-csma technique |
57 | Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar 0002 |
A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 726-735, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
53 | Hongbo Zeng, Kun Huang, Ming Wu, Weiwu Hu |
Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings, pp. 304-314, 2007, Springer, 978-3-540-74308-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
53 | Chun Liu 0001, Anand Sivasubramaniam, Mahmut T. Kandemir, Mary Jane Irwin |
Enhancing L2 organization for CMPs with a center cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
45 | Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan |
Compiler directed network-on-chip reliability enhancement for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems, LCTES 2010, Stockholm, Sweden, April 13-15, 2010, pp. 85-94, 2010, ACM, 978-1-60558-953-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
reliability, compiler, noc, chip multiprocessors |
45 | Hyunhee Kim, Jung Ho Ahn, Jihong Kim 0001 |
Replication-aware leakage management in chip multiprocessors with private L2 cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 135-140, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
leakage power management, chip multiprocessors, L2 caches |
45 | Seung Woo Son 0001, Mahmut T. Kandemir, Mustafa Karaköy, Dhruva R. Chakrabarti |
A compiler-directed data prefetching scheme for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2009, Raleigh, NC, USA, February 14-18, 2009, pp. 209-218, 2009, ACM, 978-1-60558-397-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
compiler, chip multiprocessors, prefetching, helper thread |
45 | Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, Russ Joseph |
Process variation characterization of chip-level multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 694-697, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
software, process variation, characterization |
45 | Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger |
Multitasking workload scheduling on flexible-core chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, Toronto, Ontario, Canada, October 25-29, 2008, pp. 187-196, 2008, ACM, 978-1-60558-282-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
flexible cores, multitask scheduling, multicore architectures |
45 | Mario Donato Marino |
L2-Cache Hierarchical Organizations for Multi-core Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA Workshops ![In: Frontiers of High Performance Computing and Networking - ISPA 2006 Workshops, ISPA 2006 International Workshops, FHPCN, XHPC, S-GRACE, GridGIS, HPC-GTP, PDCE, ParDMCom, WOMP, ISDF, and UPWN, Sorrento, Italy, December 4-7, 2006, Proceedings, pp. 74-83, 2006, Springer, 3-540-49860-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
45 | Vasileios Liaskovitis, Shimin Chen, Phillip B. Gibbons, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Michael Kozuch, Todd C. Mowry, Chris Wilkerson |
Parallel depth first vs. work stealing schedulers on CMP architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30 - August 2, 2006, pp. 330, 2006, ACM, 1-59593-452-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
scheduling, caches, chip multiprocessors |
45 | Julia Chen, Philo Juang, Kevin Ko, Gilberto Contreras, David Penry, Ram Rangan, Adam Stoler, Li-Shiuan Peh, Margaret Martonosi |
Hardware-modulated parallelism in chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 33(4), pp. 54-63, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Bradford M. Beckmann, David A. Wood 0001 |
Managing Wire Delay in Large Chip-Multiprocessor Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 4-8 December 2004, Portland, OR, USA, pp. 319-330, 2004, IEEE Computer Society, 0-7695-2126-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
45 | David P. Anderson, Ron Kuivila |
A System for Computer Music Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 8(1), pp. 56-82, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
42 | Dan Gibson, David A. Wood 0001 |
Forwardflow: a scalable core for power-constrained CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 14-25, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
scalable core, chip multiprocessor (cmp), power |
42 | Gilles Pokam, Cristiano Pereira, Klaus Danne, Rolf Kassa, Ali-Reza Adl-Tabatabai |
Architecting a chunk-based memory race recorder in modern CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 576-585, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
memory race recorder, determinism, deterministic replay |
42 | Guangyu Sun 0003, Xiangyu Dong, Yuan Xie 0001, Jian Li 0059, Yiran Chen 0001 |
A novel architecture of the 3D stacked MRAM L2 cache for CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 239-249, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Alberto Ros 0001, Manuel E. Acacio, José M. García 0001 |
Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings, pp. 11-27, 2009, Springer, 978-3-642-03643-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Major Bhadauria, Vincent M. Weaver, Sally A. McKee |
Accomodating Diversity in CMPs with Heterogeneous Frequencies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings, pp. 248-262, 2009, Springer, 978-3-540-92989-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Mahmut T. Kandemir, Ozcan Ozturk 0001, Sai Prashanth Muralidhara |
Dynamic thread and data mapping for NoC based CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 852-857, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
mapping, dynamic, CMP, thread, NoC, data |
42 | Christian Fensch, Marcelo Cintra |
An OS-based alternative to full hardware coherence on tiled CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA, pp. 355-366, 2008, IEEE Computer Society, 978-1-4244-2070-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
42 | Jaehyuk Huh 0001, Doug Burger, Stephen W. Keckler |
Exploring the Design Space of Future CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 8-12 September 2001, Barcelona, Spain, pp. 199-210, 2001, IEEE Computer Society, 0-7695-1363-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Jianwei Chen, Lakshmi Kumar Dabbiru, Daniel Wong 0001, Murali Annavaram, Michel Dubois 0001 |
Adaptive and Speculative Slack Simulations of CMPs on CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2010, 4-8 December 2010, Atlanta, Georgia, USA, pp. 523-534, 2010, IEEE Computer Society, 978-0-7695-4299-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
39 | Jianwei Chen, Murali Annavaram, Michel Dubois 0001 |
SlackSim: a platform for parallel simulations of CMPs on CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 37(2), pp. 20-29, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Xiang Zhang, Ahmed Louri |
A multilayer nanophotonic interconnection network for on-chip many-core communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 156-161, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
interconnection networks, CMP, 3D, silicon photonics |
34 | Shekhar Srikantaiah, Mahmut T. Kandemir, Qian Wang |
SHARP control: controlled shared cache management in chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 517-528, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Mahmut T. Kandemir, Sai Prashanth Muralidhara, Sri Hari Krishna Narayanan, Yuanrui Zhang, Ozcan Ozturk 0001 |
Optimizing shared cache behavior of chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 505-516, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick, Russ Joseph |
Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8), pp. 1479-1492, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Sevin Fide, Stephen F. Jenks |
Architecture optimizations for synchronization and communication on chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Lars Arge, Michael T. Goodrich, Michael J. Nelson 0002, Nodari Sitchinava |
Fundamental parallel algorithms for private-cache chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Munich, Germany, June 14-16, 2008, pp. 197-206, 2008, ACM, 978-1-59593-973-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
parallel external memory, pem, private-cache cmp |
34 | Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo |
Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(8), pp. 869-880, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | John Cieslewicz, Kenneth A. Ross, Ioannis Giannakakis |
Parallel buffers for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DaMoN ![In: Workshop on Data Management on New Hardware, DaMoN 2007, Beijing, China, June 15, 2007, pp. 2, 2007, ACM, 978-1-59593-772-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya |
Power reduction of chip multi-processors using shared resource control cooperating with DVFS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 615-622, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Weiwu Hu, Rui Hou, Jun-Hua Xiao, Long-Bin Zhang |
High Performance General-Purpose Microprocessors: Past and Future. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 21(5), pp. 631-640, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
high performance general-purpose microprocessor, Godson processor, chip multiprocessors, instruction level parallelism, thread level parallelism, data level parallelism |
34 | Gregory Buehrer, Srinivasan Parthasarathy 0001, Yen-Kuang Chen |
Adaptive Parallel Graph Mining for CMP Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDM ![In: Proceedings of the 6th IEEE International Conference on Data Mining (ICDM 2006), 18-22 December 2006, Hong Kong, China, pp. 97-106, 2006, IEEE Computer Society, 0-7695-2701-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Bradford M. Beckmann, Michael R. Marty, David A. Wood 0001 |
ASR: Adaptive Selective Replication for CMP Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA, pp. 443-454, 2006, IEEE Computer Society, 0-7695-2732-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Hee Seo, Seon Wook Kim |
OpenMP Directive Extension for BlackFin 561 Dual Core Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: Sixth International Conference on Computer and Information Technology (CIT 2006), 20-22 September 2006, Seoul, Korea, pp. 49, 2006, IEEE Computer Society, 0-7695-2687-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Mario Donato Marino |
32-core CMP with multi-sliced L2: 2 and 4 cores sharing a L2 slice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBAC-PAD ![In: 18th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2006), 17-20 October 2006, Ouro Preto, Minas Gerais, Brazil, pp. 141-150, 2006, IEEE Computer Society, 0-7695-2704-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz, T. N. Vijaykumar |
Transient-Fault Recovery for Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 98-109, 2003, IEEE Computer Society, 0-7695-1945-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das |
Coordinated power management of voltage islands in CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: SIGMETRICS 2010, Proceedings of the 2010 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, New York, New York, USA, 14-18 June 2010, pp. 359-360, 2010, ACM, 978-1-4503-0038-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
chip multiprocessors (CMP), control theory, GALs, DVFs |
31 | Jingtong Hu, Chun Jason Xue, Wei-Che Tseng, Yi He 0001, Meikang Qiu, Edwin Hsing-Mean Sha |
Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 350-355, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
data recomputation, CMP, flash memory, data migration, phase change memory, SPM, non-volatile memory |
31 | Moinuddin K. Qureshi |
Adaptive Spill-Receive for robust high-performance caching in CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 45-54, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das |
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 175-186, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Chris R. Jesshope, Mike Lankamp, Li Zhang 0034 |
Evaluating CMPs and Their Memory Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2009, 22nd International Conference, Delft, The Netherlands, March 10-13, 2009. Proceedings, pp. 246-257, 2009, Springer, 978-3-642-00453-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Suk-Bok Lee, Sai-Wang Tam, Ioannis Pefkianakis, Songwu Lu, M. Frank Chang, Chuanxiong Guo, Glenn Reinman, Chunyi Peng 0001, Mishali Naik, Lixia Zhang 0001, Jason Cong |
A scalable micro wireless interconnect structure for CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MobiCom ![In: Proceedings of the 15th Annual International Conference on Mobile Computing and Networking, MOBICOM 2009, Beijing, China, September 20-25, 2009, pp. 217-228, 2009, ACM, 978-1-60558-702-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
on-chip wireless interconnection network, chip multiprocessors |
31 | Daniel Sánchez 0004, Juan L. Aragón, José M. García 0001 |
REPAS: Reliable Execution for Parallel ApplicationS in Tiled-CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2009 Parallel Processing, 15th International Euro-Par Conference, Delft, The Netherlands, August 25-28, 2009. Proceedings, pp. 321-333, 2009, Springer, 978-3-642-03868-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Joseph Sloan, Rakesh Kumar 0002 |
Towards scalable reliability frameworks for error prone CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 261-270, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic constitution, in-network fault tolerance |
31 | Matthew A. Watkins, Mark J. Cianchetti, David H. Albonesi |
Shared reconfigurable architectures for CMPS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 299-304, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Cor Meenderinck, Ben H. H. Juurlink |
(When) Will CMPs Hit the Power Wall?. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par Workshops ![In: Euro-Par 2008 Workshops - Parallel Processing, VHPC 2008, UNICORE 2008, HPPC 2008, SGS 2008, PROPER 2008, ROIA 2008, and DPA 2008, Las Palmas de Gran Canaria, Spain, August 25-26, 2008, Revised Selected Papers, pp. 184-193, 2008, Springer, 978-3-642-00954-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Mahmut T. Kandemir, Ozcan Ozturk 0001 |
Software-directed combined cpu/link voltage scaling fornoc-based cmps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 2008 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2008, Annapolis, MD, USA, June 2-6, 2008, pp. 359-370, 2008, ACM, 978-1-60558-005-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
compiler, CMP, NoC, voltage scaling, cpu, communication link |
31 | Yang Ding, Mahmut T. Kandemir, Padma Raghavan, Mary Jane Irwin |
A helper thread based EDP reduction scheme for adapting application execution in CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-14, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Hongbo Zeng, Jun Wang, Ge Zhang 0007, Weiwu Hu |
An interconnect-aware power efficient cache coherence protocol for CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-11, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Antonio Flores, Manuel E. Acacio, Juan L. Aragón |
Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 2008 International Conference on Parallel Processing, ICPP 2008, September 8-12, 2008, Portland, Oregon, USA, pp. 295-303, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | M. Aater Suleman, Moinuddin K. Qureshi, Yale N. Patt |
Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2008, Seattle, WA, USA, March 1-5, 2008, pp. 277-286, 2008, ACM, 978-1-59593-958-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
synchronization, CMP, bandwidth, multi-threaded |
31 | Mahmut T. Kandemir |
Data locality enhancement for CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 155-159, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Ozcan Ozturk 0001, Mahmut T. Kandemir, Seung Woo Son 0001 |
An ilp based approach to reducing energy consumption in nocbased CMPS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 411-414, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
power aware compiler and operating system design |
31 | Shimin Chen, Phillip B. Gibbons, Michael Kozuch, Vasileios Liaskovitis, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Todd C. Mowry, Chris Wilkerson |
Scheduling threads for constructive cache sharing on CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2007: Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures, San Diego, California, USA, June 9-11, 2007, pp. 105-115, 2007, ACM, 978-1-59593-667-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
constructive cache sharing, parallel depth first, thread granularity, working set profiling, chip multiprocessors, scheduling algorithms, work stealing |
31 | Lisa R. Hsu, Steven K. Reinhardt, Ravishankar R. Iyer 0001, Srihari Makineni |
Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 13-22, 2006, ACM, 1-59593-264-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
performance, cache, multiprocessor, partitioning |
31 | Lisa R. Hsu, Ravishankar R. Iyer 0001, Srihari Makineni, Steven K. Reinhardt, Donald Newell |
Exploring the cache design space for large scale CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 33(4), pp. 24-33, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Chun Liu 0001, Anand Sivasubramaniam, Mahmut T. Kandemir, Mary Jane Irwin |
Exploiting Barriers to Optimize Power Consumption of CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su |
A hyperscalar multi-core architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 77-78, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
cmps, dynamic multi-core chips, reconfigurable multi-core architectures, chip multiprocessors |
26 | Ke Pei, Gang Zhang, Chang Qing |
OS-Level IPC Implementation in Complementary Multi-processor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APWCS ![In: 2010 Asia-Pacific Conference on Wearable Computing Systems, APWCS 2010, Shenzhen, China , 17-18 April 2010, pp. 74-77, 2010, IEEE Computer Society, 978-0-7695-4003-0. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
IPC Interface, HPI, CMPS, TMS320DM642 |
26 | Dawid Zydek, Henry Selvaraj |
Processor Allocation Problem for NoC-Based Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Sixth International Conference on Information Technology: New Generations, ITNG 2009, Las Vegas, Nevada, USA, 27-29 April 2009, pp. 96-101, 2009, IEEE Computer Society, 978-0-7695-3596-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
allocation algorithms, CMPs, NoC, hardware implementation, scheduling techniques |
26 | Michael R. Marty, Mark D. Hill |
Virtual Hierarchies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 28(1), pp. 99-109, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
virtual hierarchies, virtual machines, partitioning, chip multiprocessors (CMPs), multicore, cache coherence, server consolidation, space sharing |
26 | Michael R. Marty, Mark D. Hill |
Virtual hierarchies to support server consolidation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 46-56, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
virtual machines, partitioning, chip multiprocessors (CMPs), multicore, memory hierarchies, cache coherence, server consolidation |
23 | Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson |
Energy-efficient redundant execution for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 143-146, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
redundant execution, microarchitecture, transient faults, permanent faults |
23 | Abhishek Bhattacharjee, Margaret Martonosi |
Inter-core cooperative TLB for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2010, Pittsburgh, Pennsylvania, USA, March 13-17, 2010, pp. 359-370, 2010, ACM, 978-1-60558-839-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
parallelism, prefetching, translation lookaside buffer |
23 | Xiaoxia Wu, Guangyu Sun 0003, Xiangyu Dong, Reetuparna Das, Yuan Xie 0001, Chita R. Das, Jian Li 0059 |
Cost-driven 3D integration with interconnect layers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 150-155, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
interconnect service layer, three-dimensional integrated circuit, network-on-chip |
23 | Cor Meenderinck, Arnaldo Azevedo, Ben H. H. Juurlink, Mauricio Alvarez 0001, Alex Ramírez |
Parallel Scalability of Video Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(2), pp. 173-194, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Scalability, Parallel processing, Chip multiprocessors, H.264, Video codecs |
23 | Andrew DeOrio, Ilya Wagner, Valeria Bertacco |
Dacota: Post-silicon validation of the memory subsystem in multi-core designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 405-416, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Magnus Jahre, Marius Grannæs, Lasse Natvig |
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC ![In: 11th IEEE International Conference on High Performance Computing and Communications, HPCC 2009, 25-27 June 2009, Seoul, Korea, pp. 622-629, 2009, IEEE, 978-0-7695-3738-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Shirish Bahirat, Sudeep Pasricha |
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 129-136, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
photonic interconnect, network-on-chip, chip multiprocessor |
23 | Young Hoon Kang, Jeff Sondeen, Jeffrey T. Draper |
Multicast routing with dynamic packet fragmentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 113-116, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
on-chip router, interconnection network, NoC |
23 | Assaf Shacham, Keren Bergman, Luca P. Carloni |
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(9), pp. 1246-1260, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon C. Steely Jr., Joel S. Emer |
Adaptive insertion policies for managing shared caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, Toronto, Ontario, Canada, October 25-29, 2008, pp. 208-219, 2008, ACM, 978-1-60558-282-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
set dueling, shared cache, replacement, cache partitioning |
23 | Noel Eisley, Li-Shiuan Peh, Li Shang |
Leveraging on-chip networks for data cache migration in chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, Toronto, Ontario, Canada, October 25-29, 2008, pp. 197-207, 2008, ACM, 978-1-60558-282-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
network-driven computing, interconnection network, CMP, chip-multiprocessor, migration |
23 | Ricardo Fernández Pascual, José M. García 0001, Manuel E. Acacio, José Duato |
A fault-tolerant directory-based cache coherence protocol for CMP architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, pp. 267-276, 2008, IEEE Computer Society, 978-1-4244-2397-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Ramazan Bitirgen, Engin Ipek, José F. Martínez |
Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 318-329, 2008, IEEE Computer Society, 978-1-4244-2836-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Easwaran Raman, Guilherme Ottoni, Arun Raman, Matthew J. Bridges, David I. August |
Parallel-stage decoupled software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Sixth International Symposium on Code Generation and Optimization (CGO 2008), April 5-9, 2008, Boston, MA, USA, pp. 114-123, 2008, ACM, 978-1-59593-978-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
doall, dswp, tlp, automatic parallelization, multi-core architectures, pipelined parallelism |
23 | Rui Gong, Kui Dai, Zhiying Wang 0003 |
Transient Fault Recovery on Chip Multiprocessor based on Dual Core Redundancy and Context Saving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICYCS ![In: Proceedings of the 9th International Conference for Young Computer Scientists, ICYCS 2008, Zhang Jia Jie, Hunan, China, November 18-21, 2008, pp. 148-153, 2008, IEEE Computer Society, 978-0-7695-3398-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Rajdeep Bhowmik, Chaitali Gupta, Madhusudhan Govindaraju, Aneesh Aggarwal |
Optimizing XML processing for grid applications using an emulation framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-11, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Christian Bienia, Sanjeev Kumar, Kai Li 0001 |
PARSEC vs. SPLASH-2: A quantitative comparison of two multithreaded benchmark suites on Chip-Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IISWC ![In: 4th International Symposium on Workload Characterization (IISWC 2008), Seattle, Washington, USA, September 14-16, 2008, pp. 47-56, 2008, IEEE Computer Society, 978-1-4244-2778-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Abu Saad Papa, Madhu Mutyam |
Power management of variation aware chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 423-428, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
chipmulti-processor, process variation, power-aware, adaptive voltage scaling |
23 | Rui Gong, Kui Dai, Zhiying Wang 0003 |
Transient Fault Tolerance on Chip Multiprocessor Based on Dual and Triple Core Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008, 15-17 December 2008, Taipei, Taiwan, pp. 273-280, 2008, IEEE Computer Society, 978-0-7695-3448-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Hui Wang, Sandeep Baldawa, Rama Sangireddy |
Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 279-285, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Michele Petracca, Benjamin G. Lee, Keren Bergman, Luca P. Carloni |
Design Exploration of Optical Interconnection Networks for Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Interconnects ![In: 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 26-28 August 2008, Stanford, CA, USA, pp. 31-40, 2008, IEEE Computer Society, 978-0-7695-3380-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Networks-on-Chip, Interconnection, Chip Multiprocessors, Optics |
23 | Shekhar Srikantaiah, Mahmut T. Kandemir, Mary Jane Irwin |
Adaptive set pinning: managing shared caches in chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2008, Seattle, WA, USA, March 1-5, 2008, pp. 135-144, 2008, ACM, 978-1-59593-958-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
inter-processor, intra-processor, set pinning, CMP, shared cache |
23 | Chen-Yong Cher, Michael Gschwind |
Cell GC: using the cell synergistic processor as a garbage collection coprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VEE ![In: Proceedings of the 4th International Conference on Virtual Execution Environments, VEE 2008, Seattle, WA, USA, March 5-7, 2008, pp. 141-150, 2008, ACM, 978-1-59593-796-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
BDW, SPU, explicitly managed memory hierarchies, local store, garbage collection, accelerator, SPE, coprocessor, cell, mark-sweep |
23 | Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun |
A practical FPGA-based framework for novel CMP research. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 116-125, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA-based emulation, transactional memory, chip multi-processor |
23 | Guilherme Ottoni, David I. August |
Global Multi-Threaded Instruction Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA, pp. 56-68, 2007, IEEE Computer Society, 0-7695-3047-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Antonio Flores, Juan L. Aragón, Manuel E. Acacio |
Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2007, 14th International Conference, Goa, India, December 18-21, 2007, Proceedings, pp. 133-146, 2007, Springer, 978-3-540-77219-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Heterogeneus On-Chip Interconnection Network, Chip-Multiprocessor, Energy-Efficient Architectures, Parallel Scientific Applications |
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