Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
127 | Valeri Solovjev |
Refined CPLD Macrocell Architecture for the Effective FSM Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1102-, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
83 | Jae-Jin Kim, Hi-Seok Kim, Chi-Ho Lin |
A new techology mapping for CPLD under the time constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 235-238, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
feasible cluster, number of multi-level, technology mapping for CPLD, time constraint |
83 | Bernardo Kastrup, Arjan Bink, Jan Hoogerbrugge |
ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 92-, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
XPLA, compilers, static-analysis, computer-architecture, reconfigurable-computing, compiler-optimizations, hardware-acceleration, programmable-logic, CPLD, custom-instructions |
77 | Shi Yu Yan, Ji Zhou Li |
Research on the DDS' CPLD Control to Generate Special Band Signal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BMEI (2) ![In: Proceedings of the 2008 International Conference on BioMedical Engineering and Informatics, BMEI 2008, May 28-30, 2008, Sanya, Hainan, China - Volume 2, pp. 681-684, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
74 | Nikolay Kostadinov, Anelia Ivanova |
A VHDL training model of a processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CompSysTech ![In: Proceedings of the 2007 International Conference on Computer Systems and Technologies, CompSysTech 2007, Rousse, Bulgaria, June 14-15, 2007, pp. 124, 2007, ACM, 978-954-9641-50-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
CPLD implementation, VHDL model, processor, instruction set |
66 | Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang |
Performance-driven mapping for CPLD architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 39-47, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
PLA-style logic cells, FPGA, technology mapping, CPLD, delay optimization |
66 | Yasumasa Hayashi, Takashi Matsubara 0002, Yoshiaki Koga |
Implementation and evaluation for dependable bus control using CPLD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 2000 Pacific Rim International Symposium on Dependable Computing (PRDC 2000), 18-20 December 2000, Los Angeles, CA, USA, pp. 11-18, 2000, IEEE Computer Society, 0-7695-0975-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
phase control, dependable bus control, bus systems, dependable bus operations, bus phase control, reliability, dependability, sequential circuits, system buses, CPLD, asynchronous sequential logic, asynchronous sequential circuit |
60 | Faizal Arya Samman, Eniman Y. Syamsuddin |
Programmable fuzzy logic controller circuit on CPLD chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (2) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 561-564, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
57 | Pai-Shan Pa, C. M. Wu |
The New Design of Digital Servo Robot Controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIRA (2) ![In: Intelligent Robotics and Applications, First International Conference, ICIRA 2008, Wuhan, China, October 15-17, 2008 Proceedings, Part II, pp. 1105-1114, 2008, Springer, 978-3-540-88516-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Servo, Robot, Toy, CPLD, PWM, Single Chip |
57 | Mark Holland, Scott Hauck |
Improving performance and robustness of domain-specific CPLDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 50-59, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
computer-aided design, system-on-a-chip, reconfigurable logic, CPLD, sparse crossbar |
51 | Chun-Chieh Wang, Juhng-Perng Su |
Fuzzy Gain Scheduled Integral Control and Its Application to a Hovercraft Vessel with Uncertainties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICIC (1) ![In: First International Conference on Innovative Computing, Information and Control (ICICIC 2006), 30 August - 1 September 2006, Beijing, China, pp. 501-504, 2006, IEEE Computer Society, 0-7695-2616-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
51 | Zhifeng Diao, Dongxu Shen, Victor O. K. Li |
A channel-condition and packet-length dependent scheduler in wireless OFDM systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Fall (2) ![In: Proceedings of the 60th IEEE Vehicular Technology Conference, VTC Fall 2004, 26-29 September 2004, Los Angeles, CA, USA, pp. 1038-1042, 2004, IEEE. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
49 | Gerhard Grießnig, Roland Mader, Christian Steger, Reinhold Weiss |
Design and Implementation of Safety Functions on a Novel CPLD-Based Fail-Safe System Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 17th IEEE International Conference and Workshops on the Engineering of Computer-Based Systems, ECBS 2010, Oxford, England, UK, 22-26 March 2010, pp. 206-212, 2010, IEEE Computer Society, 978-0-7695-4005-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
safety-critical embedded system, fail-safe system, safety function, safety, CPLD, IEC 61508 |
43 | Junmei Zhang, Wenbin Li 0004, Chao Sa, Deming Wang, Dongxu Cui |
CPLD-based optimal control for wireless remote control pruning machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSCWD ![In: Proceedings of the 13th International Conference on Computers Supported Cooperative Work in Design, CSCWD 2009, April 22-24, 2009, Santiago, Chile, pp. 374-377, 2009, IEEE, 978-1-4244-3534-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
43 | Junmei Zhang, Wenbin Li 0004, Chao Sa, Deming Wang, Patrick S. K. Chua, F. L. Tan |
Development of a CPLD Based Wireless Remote Control System of Pruning Machine for Plantation Forest. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSCWD ![In: Proceedings of the 11th International Conference on Computer Supported Cooperative Work in Design, CSCWD 2007, April 26-28, 2007, Melbourne, Australia, pp. 1078-1081, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Dariusz Kania |
Two-Level Logic Synthesis on PAL-Based CPLD and FPGA Using Decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1278-1281, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
40 | Dimitrios Lymberopoulos, Nissanka Bodhi Priyantha, Feng Zhao 0001 |
mPlatform: a reconfigurable architecture and efficient data sharing mechanism for modular sensor nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSN ![In: Proceedings of the 6th International Conference on Information Processing in Sensor Networks, IPSN 2007, Cambridge, Massachusetts, USA, April 25-27, 2007, pp. 128-137, 2007, ACM, 978-1-59593-638-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
high speed data bus, reconfigurable sensor node, CPLD, modular architecture |
34 | Mark Holland, Scott Hauck |
Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2), pp. 291-295, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Dariusz Kania |
A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 152-155, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
logic synthesis, technology mapping, CPLDs |
34 | Dariusz Kania, Józef Kulisz, Adam Milik |
A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 114-121, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic |
Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 232-241, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
34 | K. K. Lee, D. F. Wong 0001 |
LRoute: a delay minimal router for hierarchical CPLDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 12-20, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
complex programmable logic devices, routing, hierarchical model, Lagrangian relaxation |
34 | Francisco Ibarra Picó, Sergio Cuenca-Asensi |
An Associative Neural Network and Its Special Purpose Pipeline Architecture in Image Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN (2) ![In: Engineering Applications of Bio-Inspired Artificial Neural Networks, International Work-Conference on Artificial and Natural Neural Networks, IWANN '99, Alicante, Spain, June 2-4, 1999, Proceedings, Volume II, pp. 95-106, 1999, Springer. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Topics Computer vision, real-time quality control, neural nets, texture recognition |
34 | James O. Hamblen, Gregory E. Ruhl |
Using the Altera UP-1 Board for Prototyping and VGA Video Display Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: IEEE International Conference on Microelectronic Systems Education, MSE 1999, Arlington, Virginia, USA, July 19-21, 1999, pp. 16-17, 1999, IEEE Computer Society, 0-7695-0312-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Valeri Solovjev, Mariusz Chyzy |
The Universal Algorithm for Fitting Targeted to Complex Programmable Logic Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1286-1289, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Alexander Barkalov 0001, Larysa Titarenko, Slawomir Chmielewski |
Design of CPLD-based mealy FSMs with counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 7th International Conference on Modern Circuits and Systems Technologies, MOCAST 2018, Thessaloniki, Greece, May 7-9, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-4788-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Hong Chen, Zhifan Du, Xin Liu, Yu Meng |
A New Method for Observing the Bifurcation of a Nonlinear System Based on CPLD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Hiding Multim. Signal Process. ![In: J. Inf. Hiding Multim. Signal Process. 8(5), pp. 1141-1148, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
26 | Shaowei Li, Shengzheng Wang |
Design Method for Ship Handling Simulator Based On CPLD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNCC ![In: Proceedings of the VI International Conference on Network, Communication and Computing, ICNCC 2017, Kunming, China, December 8-10, 2017, pp. 243-247, 2017, ACM, 978-1-4503-5366-3. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
26 | Alexander Barkalov 0001, Larysa Titarenko, Jacek Bieganowski |
Code sharing in CPLD-based Moore FSMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 6th International Conference on Modern Circuits and Systems Technologies, MOCAST 2017, Thessaloniki, Greece, May 4-6, 2017, pp. 1-4, 2017, IEEE, 978-1-5090-4386-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
26 | Fabao Yan, Yan-Rui Su, Jian-Xin Liu |
The Method of Real-Time Data Weighting Operations of CPLD/FPGA in Measurement Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Commun. ![In: J. Commun. 10(12), pp. 990-996, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Alexander Barkalov 0001, Larysa Titarenko, Slawomir Chmielewski |
Hardware Reduction in CPLD-Based Moore FSM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 23(6), 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Alexander Barkalov 0001, Larysa Titarenko, Lukasz Smolinski |
Hardware reduction for compositional microprogram control unit dedicated for CPLD systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: East-West Design & Test Symposium, EWDTS 2013, Rostov-on-Don, Russia, September 27-30, 2013, pp. 1-6, 2013, IEEE Computer Society, 978-1-4799-2095-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
26 | Chien-Nan Lee |
An intelligent sprinkler based on CPLD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMLC ![In: International Conference on Machine Learning and Cybernetics, ICMLC 2013, Tianjin, China, July 14-17, 2013, pp. 1773-1778, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
26 | Javier García-Zubía, Ignacio Angulo, Pablo Orduña, Unai Hernández, Diego López-de-Ipiña, Luis Rodriguez, Olga Dziabenko, Verónica Canivell |
WebLab-Deusto-CPLD: A Practical Experience. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Online Eng. ![In: Int. J. Online Eng. 8(S1), pp. 17-18, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
26 | Alexander Barkalov 0001, Larysa Titarenko, Slawomir Chmielewski |
Synthesis of control unit with refined state encoding for CPLD devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 9th East-West Design & Test Symposium, EWDTS 2011, Sevastopol, Ukraine, September 9-12, 2011, pp. 60-65, 2011, IEEE Computer Society, 978-1-4577-1957-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Ziga Matjasec, Denis Donlagic |
An optical signal processing device for white-light interferometry, based on CPLD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIPRO ![In: MIPRO, 2011 Proceedings of the 34th International Convention, Opatija, Croatia, 23-27 May, 2011, pp. 60-64, 2011, IEEE, 978-1-4577-0996-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
26 | Traian Tulbure |
A Dynamic Reconfigurable CPLD Architecture for Structured ASIC Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011. Proceedings, pp. 296-301, 2011, Springer, 978-3-642-19474-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Alexander Barkalov 0001, Larysa Titarenko, Slawomir Chmielewski |
Reduction in the number of PAL macrocells for Moore FSM implemented with CPLD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010, pp. 390-394, 2010, IEEE Computer Society, 978-1-4244-9555-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Yang Yang, Yanqing Zhao |
Application of CPLD in Pulse Power for EDM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCTA (4) ![In: Computer and Computing Technologies in Agriculture IV - 4th IFIP TC 12 Conference, CCTA 2010, Nanchang, China, October 22-25, 2010, Selected Papers, Part IV, pp. 398-402, 2010, Springer, 978-3-642-18368-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Xinlei Li, Gang Liu, Mingming Guo, Yin Liu, Fei Yang |
A Circuit Module and CPLD Laser Ground Controller Based on RS485. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCTA (3) ![In: Computer and Computing Technologies in Agriculture IV - 4th IFIP TC 12 Conference, CCTA 2010, Nanchang, China, October 22-25, 2010, Selected Papers, Part III, pp. 327-340, 2010, Springer, 978-3-642-18353-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Jianjun Ding, Xihua Wang, Chao Sun |
The Application of CPLD and ARM in Food Safety Testing Data Fusion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCTA (3) ![In: Computer and Computing Technologies in Agriculture IV - 4th IFIP TC 12 Conference, CCTA 2010, Nanchang, China, October 22-25, 2010, Selected Papers, Part III, pp. 36-40, 2010, Springer, 978-3-642-18353-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
26 | S. Raveendran, P. Talwai, T. Khan, R. Balasubramanian, K. Agilandaeswari |
Design of IOIM for VME bus based CPU using CPLD for nuclear power plants. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICWET ![In: Proceedings of the ICWET '10 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 26 - 27, 2010, pp. 991-993, 2010, ACM, 978-1-60558-812-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Sid-Ahmed Benali Senouci |
Physical Synthesis for CPLD Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIIA ![In: Proceedings of the 2nd Conférence Internationale sur l'Informatique et ses Applications (CIIA'09), Saida, Algeria, May 3-4, 2009, 2009, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
26 | Gerhard Grießnig, Roland Mader, Christian Steger, Reinhold Weiss |
Fault insertion testing of a novel CPLD-based fail-safe system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, pp. 214-219, 2009, IEEE, 978-1-4244-3781-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Robert Czerwinski, Dariusz Kania |
CPLD-oriented Synthesis of Finite State Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2009, 27-29 August 2009, Patras, Greece, pp. 521-528, 2009, IEEE Computer Society, 978-0-7695-3782-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Joydeb Roy Choudhury, Tribeni Prasad Banerjee, A. Nathvani, Rangeen Basu Roy Chowdhury, A. K. Bhattacharya |
Design Methodology Internal Sub State Observer using CPLD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NaBIC ![In: World Congress on Nature & Biologically Inspired Computing, NaBIC 2009, 9-11 December 2009, Coimbatore, India, pp. 1636-1640, 2009, IEEE, 978-1-4244-5053-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Ketan J. Raut, Pankaj Bande, Manish M. Patil |
A Novel Prototype for Obstacle Detection and Relative Speed Control of an Automotive Using CPLD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICETET ![In: First International Conference on Emerging Trends in Engineering and Technology, ICETET '08, Nagpur, Maharashtra, India, July 16-18, 2008, pp. 979-983, 2008, IEEE Computer Society, 978-0-7695-3267-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Jyung Hyun Lee, Yeon Kwan Moon, YoungHo Yoon, Hee Joon Park, Chul-Ho Won, Hyun-Chul Choi, Jin-Ho Cho |
CPLD Based Bi-Directional Wireless Capsule Endoscopes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 90-D(3), pp. 694-697, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Choong-Mo Youn |
Digital Sequence CPLD Technology Mapping Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inform. and Commun. Convergence Engineering ![In: J. Inform. and Commun. Convergence Engineering 5(2), pp. 131-135, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
26 | Choong-Mo Youn, Jae-Jin Kim |
A CLB-based CPLD Low-power Technology Mapping Algorithm considered a Trade-off. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inform. and Commun. Convergence Engineering ![In: J. Inform. and Commun. Convergence Engineering 5(1), pp. 59-63, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
26 | Dariusz Kania, Józef Kulisz |
Logic synthesis for PAL-based CPLD-s based on two-stage decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Softw. ![In: J. Syst. Softw. 80(7), pp. 1129-1141, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Jyung Hyun Lee, Yeon Kwan Moon, Sang Hyo Woo, Chang Wook Kim, Hee Joon Park, Jong Sik Jin, Chul-Ho Won, Hyun-Chul Choi, Yoon Nyun Kim, Jin-Ho Cho |
Design & Implementation of CPLD Controller for Bi-directional VGA Capsule Endoscop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BIOCOMP ![In: International Conference on Bioinformatics & Computational Biology, BIOCOMP 2007, Volume I, June 25-28, 2007, Las Vegas Nevada, USA, pp. 275-281, 2007, CSREA Press, 1-60132-040-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
26 | Zhifeng Diao, Dongxu Shen, Victor O. K. Li |
CPLD-PGPS scheduler in wireless OFDM systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 5(10), pp. 2923-2931, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Eftichios Koutroulis 0001, Apostolos Dollas, Kostas Kalaitzakis |
High-frequency pulse width modulation implementation using FPGA and CPLD ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 52(6), pp. 332-344, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Chin-Wen Chuang, Liang-Cheng Shiu |
CPLD based DIVSC of hydraulic position control systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 30(7), pp. 527-541, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Mile K. Stojcev, Goran Lj. Djordjevic, Tatjana R. Stankovic |
Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 44(1), pp. 173-178, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Zhifeng Diao, Dongxu Shen, Victor O. K. Li |
CPLD-PGPS scheduling algorithm in wireless OFDM systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GLOBECOM ![In: Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November - 3 December 2004, pp. 3732-3736, 2004, IEEE, 0-7803-8794-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Paul Leventis, Brad Vest, Mike Hutton, David M. Lewis |
MAX II: A low-cost, high-performance LUT-based CPLD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC 2004, Orlando, FL, USA, October 2004, pp. 443-446, 2004, IEEE, 0-7803-8495-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang |
Performance-driven mapping for CPLD architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10), pp. 1424-1431, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Shih-Liang Chen, TingTing Hwang, C. L. Liu 0001 |
A technology mapping algorithm for CPLD architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, FPT 2002, Hong Kong, China, December 16-18, 2002, pp. 204-210, 2002, IEEE, 0-7803-7574-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Roberto Sepúlveda, Oscar Montiel, Patricia Melin |
Fuzzy Control Embedded in a CPLD for Testing Batteries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IC-AI ![In: Proceedings of the International Conference on Artificial Intelligence, IC-AI '02, June 24 - 27, 2002, Las Vegas, Nevada, USA, Volume 3, pp. 1170-1176, 2002, CSREA Press, 1-892512-27-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
26 | Wan-De Weng, Wen Pin Yang |
The CPLD implementation of Viterbi algorithm in grand alliance ATSC systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 48(5), pp. 898-903, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Andrew Kennings, Haneef Mohammed, Joseph P. Skudlarek, Bing Tian |
Cypress Delta39KTM. A memory-rich, high performance, scalable CPLD architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, CICC 2000, Orlando, FL, USA, May 21-24, 2000, pp. 135-138, 2000, IEEE, 0-7803-5809-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | J. Living, Bashir M. Al-Hashimi |
Mixed arithmetic architecture: a solution to the iteration bound for resource efficient FPGA and CPLD recursive digital filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 478-481, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Ali Benkhalil, Stanley S. Ipson, William Booth |
A novel CPLD based implementation of a motion detection algorithm for surveillance applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, CICC 1998, Santa Clara, CA, USA, May 11-14, 1998, pp. 105-108, 1998, IEEE, 0-7803-4292-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
26 | Stephen Dean Brown, Jonathan Rose |
FPGA and CPLD Architectures: A Tutorial. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 13(2), pp. 42-57, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
23 | Guochen An, Zhiyong Meng, Xiaojun Wang |
Design of Grounding Resistance Measurement System Based on DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APWCS ![In: 2010 Asia-Pacific Conference on Wearable Computing Systems, APWCS 2010, Shenzhen, China , 17-18 April 2010, pp. 220-223, 2010, IEEE Computer Society, 978-0-7695-4003-0. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
grounding resistance, alien frequencies, DSP, CPLD, measuring method |
23 | Yinke Dou, Jianmin Qin, Xiaomin Chang |
The Study of a Capacitance Sensor and its System Used in Measuring Ice Thickness, Sedimentation and Water Level of a Reservoir. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFITA (3) ![In: International Forum on Information Technology and Applications, IFITA 2009, Chengdu, China, 15-17 May 2009, pp. 616-619, 2009, IEEE Computer Society, 978-0-7695-3600-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Multi-electrode Capacitance, Ice thickness, water level, CPLD, Sedimentation |
23 | Hongli Tian, Shuo Shi, Jun Zhang, Hongdong Zhao |
Controllable Arbitrary Integer Frequency Divider Based on VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JCAI ![In: First IITA International Joint Conference on Artificial Intelligence, Hainan Island, China, 25-26 April 2009, pp. 691-694, 2009, IEEE Computer Society, 978-0-7695-3615-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
50% duty cycle, frequency divider, FPGA, VHDL, CPLD |
23 | Jason Cong, Hui Huang 0001, Xin Yuan 0005 |
Technology mapping and architecture evalution for k/m-macrocell-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(1), pp. 3-23, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
FPGA, technology mapping, CPLD, PLD |
23 | Steve Ferrera, Nicholas P. Carter |
A magnetoelectronic macrocell employing reconfigurable threshold logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 143-151, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
PLA/CPLD, magnetoelectronic circuits, wired-and logic, threshold logic, lookup table, non-volatility |
23 | Uwe Meyer-Bäse, Antonio García 0001, Fred J. Taylor |
Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 28(1-2), pp. 115-128, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
field-programmable logic (FPL), complex programmable logic devices (CPLD), zero-IF filter, field programmable gate array (FPGA), digital signal processing (DSP), residue number system (RNS), channelizer |
17 | Liu Weiguang, Wang Wenqi, Cui Jiangtao |
A New Scheme for Multisensor Image Fusion System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IAS ![In: Proceedings of the Fifth International Conference on Information Assurance and Security, IAS 2009, Xi'An, China, 18-20 August 2009, pp. 509-512, 2009, IEEE Computer Society, 978-0-7695-3744-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Yaohua Sun, Ting Zhu 0001, Ziguo Zhong, Tian He 0001 |
Energy profiling for mPlatform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SenSys ![In: Proceedings of the 7th International Conference on Embedded Networked Sensor Systems, SenSys 2009, Berkeley, California, USA, November 4-6, 2009, pp. 407-408, 2009, ACM, 978-1-60558-519-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
TwinStar, energy profiling, mPlatform, ultra-capacitor, energy harvesting |
17 | Gang Wang, Du Chen, Jian Chen, Jianliang Ma, Tianzhou Chen |
A Performance Model for Run-Time Reconfigurable Hardware Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings, pp. 54-66, 2009, Springer, 978-3-642-03643-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Jian-hua Qiao, Lin-sheng Li, Jinggang Zhang |
Design of Rail Surface Crack-detecting System Based on Linear CCD Sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNSC ![In: Proceedings of the IEEE International Conference on Networking, Sensing and Control, ICNSC 2008, Hainan, China, 6-8 April 2008, pp. 1626-1631, 2008, IEEE, 978-1-4244-1685-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Falk Salewski, Stefan Kowalewski |
Achieving Highly Reliable Embedded Software: An Empirical Evaluation of Different Approaches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAFECOMP ![In: Computer Safety, Reliability, and Security, 26th International Conference, SAFECOMP 2007, Nuremberg, Germany, September 18-21, 2007., pp. 270-275, 2007, Springer, 978-3-540-75100-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Bharath Balaji Kannan, Khai D. T. Ngo |
Digital Inverse Timing Generator with Wide Dynamic Range. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 313-316, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Jiazhong Xu, Bo You, Deli Jia, Dongjie Li |
Motion Synchronization System of Filament Winding Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICIC (1) ![In: First International Conference on Innovative Computing, Information and Control (ICICIC 2006), 30 August - 1 September 2006, Beijing, China, pp. 105-108, 2006, IEEE Computer Society, 0-7695-2616-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Muhammad N. Marsono, M. Watheq El-Kharashi, Fayez Gebali |
Binary LNS-based naive Bayes hardware classifier for spam control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle |
An automated, reconfigurable, low-power RFID tag. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 131-136, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | André DeHon |
Design of programmable interconnect for sublithographic programmable logic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 127-137, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Manhattan mesh, sublithographic architecture, programmable logic arrays, nanowires, programmable interconnect |
17 | Mike Hutton |
Architecture and CAD for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 3, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Seyed Reza Abdollahi, Bertan Bakkaloglu, S. K. Hosseini |
A Fully Digital Numerical-Controlled-Oscillator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 389-398, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Christian Siemers, Volker Winterstein |
Modelling Programmable Logic Devices and Reconfigurable, Microprocessor-Related Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 188, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang |
Combinational circuit fault diagnosis using logic emulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 549-552, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Songpol Ongwattanakul, Phaisit Chewputtanagul, David Jeff Jackson, Kenneth G. Ricks |
Scalable giga-pixels/s binary image morphological operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 444-447, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni |
Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 332-339, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Cyprian Grassmann, Joachim K. Anlauf |
RACER - A Rapid Prototyping Accelerator for Pulsed Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 22-24 April 2002, Napa, CA, USA, Proceedings, pp. 277-278, 2002, IEEE Computer Society, 0-7695-1801-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Seyed Reza Abdollahi, Sayfe Kiaei, Bertan Bakkaloglu, Seid Mehdi Fakhraie, R. Anvari, Seyed Ehsan Abdollahi |
An all-digital programmable digitally-controlled-oscillator (DCO) for digital wireless applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 101-104, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Dariusz Kania |
Decomposition-Based Synthesis and its Application in PAL-Oriented Technology Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 26th EUROMICRO 2000 Conference, Informatics: Inventing the Future, 5-7 September 2000, Maastricht, The Netherlands, pp. 1138-1145, 2000, IEEE Computer Society, 0-7695-0780-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Deni Torres, J. Gonzalez, Manuel Guzman, L. Nuñez |
A new bus assignment in a designed shared bus switch fabric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 423-426, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|