Search results for "CPLDs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
104	Mark Holland, Scott Hauck	Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
85	Dariusz Kania	A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	logic synthesis, technology mapping, CPLDs
67	Mark Holland, Scott Hauck	Improving performance and robustness of domain-specific CPLDs.	FPGA	2006	DBLP DOI BibTeX RDF	computer-aided design, system-on-a-chip, reconfigurable logic, CPLD, sparse crossbar
67	K. K. Lee, D. F. Wong 0001	LRoute: a delay minimal router for hierarchical CPLDs.	FPGA	2001	DBLP DOI BibTeX RDF	complex programmable logic devices, routing, hierarchical model, Lagrangian relaxation
67	Kenneth Yan	Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks.	ASP-DAC	2001	DBLP DOI BibTeX RDF
56	Jason Helge Anderson, Stephen Dean Brown	Technology Mapping for Large Complex PLDs.	DAC	1998	DBLP DOI BibTeX RDF	technology mapping, programmable logic devices, PLA-style logic blocks
48	Robert Czerwinski, Dariusz Kania	State Assignment for PAL-based CPLDs.	DSD	2005	DBLP DOI BibTeX RDF
48	Dariusz Kania, Adam Milik, Józef Kulisz	Decomposition of Multi-Output Functions for CPLDs.	DSD	2005	DBLP DOI BibTeX RDF
30	Alexander Barkalov 0001, Larysa Titarenko, Kamil Mielcarek, Malgorzata Mazurkiewicz, Elzbieta Kawecka	Logic Synthesis for VLSI-Based Combined Finite State Machines - Synthesis Targeting ASICs, CPLDs and FPGAs		2022	DOI RDF
30	Dariusz Kania	Logic Decomposition for PAL-Based CPLDs.	J. Circuits Syst. Comput.	2015	DBLP DOI BibTeX RDF
30	David C. Dyer, Yan Lin Aung	A Multi-Paradigm Approach to Teaching Students Embedded Systems Design using FPGAs and CPLDs.	FPGAworld	2014	DBLP DOI BibTeX RDF
30	Robert Czerwinski, Dariusz Kania	Area and speed oriented synthesis of FSMs for PAL-based CPLDs.	Microprocess. Microsystems	2012	DBLP DOI BibTeX RDF
30	Adam Opara, Dariusz Kania	Decomposition-based logic synthesis for PAL-based CPLDs.	Int. J. Appl. Math. Comput. Sci.	2010	DBLP DOI BibTeX RDF
30	Dariusz Kania, Adam Milik	Logic synthesis based on decomposition for CPLDs.	Microprocess. Microsystems	2010	DBLP DOI BibTeX RDF
30	Robert Czerwinski, Dariusz Kania	Synthesis of finite state machines for CPLDs.	Int. J. Appl. Math. Comput. Sci.	2009	DBLP DOI BibTeX RDF
30	Dariusz Kania, Józef Kulisz, Adam Milik	A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs.	DSD	2005	DBLP DOI BibTeX RDF
30	Mark Holland, Scott Hauck	Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC.	FPL	2005	DBLP DOI BibTeX RDF
30	Mark Holland, Scott Hauck	Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC.	FCCM	2005	DBLP DOI BibTeX RDF
30	Dariusz Kania	Logic synthesis of multi-output functions for PAL-based CPLDs.	FPT	2002	DBLP DOI BibTeX RDF
30	Li Shang, Niraj K. Jha	High-Level Power Modeling of CPLDs and FPGAs.	ICCD	2001	DBLP DOI BibTeX RDF
30	Kenneth Yan	Logic Synthesis for CPLDs and FPGAs with PLA-Style Logic Blocks.	VLSI Design	2001	DBLP DOI BibTeX RDF
30	Walter Soto Encinas Júnior, Edson dos Santos Moreira	Hardware-Software Partition with Microcontrollers and CPLDs: A Case Study.	PDPTA	1999	DBLP BibTeX RDF
30	Bernardo Kastrup	Automatic Hardware Synthesis for a Hybrid Reconfigurable CPU Featuring Philips CPLDs	CoRR	1998	DBLP BibTeX RDF
30	David Greenfield, Caleb Crome, Martin S. Won, Doug Amos	Enhancing fixed point DSP processor performance by adding CPLDs as coprocessing elements.	FPL	1997	DBLP DOI BibTeX RDF
19	Dirk Koch, Christian Beckhoff, Jürgen Teich	Hardware Decompression Techniques for FPGA-Based Embedded Systems.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	reconfigurable computing, configuration, Bitstream
19	Hans Kristian Otnes Berge, Philipp Häfliger	High-Speed Serial AER on FPGA.	ISCAS	2007	DBLP DOI BibTeX RDF
19	R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, André Inácio Reis	Asynchronous circuit design on reconfigurable devices.	SBCCI	2006	DBLP DOI BibTeX RDF	FPGAs, asynchronous circuits
19	Luís Gomes 0001, Anikó Costa	Teaching Formal Methods Within System-on-a-Programmable-Chip Design.	MSE	2005	DBLP DOI BibTeX RDF
19	R. James Duckworth	Embedded System Design with FPGAs Using HDLs (Lessons Learned and Pitfalls to Be Avoided).	MSE	2005	DBLP DOI BibTeX RDF
19	Mike Hutton	Architecture and CAD for FPGAs.	SBCCI	2004	DBLP DOI BibTeX RDF
19	Mike Hutton	Advances and trends in FPGA design.	SBCCI	2004	DBLP DOI BibTeX RDF
19	Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka	Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	SRAM test, SRAM-based reconfigurable cell, memory tester, marching test
19	Luís Gomes 0001	Introducing Programmable Logic Devices into Digital Design.	MSE	2001	DBLP DOI BibTeX RDF
19	Charles E. Stroud, James R. Bailey, Johan R. Emmert	A New Method for Testing Re-Programmable PLAs.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	electrically erasable programmable logic array testing, manufacturing test development, bridging faults
19	Bernardo Kastrup, Orlando Moreira	A Novel Approach to Minimizing the Logic of Combinatorial Multiplexing Circuits in Product-Term-Based Hardware.	EUROMICRO	2000	DBLP DOI BibTeX RDF
19	Dariusz Kania	A Technology Mapping Algorithm for PAL-Based Devices Using Multi-Output Function Graphs.	EUROMICRO	2000	DBLP DOI BibTeX RDF
19	Bharat P. Dave	CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems.	DATE	1999	DBLP DOI BibTeX RDF
19	Daniel P. Van der Velde, Ad J. van de Goor	Designing a Memory Module Tester.	MTDT	1999	DBLP DOI BibTeX RDF
19	A. Dornbusch, José Pineda de Gyvez	Chaotic generation of PN sequences: a VLSI implementation.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
19	Jason Helge Anderson, Stephen Dean Brown	An LPGA with Foldable PLA-style Logic Blocks.	FPGA	1998	DBLP DOI BibTeX RDF
19	J. Fischer, C. Müller, H. Kurz	A Co-simulation Concept for an Efficient Analysis of Complex Logic Designs.	FPL	1998	DBLP DOI BibTeX RDF
19	A. Abo Shosha, P. Reinhart, F. Rongen	Reconfigurable PCI-Bus Interface (RPCI).	FPL	1998	DBLP DOI BibTeX RDF
19	Michael J. Lees, Duncan A. Campbell, J. C. Devlin	A high-speed reconfigurable defuzzification architecture for true centre-of-gravity computations.	ANZIIS	1996	DBLP DOI BibTeX RDF