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Searching for phrase Carry-save (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1974-1991 (16) 1992-1995 (20) 1996-1998 (15) 1999-2000 (22) 2001-2002 (20) 2003 (19) 2004-2005 (25) 2006 (20) 2007 (19) 2008 (18) 2009-2015 (17) 2016-2024 (11)
Publication types (Num. hits)
article(70) inproceedings(150) phdthesis(2)
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The graphs summarize 235 occurrences of 151 keywords

Results
Found 222 publication records. Showing 222 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
117Oscar Gustafsson, Henrik Ohlsson, Lars Wanhammar Minimum-adder integer multipliers using carry-save adders. Search on Bibsonomy ISCAS (2) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
97Mike Paterson, Nicholas Pippenger, Uri Zwick Faster Circuits and Shorter Formulae for Multiple Addition, Multiplication and Symmetric Boolean Functions Search on Bibsonomy FOCS The full citation details ... 1990 DBLP  DOI  BibTeX  RDF multiplication circuits, multiple addition, shallowest possible circuits, shortest possible formulas, occurrence matrix, shortest multiple carry-save addition formulas, delay matrix, multiple carry-save adders, multiplication, symmetric Boolean functions, carry-save addition
93Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian An effective BIST scheme for carry-save and carry-propagate array multipliers. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF BIST scheme, carry-propagate array multipliers, carry-save array multipliers, complex VLSI devices, maximum length LFSR, count-based scheme, multiplier cells, VLSI, logic testing, controllability, built-in self test, integrated circuit testing, automatic testing, observability, fault coverage, test pattern generator, multiplying circuits, carry logic
84Bong-Il Park, In-Cheol Park, Chong-Min Kyung A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders. Search on Bibsonomy ICCD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Booth algorithm, Carry-Save Adder and Wallace Tree, Multiplier
83Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001 Design of a radix-2m hybrid array multiplier using carry save adder format. Search on Bibsonomy SBCCI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF hybrid multiplier, low power, carry save adder
79Javier Hormigo, Manuel Ortiz, Francisco J. Quiles 0002, Francisco J. Jaime, Julio Villalba, Emilio L. Zapata Efficient Implementation of Carry-Save Adders in FPGAs. Search on Bibsonomy ASAP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
78Junhyung Um, Taewhan Kim An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2001 DBLP  DOI  BibTeX  RDF VLSI, arithmetic circuits, Carry-save-addition
74Alexandre F. Tenca, Song Park, Lo'ai Ali Tawalbeh Carry-Save Representation Is Shift-Unsafe: The Problem and Its Solution. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Carry-save, arithmetic shift, computer arithmetic, redundant representation
72Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr. The use of carry-save representation in joint module selection and retiming. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
72Tobias G. Noll Carry-save architectures for high-speed digital signal processing. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
65Behrooz Parhami Comments on "Evaluation of A + B + K Conditions Without Carry Propagation". Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF carry-free circuit, A+B=K, negative effects, carry-save redundant numbers, (3, 2)-counters, carry propagation, carry-save numbers, pipeline processing, logic circuits, pipelined architectures, comparators, addition, parallel counters, redundant number representation, conditional branches
63M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas New and Improved Architectures for Montgomery Modular Multiplication. Search on Bibsonomy Mob. Networks Appl. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF reconfigurable multiplier, scalable multiplier, RSA, ECC, carry save adders, Montgomery modular multiplication
63Stanislaw J. Piestrak Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF residue generators, multioperand modular adders, arithmetic error detecting codes, binary-to-residue number system, residue generator, digital arithmetic, adders, Chinese remainder theorem, residue number system, arithmetic codes, residue arithmetic, carry-save adders
63Hung Chi Lai, Saburo Muroga Logic Networks of Carry-Save Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1982 DBLP  DOI  BibTeX  RDF parallel adder in double-rail input logic, Carry?save adders, input bundles, multioperand adders, NAND gates, NOR gates, output bundles, logic design, multipliers, full adders
62Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr. Optimal joint module-selection and retiming with carry-save representation. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
62Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr. Bit-level arithmetic optimization for carry-save additions. Search on Bibsonomy ICCAD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
58Viktor Bunimov, Manfred Schimmler Area and Time Efficient Modular Multiplication of Large Integers. Search on Bibsonomy ASAP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Montgomery algorithm, interleaved modular multiplication, MSB-first arithmetic, redundant number arithmetic, Modular multiplication, carry save addition
56Jean-Luc Beuchat, Jean-Michel Muller Automatic Generation of Modular Multipliers for FPGA Applications. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
56Mark A. Erle, Michael J. Schulte Decimal Multiplication Via Carry-Save Addition. Search on Bibsonomy ASAP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
56Paolo Montuschi, Luigi Ciminiera n × n carry-save multipliers without final addition. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
52Çetin Kaya Koç, Ching Yu Hung Bit-level systolic arrays for modular multiplication. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF sign estimation, scheduling, systolic array, modular multiplication, carry save adders
47Levent Aksoy, Ece Olcay Günes Area optimization algorithms in high-speed digital FIR filter synthesis. Search on Bibsonomy SBCCI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF high-speed filter design, multiple constant multiplications, subexpression sharing, area optimization, carry-save adders
46Viv A. Bartlett, Andrew G. Dempster Using carry-save adders in low-power multiplier blocks. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
46Junhyung Um, Taewhan Kim, C. L. Liu 0001 Optimal allocation of carry-save-adders in arithmetic optimization. Search on Bibsonomy ICCAD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
43Ajay Kumar Verma, Paolo Ienne Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF multiplier-like circuits, XOR-dominated circuits, datapath design, netlist optimization, carry-save form, column compressors, XOR operations, logic synthesizers, algebraic factoring, computer arithmetic, logic synthesis, digital design, parallel multipliers
43Bonseok Koo, Dongwook Lee, Gwonho Ryu, Taejoo Chang, Sangjin Lee 0002 High-Speed RSA Crypto-processor with Radix-4 Modular Multiplication and Chinese Remainder Theorem. Search on Bibsonomy ICISC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Booth’s algorithm, RSA, Chinese Remainder Theorem, Montgomery multiplication, Carry Save Adder
43Viktor Bunimov, Manfred Schimmler Efficient Parallel Multiplication Algorithm for Large Integres. Search on Bibsonomy Euro-Par The full citation details ... 2003 DBLP  DOI  BibTeX  RDF large number arithmetic, redundant numbers, Computer arithmetic, integer multiplication, carry save addition, parallel multiplication
43Junhyung Um, Taewhan Kim Layout-aware synthesis of arithmetic circuits. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF layout, high performance, carry-save-adder
43S. Ramanathan, V. Visvanathan A systolic architecture for LMS adaptive filtering with minimal adaptation delay. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF LMS adaptive filtering, minimal adaptation delay, convergence behaviour, function preserving transformations, SFG representation, carry-save arithmetic, systolic folded pipelined architecture, VLSI, delays, systolic arrays, pipeline processing, adaptive filters, digital filters, digital signal processing chips, convergence of numerical methods, systolic architecture, signal flow graphs, signal flow graph, least mean squares methods, LMS algorithm
43D. V. Poornaiah, P. V. Ananda Mohan A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF concurrent dual multiplier-dual adder architecture, video coding applications, high-throughput image coding, carry-save 4:2 compressors, computational complexity, VLSI, VLSI, data compression, video coding, adders, computation time, multiplying circuits, digital signal processing chips
43Song Cui, Neil Burgess, Michael J. Liebelt, Kamran Eshraghian A GaAs IEEE Floating Point Standard Single Precision Multiplier. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1995 DBLP  DOI  BibTeX  RDF floating point multiplier, rounding algorithm, modified carry save array, GaAs technology
41Ajay Kumar Verma, Philip Brisk, Paolo Ienne Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
41Mark A. Erle, Michael J. Schulte, Brian J. Hickmann Decimal Floating-Point Multiplication Via Carry-Save Addition. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
41Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
41Ajay Kumar Verma, Paolo Ienne Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
41Youngtae Kim, Taewhan Kim Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
41Kei-Yong Khoo, Chao-Liang Chen, Alan N. Willson Jr. A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking. Search on Bibsonomy ISCAS (1) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
41Taewhan Kim, William Jao, Steven W. K. Tjiang Circuit optimization using carry-save-adder cells. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
41Taewhan Kim, William Jao, Steven W. K. Tjiang Arithmetic Optimization Using Carry-Save-Adders. Search on Bibsonomy DAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band
36Jun-Hong Chen, Haw-Shiuan Wu, Ming-Der Shieh, Wen-Ching Lin A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi Improved Design of High-Performance Parallel Decimal Multipliers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2010 DBLP  DOI  BibTeX  RDF Decimal multiplication, decimal carry-save addition, decimal codings, parallel multiplication
32Naofumi Takagi Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms. Search on Bibsonomy ISMVL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF carry-save form, carry-propagation-free addition, multiplier recoding, computer arithmetic, signed-digit number representation, digit-recurrence algorithm
32Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan A New Divide and Conquer Method for Achieving High Speed Division in Hardware. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Carry Propagate Adders, Pipelineability, Throughput, Latency, Rounding, Carry Save Adders, Radix, SRT
32Dhananjay S. Phatak, Tom Goff, Israel Koren Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2001 DBLP  DOI  BibTeX  RDF constant-time addition, simultaneous format conversion, redundant adders, signed-digit addition, 4:2 compressor, Redundant representations, carry-save addition
32Milos D. Ercegovac, Tomás Lang, Paolo Montuschi Very-High Radix Division with Prescaling and Selection by Rounding. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF very-high radix division, quotient-digit selection, carry-save, computer arithmetic, digital arithmetic, selection, rounding, redundant representation, prescaling, carry logic, division algorithm
32Jean Duprat, Jean-Michel Muller The CORDIC Algorithm: New Results for Fast VLSI Implementation. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF sign functions, fast VLSI implementation, signed-digit implementation, carry-save representation, branching CORDIC method, constant normalization factor, online delay, cosine functions, VLSI, signal processing, digital arithmetic, CORDIC algorithm
32Stamatis Vassiliadis, James Phillips, Bart Blaner Interlock Collapsing ALU's. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF interlocked fixed point arithmetic logic unit, unsigned binary, binary logical operations, single instruction execution, machine cycle, architectural compatibility, parallel processing, digital arithmetic, adders, CMOS integrated circuits, CMOS technology, carry-save adder, carry-lookahead adder, two's complement
32Luigi Ciminiera, Paolo Montuschi Higher Radix Square Rooting. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1990 DBLP  DOI  BibTeX  RDF nonrestoring square root algorithms, feasible algorithms, digit set, radicand bits, starting value, partial remainder bits, digit selection, radix 4, carry-save, constraints, representation, digital arithmetic, bounds, number theory, radix
32Tom Rhyne, Noel R. Strader II A Signed Bit-Sequential Multiplier. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1986 DBLP  DOI  BibTeX  RDF VLSI signal processing circuits, Bit-sequential multiplication, Booth's algorithm, carry-save arithmetic, computer arithmetic
32R. Gnanasekaran On a Bit-Serial Input and Bit-Serial Output Multiplier. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1983 DBLP  DOI  BibTeX  RDF two's complement number representation, Add-shift multiplier, bit-sequential multiplier, on-line multiplication, carry-save addition
32John H. Zurawski, J. B. Gosling Design of High-Speed Digital Divider Units. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1981 DBLP  DOI  BibTeX  RDF uncommitted logic arrays (gate arrays), Borrow?save subtraction, carry?save addition, digital division, group subtractor, iterative division, digital arithmetic
32Daniel E. Atkins, Shauchi Ong Time-Component Complexity of Two Approaches to Multioperand Binary Addition. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1979 DBLP  DOI  BibTeX  RDF time-component complexity, Adder tree, multioperand addition, carry-save adder, carry-lookahead adder, binary addition
32Dharma P. Agrawal High-Speed Arithmetic Arrays. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1979 DBLP  DOI  BibTeX  RDF carry-look-ahead, carry-save, pipelining, multiplication, division, Arrays, square-root, square, high-speed arithmetic, sign detection, multifunction
32Paul W. Baker Suggestion for a Fast Binary Sine/Cosine Generator. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1976 DBLP  DOI  BibTeX  RDF Cascaded carry-save adders, continued products, digital arithmetic, sines, cosines
31Henrik Ohlsson, Oscar Gustafsson, Lars Wanhammar Arithmetic transformations for increased maximal sample rate of bit-parallel bireciprocal lattice wave digital filters. Search on Bibsonomy ISCAS (2) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
31Junhyung Um, Taewhan Kim, C. L. Liu 0001 A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
31Chang Nian Zhang, Behrooz A. Shirazi, David Y. Y. Yun Computing multiple modulo summation (abstract only): a new algorithm, its VLSI designs and applications. Search on Bibsonomy ACM Conference on Computer Science The full citation details ... 1987 DBLP  DOI  BibTeX  RDF
31Melika Amiri, Massoud Dousti, Majid Mohammadi Design and implementation of carry-save adder using quantum-dot cellular automata. Search on Bibsonomy J. Supercomput. The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
31Oleg Mazonka, Eduardo Chielle, Deepraj Soni, Michail Maniatakos Fast and Compact Interleaved Modular Multiplication Based on Carry Save Addition. Search on Bibsonomy ICCAD The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
31Hadise Ramezani, Majid Mohammadi, Amir Sabbagh Molahoseini An Efficient Implementation of Low-Latency Two-Dimensional Gaussian Smoothing Filter using Approximate Carry-Save Adder. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
31Raffaele De Rose, Paul Romero, Marco Lanuzza Double-precision Dual Mode Logic carry-save multiplier. Search on Bibsonomy Integr. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
31Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
31Debashis De, Jadav Chandra Das Design of novel carry save adder using quantum dot-cellular automata. Search on Bibsonomy J. Comput. Sci. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
31Daniel Dinu, Johann Großschädl, Yann Le Corre Efficient Masking of ARX-Based Block Ciphers Using Carry-Save Addition on Boolean Shares. Search on Bibsonomy ISC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
31Darjn Esposito, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo On the use of approximate adders in carry-save multiplier-accumulators. Search on Bibsonomy ISCAS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
31Kostas Tsoumanis, Sotirios Xydis, Georgios Zervakis 0001, Kiamal Z. Pekmestzi Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
31Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik A Partial Carry-Save On-the-Fly Correction Multispeculative Multiplier. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
31Ugur Cini, Olcay Kurt MAC unit for reconfigurable systems using multi-operand adders with double carry-save encoding. Search on Bibsonomy DTIS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
31Yanxiang Huang, Ajay Kapoor, Robert Rutten, José Pineda de Gyvez A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain with Carry-Save format numbers. Search on Bibsonomy Microprocess. Microsystems The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
31Song Jia, Shigong Lyu, Xiayu Li, Li Liu, Yandong He Simplified carry save adder-based array multiplier scheme and circuits design. Search on Bibsonomy Int. J. Circuit Theory Appl. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
31Ugur Cini, Olcay Kurt A MAC unit with double carry-save scheme suitable for 6-input LUT based reconfigurable systems. Search on Bibsonomy ICECS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
31Alessandro Cilardo, Davide De Caro, Nicola Petra, Francesco Caserta, Nicola Mazzocca, Ettore Napoli, Antonio Giuseppe Maria Strollo High Speed Speculative Multipliers Based on Speculative Carry-Save Tree. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
31Minas Dasygenis Generation and validation of multioperand carry save adders from the web. Search on Bibsonomy DTIS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
31Yanxiang Huang, Ajay Kapoor, Robert Rutten, José Pineda de Gyvez A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using Carry-Save format numbers. Search on Bibsonomy NORCHIP The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
31Stefan Siegel, Jürgen Wolff von Gudenberg A long accumulator like a carry-save adder. Search on Bibsonomy Computing The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
31David Neuhäuser Design and evaluation of computer arithemetic based on carry-save and signed-digit redundant number representations. Search on Bibsonomy 2012   RDF
31Carlos Diego Moreno-Moreno, Pilar Martínez, Francisco Bellido 0001, Javier Hormigo, Manuel Ortiz, Francisco J. Quiles 0002 Convolution Computation in FPGA Based on Carry-Save Adders and Circular Buffers. Search on Bibsonomy IT Revolutions The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
31Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Paolo Ienne Improving FPGA Performance for Carry-Save Arithmetic. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
31Amit Verma 0002, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. Search on Bibsonomy FPL The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
31Anton Blad, Oscar Gustafsson Redundancy reduction for high-speed fir filter architectures based on carry-save adder trees. Search on Bibsonomy ISCAS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
31Roberto Gutierrez, Javier Valls, Asuncion Perez-Pascual FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic. Search on Bibsonomy FPL The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
31Dimitris Bekiaris, Isidoros Sideris, George Economakos, Kiamal Z. Pekmestzi Power-Efficient and Low Latency Implementation of Programmable FIR filters Using Carry-Save Arithmetic. Search on Bibsonomy ICECS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
31Oscar Gustafsson, Andrew G. Dempster, Lars Wanhammar Multiplier blocks using carry-save adders. Search on Bibsonomy ISCAS (2) The full citation details ... 2004 DBLP  BibTeX  RDF
31Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka A low latency and low power dynamic Carry Save Adder. Search on Bibsonomy ISCAS (2) The full citation details ... 2004 DBLP  BibTeX  RDF
31David Defour, Florent de Dinechin Software Carry-Save: A Case Study for Instruction-Level Parallelism. Search on Bibsonomy PaCT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
31Zhan Yu, Meng-Lin Yu, Alan N. Willson Jr. Signal Representation Guided Synthesis Using Carry-Save Adders For Synchronous Data-path Circuits. Search on Bibsonomy DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
31Youngtae Kim, Taewhan Kim An Accurate Exploration of Timing and Area Trade-Offs in Arithmetic Optimization Using Carry-Save-Adders. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
31Taewhan Kim, Junhyung Um A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper). Search on Bibsonomy ASP-DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
31Wen-Chang Yeh, Chein-Wei Jen A high performance carry-save to signed-digit recoder for fused addition-multiplication. Search on Bibsonomy ICASSP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
31Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr. Efficient implementation of FIR filters using bit-level optimized carry-save additions. Search on Bibsonomy EUSIPCO The full citation details ... 2000 DBLP  BibTeX  RDF
31Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr. Joint module selection and retiming with carry-save representation. Search on Bibsonomy EUSIPCO The full citation details ... 2000 DBLP  BibTeX  RDF
31Luigi Ciminiera, Paolo Montuschi Carry-Save Multiplication Schemes without Final Addition. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
31Patrik Larsson, Chris J. Nicol Transition reduction in carry-save adder trees. Search on Bibsonomy ISLPED The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
31David R. Bull, Graham Wacey Gate Level Optimisation of Primitive Operator Digital Filters using a Carry Save Decomposition. Search on Bibsonomy ISCAS The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
31Damian Harris-Dowsett, Steve Summerfield Carry Save & Pipelining Techniques for Wave Digital Filters. Search on Bibsonomy ISCAS The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
31Stanislaw J. Piestrak Design of residue generators and multioperand modular adders using carry-save adders. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
31Hung Chi Lai A Study of Current Logic Design Problems: Part I, Design of Diagnosable Mos Networks; Part Ii, Minimum Nor (Nand) Networks for Parity Functions of an Arbitrary Number of Variables; Part Iii, Minimum Parallel Binary Adders With Nor (Nand) Gates and Their Extensions to Networks Consisting of Carry-Save Adders Search on Bibsonomy 1976   RDF
31Dhiraj K. Pradhan Fault-Tolerant Carry-Save Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1974 DBLP  DOI  BibTeX  RDF
30Sudhakar Maddi, M. B. Srinivas A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA. Search on Bibsonomy SBCCI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF sum-carry logic, RSA, ECC, reconfigurable architectures, montgomery multiplication, unified architectures
25Ming-Der Shieh, Jun-Hong Chen, Hao-Hsuan Wu, Wen-Ching Lin A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
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