|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 7 occurrences of 7 keywords
|
|
|
Results
Found 54 publication records. Showing 54 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
56 | Pei-Lin Pai |
DRAM Industry Trend. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
53 | Phil Murray, Feras Al-Hawari |
Challenges in implementing DDR3 memory interface on PCB systems: a methodology for interfacing DDR3 SDRAM DIMM to an FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2204.05107, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
33 | Ronald N. Kalla, Balaram Sinharoy, William J. Starke, Michael S. Floyd |
Power7: IBM's Next-Generation Server Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 30(2), pp. 7-15, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Power7, eDRAM, DDR3, SMT operation, PowerPC architecture, processor, IBM, RAS |
33 | Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John |
The virtual write queue: coordinating DRAM and last-level cache policies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 72-82, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
cmp many-core, ddr ddr2 ddr3, dram-parameters, memory-scheduling writeback, page-mode, write-queue, write-scheduling, dram, cache-replacement, last-level-cache |
28 | Hongzhong Zheng, Jiang Lin, Zhao Zhang 0010, Zhichun Zhu |
Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 255-266, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
bandwidth decoupling, decoupled DIMM, DRAM memories |
28 | Hongzhong Zheng, Jiang Lin, Zhao Zhang 0010, Eugene Gorbatov, Howard David, Zhichun Zhu |
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 210-221, 2008, IEEE Computer Society, 978-1-4244-2836-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Xiaofeng Yang, Ancheng Liu, Jinjin Wang |
High Speed Multi-channel Data Cache Design Based on DDR3 SDRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AIPR ![In: Proceedings of the 5th International Conference on Artificial Intelligence and Pattern Recognition, AIPR 2022, Xiamen, China, September 23-25, 2022, pp. 193-196, 2022, ACM, 978-1-4503-9689-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Vladimir M. Milovanovic, Darko M. Tasovac |
A Customizable DDR3 SDRAM Controller Tailored for FPGA-Based Data Buffering Inside Real-Time Range-Doppler Radar Signal Processing Back Ends. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCON ![In: IEEE EUROCON 2019 - 18th International Conference on Smart Technologies, Novi Sad, Serbia, July 1-4, 2019, pp. 1-6, 2019, IEEE, 978-1-5386-9301-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
26 | Ana Cóbreces, Alberto Regadío, Jesús Tabero, Pedro Reviriego, Alfonso Sánchez-Macián, Juan Antonio Maestro |
Seu and Sefi error detection and correction on a ddr3 memory system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 91, pp. 23-30, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Jianfei Wu, Wei Zhu, Binhong Li, Yafei Li, Hongyi Wang 0003, Mengjun Wang |
Investigations on immunity of interfaces between intelligent media processor and DDR3 SDRAM memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 88-90, pp. 230-235, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Tan Li, Hosung Lee, GeunYong Bak, Sanghyeon Baeg |
Failure signature analysis of power-opens in DDR3 SDRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 88-90, pp. 277-281, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Matthias Jung 0001, Deepak M. Mathew, Carl Christian Rheinländer, Christian Weis, Norbert Wehn |
A Platform to Analyze DDR3 DRAM's Power and Retention Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 34(4), pp. 52-59, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
26 | Junsub Yoon, Seo Weon Heo, Jongsun Kim |
A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 14(2), pp. 20161020, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
26 | Sergei Odintsov, Artur Jutman, Sergei Devadze |
Marginal PCB assembly defect detection on DDR3/4 memory bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: IEEE International Test Conference, ITC 2017, Fort Worth, TX, USA, October 31 - Nov. 2, 2017, pp. 1-10, 2017, IEEE, 978-1-5386-3413-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
26 | Xuedong Wang, Lingyu Shen, Min Jia |
The Design and Optimization of DDR3 Controller Based on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSPS ![In: Communications, Signal Processing, and Systems - Proceedings of the 2017 International Conference on Communications, Signal Processing, and Systems, CSPS 2017, Harbin, China, 14-16 July 2017., pp. 1744-1750, 2017, Springer, 978-981-10-6570-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
26 | Johannes Bauer 0004, Michael Gruhn, Felix C. Freiling |
Lest we forget: Cold-boot attacks on scrambled DDR3 memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Digit. Investig. ![In: Digit. Investig. 16 Supplement, pp. S65-S74, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
26 | Kyungbae Park, Donghyuk Yun, Sanghyeon Baeg |
Statistical distributions of row-hammering induced failures in DDR3 components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 67, pp. 143-149, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
26 | Kyungbae Park, Chul Seung Lim, Donghyuk Yun, Sanghyeon Baeg |
Experiments and root cause analysis for active-precharge hammering fault in DDR3 SDRAM under 3 × nm technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 57, pp. 39-46, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
26 | Wenhua Ye, Huan Li |
FPGA Based DDR3 Applications in a Multichannel Channelization Data Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCID (1) ![In: 9th International Symposium on Computational Intelligence and Design, ISCID 2016, Hangzhou, China, December 10-11, 2016, Volume 1, pp. 54-57, 2016, IEEE, 978-1-5090-3558-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
26 | Baekseok Ko, Joo-Won Kim, Kihun Oh, Chan-Keun Kwon, Soo-Won Kim |
Simulation of serpentine trace of DQ PCB layout for DDR3 applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE ![In: IEEE International Conference on Consumer Electronics, ICCE 2016, Las Vegas, NV, USA, January 7-11, 2016, pp. 27-28, 2016, IEEE, 978-1-4673-8364-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
26 | GeunYong Bak, Soonyoung Lee, Hosung Lee, Kyungbae Park, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong, Charlie Slayman |
Logic soft error study with 800-MHz DDR3 SDRAMs in 3x nm using proton and neutron beams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015, pp. 3, 2015, IEEE, 978-1-4673-7362-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Simon Lindenlauf, Hans Höfken, Marko Schuba |
Cold Boot Attacks on DDR2 and DDR3 SDRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARES ![In: 10th International Conference on Availability, Reliability and Security, ARES 2015, Toulouse, France, August 24-27, 2015, pp. 287-292, 2015, IEEE Computer Society, 978-1-4673-6590-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Rajat Chauhan, Prajkta Vyavahare, Siva Kothamasu |
Fail-safe I/O to control RESET# pin of DDR3 SDRAM and achieve ultra-low system power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015, pp. 357-360, 2015, IEEE, 978-1-4799-7581-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Hao-Yu Yang, Shih-Hua Kuo, Tzu-Hsuan Huang, Chi-Hung Chen, Chris Lin, Mango Chia-Tso Chao |
Random pattern generation for post-silicon validation of DDR3 SDRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 33rd IEEE VLSI Test Symposium, VTS 2015, Napa, CA, USA, April 27-29, 2015, pp. 1-6, 2015, IEEE Computer Society, 978-1-4799-7597-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Preeti Ranjan Panda, Vishal Patel, Praxal Shah, Namita Sharma 0001, Vaidyanathan Srinivasan, Dipankar Sarma |
Power Optimization Techniques for DDR3 SDRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 28th International Conference on VLSI Design, VLSID 2015, Bangalore, India, January 3-7, 2015, pp. 310-315, 2015, IEEE Computer Society, 978-1-4799-6658-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Vladimir V. Stankovic, Nebojsa Z. Milenkovic, Oliver M. Vojinovic |
Implementation of the Complete Predictor for DDR3 SDRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 97-D(3), pp. 589-592, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Hongming Chen 0002, Song Ma, Liu Wang, Hao Zhang, Kenyi Pan, Yuhua Cheng |
A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 57(12), pp. 1-8, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Wenchao Liu 0003, Zhenhua Zhang, Miao-Xin Li, Zhenglin Liu |
A Trustworthy Key Generation Prototype Based on DDR3 PUF for Wireless Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 14(7), pp. 11542-11556, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Abir M'zah, Bruno Monsuez |
Refresh-aware DDR3 barrel memory controller with deterministic functionality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ODES@CGO ![In: Proceedings of the 11th Workshop on Optimizations for DSP and Embedded Systems, ODES@CGO 2014, Orlando, Florida, USA, February 15, 2014, pp. 3-9, 2014, ACM, 978-1-4503-2595-0. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel |
A DDR3/4 memory link TX supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC 2014 - 40th European Solid State Circuits Conference, Venice Lido, Italy, September 22-26, 2014, pp. 135-138, 2014, IEEE, 978-1-4799-5694-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Shang-Ping Chen, Chih-Chien Hung, Qui-Ting Chen, Sheng-Ming Chang, Ming-Shi Liou, Bo-Wei Hsieh, Hsiang-I Huang, Brian Liu, Yan-Bin Luo |
26.6 A 2.667Gb/s DDR3 memory interface with asymmetric ODT on wirebond package and single-side-mounted PCB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2014 IEEE International Conference on Solid-State Circuits Conference, ISSCC 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014, pp. 448-449, 2014, IEEE, 978-1-4799-0918-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Gilbert Netzer, S. Lennart Johnsson, Daniel Ahlin, Erwin Laure |
Instrumentation for accurate energy-to-solution measurements of a texas instruments TMS320C6678 digital signal processor and its DDR3 memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
E2SC@SC ![In: Proceedings of the 2nd International Workshop on Energy Efficient Supercomputing, E2SC '14, New Orleans, Louisiana, USA, November 16-21, 2014, pp. 89-98, 2014, IEEE Computer Society, 978-1-4799-7036-0. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Su Myat Min, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran |
A case study on exploration of last-level cache for energy reduction in DDR3 DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MECO ![In: 2nd Mediterranean Conference on Embedded Computing, MECO 2013, Budva, Montenegro, June 15-20, 2013, pp. 42-45, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
26 | Seung Mo Jung, Jong Hyun Seok, Ho Jin Yoo, Do Hyung Kim 0002, You Keun Han, Woo-Seop Kim, Joo-Sun Choi, Jun Dong Cho |
Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2013 IEEE International SOC Conference, Erlangen, Germany, September 4-6, 2013, pp. 343-348, 2013, IEEE, 978-1-4799-1166-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
26 | Kambiz Kaviani, Ting Wu 0003, Jason Wei, Amir Amirkhany, Jie Shen 0010, T. J. Chin, Chintan Thakkar, Wendemagegnehu T. Beyene, Norman Chan, Catherine Chen, Bing Ren Chuang, Deborah Dressler, Vijay P. Gadde, Mohammad Hekmat, Eugene Ho, Charlie Huang, Phuong Le, Mahabaleshwara, Chris J. Madden, Navin K. Mishra, Leneesh Raghavan, Keisuke Saito, Ralf Schmitt, Dave Secker, Xudong Shi 0004, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Steve Zhang, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan |
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 47(4), pp. 926-937, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
26 | Gary A. Van Huben, Kirk D. Lamb, R. Brett Tremaine, B. E. Aleman, S. M. Rubow, S. H. Rider, Warren E. Maule, Michael E. Wazlowski |
Server-class DDR3 SDRAM memory buffer chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 56(1), pp. 3, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
26 | Heechai Kang, Kyungho Ryu, Dong-Hoon Jung, Donghwan Lee, Won Lee, SuHo Kim, JongRyun Choi, Seong-Ook Jung |
Process Variation Tolerant All-Digital 90° Phase Shift DLL for DDR3 Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(10), pp. 2186-2196, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
26 | Kyu-Nam Lim, Woong-Ju Jang, Hyung-Sik Won, Kang-Yeol Lee, Hyungsoo Kim, Dong-Whee Kim, Mi-Hyun Cho, Seung-Lo Kim, Jong-Ho Kang, Keun-Woo Park, Byung-Tae Jeong |
A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012, pp. 42-44, 2012, IEEE, 978-1-4673-0376-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
26 | Richard Crisp, Bill Gervasi, Wael Zohni, Bel Haba |
Cost-minimized double die DRAM packaging for ultra-high performance DDR3 and DDR4 multi-rank server DIMMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012, pp. 437-444, 2012, IEEE, 978-1-4673-1034-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
26 | Navin K. Mishra, Manish Jain, Phuong Le, Sanku Mukherjee, Arul Sendhil, Amir Amirkhany |
An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011, pp. 1-4, 2011, IEEE, 978-1-4577-0222-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Jong-Chern Lee, Sin-Hyun Jin, Dae-Suk Kim, Young Jun Ku, Chul Kim, Byung-Kwon Park, Hong-Gyeom Kim, Seong-Jun Ahn, Jaejin Lee, Sung-Joo Hong |
A low-power small-area open loop digital DLL for 2.2Gb/s/pin 2Gb DDR3 SDRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2011, Jeju, South Korea, November 14-16, 2011, pp. 157-160, 2011, IEEE, 978-1-4577-1784-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Uksong Kang, Hoeju Chung, Seongmoo Heo, Dukha Park, Hoon Lee, Jin Ho Kim, Soon-Hong Ahn, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jaewook Lee, Han-Sung Joo, Woo-Seop Kim, Dong Hyeon Jang, Nam-Seog Kim, Jung-Hwan Choi, Tae-Gyeong Chung, Jei-Hwan Yoo, Joo-Sun Choi, Changhyun Kim, Young-Hyun Jun |
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 45(1), pp. 111-119, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Vladimir V. Stankovic, Nebojsa Z. Milenkovic |
DDR3 SDRAM with a Complete Predictor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 93-D(9), pp. 2635-2638, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Jaejun Lee, Sungho Lee, Sangwook Nam |
Multi-Slot Main Memory System for Post DDR3. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 57-II(5), pp. 334-338, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Heechai Kang, Kyungho Ryu, Donghwan Lee, Won Lee, SuHo Kim, JongRyun Choi, Seong-Ook Jung |
Process variation tolerant all-digital multiphase DLL for DDR3 interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings, pp. 1-4, 2010, IEEE, 978-1-4244-5758-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Yongsam Moon, Yong-Ho Cho, Hyun-Bae Lee, Byung-Hoon Jeong, Seok-Hun Hyun, Byungchul Kim, In-Chul Jeong, Seong-Young Seo, Junho Shin, Seok-Woo Choi, Ho-Sung Song, Jung-Hwan Choi, Kyehyun Kyung, Young-Hyun Jun, Kinam Kim |
1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009, pp. 128-129, 2009, IEEE, 978-1-4244-3458-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Uksong Kang, Hoeju Chung, Seongmoo Heo, Soon-Hong Ahn, Hoon Lee, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jin Ho Kim, Jaewook Lee, Han-Sung Joo, Woo-Seop Kim, Hyun-Kyung Kim, Eun-Mi Lee, So-Ra Kim, Keum-Hee Ma, Dong-Hyun Jang, Nam-Seog Kim, Man-Sik Choi, Sae-Jang Oh, Jung-Bae Lee, Tae-Kyung Jung, Jei-Hwan Yoo, Changhyun Kim |
8Gb 3D DDR3 DRAM using through-silicon-via technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009, pp. 130-131, 2009, IEEE, 978-1-4244-3458-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Xin Yang 0010, Sakir Sezer, John V. McCanny, Dwayne Burns |
DDR3 based lookup circuit for high-performance network processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: Annual IEEE International SoC Conference, SoCC 2009, September 9-11, 2009, Belfast, Northern Ireland, UK, Proceedings, pp. 351-354, 2009, IEEE, 978-1-4244-4940-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura |
An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 42(1), pp. 201-209, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Churoo Park, Hoeju Chung, Yun-Sang Lee, Jaekwan Kim 0003, JaeJun Lee, Moo Sung Chae, Dae-Hee Jung, Sung-Ho Choi, Seung-young Seo, Taek-Seon Park, Jun-Ho Shin, Jin-Hyung Cho, Seunghoon Lee, Ki-Whan Song, Kyu-Hyoun Kim, Jung-Bae Lee, Changhyun Kim, Soo-In Cho |
A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 41(4), pp. 831-838, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura |
An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006, pp. 557-566, 2006, IEEE, 1-4244-0079-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Uk-Rae Cho, Tae-Hyoung Kim, Yong-Jin Yoon, Jong-Cheol Lee, Dae-Gi Bae, Nam-Seog Kim, Kang-Young Kim, Young-Jae Son, Jeong-Suk Yang, Kwon-Il Sohn, Sung-Tae Kim, In-Yeol Lee, Kwang-Jin Lee, Tae-Gyoung Kang, Su-Chul Kim, Kee-Sik Ahn, Hyun-Geun Byun |
A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 38(11), pp. 1943-1951, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Harold Pilo, Darren Anand, John Barth 0001, Steve Burns 0001, Phil Corson, Jim Covino, Steve Lamphier |
A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 38(11), pp. 1974-1980, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Nam-Seog Kim, Yong-Jin Yoon, Uk-Rae Cho, Hyun-Geun Byun |
Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2003, San Jose, CA, USA, September 21 - 24, 2003, pp. 391-394, 2003, IEEE, 0-7803-7842-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #54 of 54 (100 per page; Change: )
|
|