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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 70 occurrences of 60 keywords
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Results
Found 408 publication records. Showing 408 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
98 | Bruce F. Cockburn, Keith Boyle |
Design and Characterization of a Digital Delay Locked Loop Synthesized from Black Box Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1214-1217, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
84 | Yating Wu, Wai Keung Wong, Shu Hung Leung, Y. S. Zhu |
A Modified De-Correlated Delay Lock Loop with Better Static Response for Synchronous DS-CDMA Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 65th IEEE Vehicular Technology Conference, VTC Spring 2007, 22-25 April 2007, Dublin, Ireland, pp. 1796-1800, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
78 | Seungsoo Yoo, Jun Tae Kim, Sun Yong Kim, Youngyoon Lee, Seokho Yoon |
A novel tracking scheme in location systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICUIMC ![In: Proceedings of the 2nd International Conference on Ubiquitous Information Management and Communication, ICUIMC 2008, Suwon, Korea, January 31 - February 01, 2008, pp. 266-269, 2008, ACM, 978-1-59593-993-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
ELP-DLL, EML-DLL, tracking bias, tracking bias compensation, location systems |
74 | Kuo-Hsing Cheng, Yu-Lung Lo |
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE Designers' Forum ![In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 178-182, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-0-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
60 | Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang |
A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1174-1177, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
60 | Atsushi Suzuki, Shoji Kawahito, Daisuke Miyazaki, Masanori Furuta |
A digitally skew correctable multi-phase clock generator using a master-slave DLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 105-108, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
59 | Michael H. Perrott |
Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 498-503, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
fractional-N, sigma, PLL, frequency, delta, DLL, synthesizer |
56 | Yong Shim, Youngkwon Jo, Soo Hwan Kim, Suki Kim, Kwanjun Cho |
A register controlled delay locked loop using a TDC and a new fine delay line scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
56 | Youngkwon Jo, Yong Shim, Soo Hwan Kim, Suki Kim, Kwanjun Cho |
A mixed-structure delay locked-loop with wide range and fast locking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
56 | Tom Egan, Samiha Mourad |
Design-for-testability for embedded delay-locked loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(8), pp. 984-988, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
56 | Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu |
A mixed-mode delay-locked loop for wide-range operation and multiphase outputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 196-199, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
56 | Cheng Jia, Linda S. Milor |
A BIST Solution for The Test of I/O Speed. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 1023-1030, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
56 | Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu, Shu-Yin Hung |
A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June - 2 July 2003, Calgary, Alberta, Canada, pp. 90-93, 2003, IEEE Computer Society, 0-7695-1944-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
54 | Deepak Venugopal, Guoning Hu, Nicoleta Roman |
Intelligent virus detection on mobile devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PST ![In: Proceedings of the 2006 International Conference on Privacy, Security and Trust: Bridge the Gap Between PST Technologies and Business Services, PST 2006, Markham, Ontario, Canada, October 30 - November 1, 2006, pp. 65, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
common functionality, security, mobile, virus detection, DLL |
47 | Cédric Majek, Yann Deval, Hervé Lapuyade, Jean-Baptiste Bégueret |
Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CMOS-SOI, factorial delay locked loop, multi-standard frequency synthesizer, quadrature phase signals, voltage controlled delay element |
47 | Md. Ibrahim Faisal, Magdy A. Bayoumi |
A low-area, low-power programmable frequency multiplier for DLL based clock synthesizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1460-1463, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
47 | Chih-Hsing Lin, Ching-Te Chiu |
A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3888-3891, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Pengfei Li 0001, Rizwan Bashirullah |
A DLL Based Multiphase Hysteretic DC-DC Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 98-101, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Vasco M. Manquinho, João Marques-Silva 0001 |
On Applying Cutting Planes in DLL-Based Algorithms for Pseudo-Boolean Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAT ![In: Theory and Applications of Satisfiability Testing, 8th International Conference, SAT 2005, St. Andrews, UK, June 19-23, 2005, Proceedings, pp. 451-458, 2005, Springer, 3-540-26276-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Stephen K. Sunter, Aubin Roy |
Noise-Insensitive Digital BIST for any PLL or DLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(5), pp. 461-472, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
BIST, Jitter, Design for test, PLL, Mixed-signal test, DLL |
42 | Taeho Kwon, Zhendong Su 0001 |
Automatic detection of unsafe component loadings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSTA ![In: Proceedings of the Nineteenth International Symposium on Software Testing and Analysis, ISSTA 2010, Trento, Italy, July 12-16, 2010, pp. 107-118, 2010, ACM, 978-1-60558-823-0. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
unsafe component loading, dynamic analysis |
42 | Enrique Barajas, R. Cosculluela, D. Coutinho, Diego Mateo, José Luis González 0001, I. Cairò, S. Banda, M. Ikeda |
Interactive presentation: Behavioral modeling of delay-locked loops and its application to jitter optimization in ultra wide-band impulse radio systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1430-1435, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Xiaosheng Wang |
A Generalized Decision Logic Language for Information Tables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFIE ![In: Fuzzy Information and Engineering, Proceedings of the Second International Conference of Fuzzy Information and Engineering, ICFIE 2007, May 13-16, 2007, Guangzhou, China, pp. 16-21, 2007, Springer, 978-3-540-71440-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Decision Logic Language, Information Tables, Rough Sets, Credibility, Decision Rules |
42 | Xiang Gao 0002, Eric A. M. Klumperink, Bram Nauta |
Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2854-2857, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Po-Jen Chuang, Young-Tzong Hsiao, Yu-Shian Chiu |
An Efficient Value Predictor Dynamically Using Loop and Locality Properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 30(1), pp. 19-36, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
loop and locality properties, benchmarks, value prediction, prediction accuracy, hardware cost, experimental performance evaluation |
42 | Jorge Calera-Rubio, José Oncina |
Identifying Left-Right Deterministic Linear Languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICGI ![In: Grammatical Inference: Algorithms and Applications, 7th International Colloquium, ICGI 2004, Athens, Greece, October 11-13, 2004, Proceedings, pp. 283-284, 2004, Springer, 3-540-23410-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
42 | DoRon B. Motter, Igor L. Markov |
A Compressed Breadth-First Search for Satisfiability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ALENEX ![In: Algorithm Engineering and Experiments, 4th International Workshop, ALENEX 2002, San Francisco, CA, USA, January 4-5, 2002, Revised Papers, pp. 29-42, 2002, Springer, 3-540-43977-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
40 | Jaeyong Lee, Sungil Cho, Kwangsub Yoon |
12bits 40mhz pipelined ADC with duty-correction circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 441-444, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
adc(analog-to-digital converter), pipeline, cmos, dll |
40 | Rashed Zafar Bhatti, Monty Denneau, Jeff Draper |
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 198-203, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
CDR, CML driver, LVDS, SerDes, duty cycle correction (DCC), jitter and skew compensation, standard cell based serializer and deserializer circuits for high speed signaling, PLL, DLL, phase detection |
37 | Young-Soo Ryu, Young-Shig Choi |
A DLL Based Clock Synthesizer with Locking Status Indicator A DLL Based Clock Synthesizer with Locking Status Indicator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inform. and Commun. Convergence Engineering ![In: J. Inform. and Commun. Convergence Engineering 3(3), pp. 142-145, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
33 | Cheng Jia, Linda S. Milor |
A BIST Circuit for DLL Fault Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(12), pp. 1687-1695, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Jinn-Shyan Wang, Yi-Ming Wang, Chun-Yuan Cheng, Yu-Chia Liu |
An improved SAR controller for DLL applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski |
A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 701-704, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Stefan Szeider |
Backdoor Sets for DLL Subsolvers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Autom. Reason. ![In: J. Autom. Reason. 35(1-3), pp. 73-88, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
unit propagation, pure literal elimination, backdoor sets, W[P]-completeness, satisfiability, parameterized complexity |
33 | Mathieu Renaud, Yvon Savaria |
A CMOS three-state frequency detector complementary to an enhanced linear phase detector for PLL, DLL or high frequency clock skew measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 148-151, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | S. Nagavarapu, J. Yan, Edward K. F. Lee, Randall L. Geiger |
An asynchronous data recovery/retransmission technique with foreground DLL calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 354-357, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Narayan Prasad, Mahesh K. Varanasi |
Analysis and Optimization of Diagonally Layered Lattice Schemes for MIMO Fading Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 54(3), pp. 1162-1185, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Balaji Srinivasan, Vinay Bhaskar Chandratre, Menka Tewani |
0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 613-619, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | John Keane 0001, Tony Tae-Hyoung Kim, Chris H. Kim |
An on-chip NBTI sensor for measuring PMOS threshold voltage degradation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 189-194, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
locked loop, delay, aging, NBTI |
28 | Bob Stengel, Said Rami |
A 90nm Quadrature Generator with Frequency Extension up to 4GHz. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1697-1700, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Scott L. Rosen, John A. Stine, William J. Weiland |
A MANET simulation tool to study algorithms for generating propagation maps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSC ![In: Proceedings of the Winter Simulation Conference WSC 2006, Monterey, California, USA, December 3-6, 2006, pp. 2219-2224, 2006, IEEE Computer Society, 1-4244-0501-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Volnei A. Pedroni, Ricardo U. Pedroni |
PLL-less clock multiplier with self-adjusting phase symmetry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Ping-Ying Wang, C.-H. Chou, Hsueh-Wu Kao |
Chaos in delay locked loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Enrico Giunchiglia, Marco Maratea |
optsat: A Tool for Solving SAT Related Optimization Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JELIA ![In: Logics in Artificial Intelligence, 10th European Conference, JELIA 2006, Liverpool, UK, September 13-15, 2006, Proceedings, pp. 485-489, 2006, Springer, 3-540-39625-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Lei Shen, Fangni Chen, Shiju Li |
Performance of Coherent Delay Lock Loop in the Presence of CW Interference and Additive Noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMSCCS (1) ![In: Interdisciplinary and Multidisciplinary Research in Computer Science, IEEE CS Proceeding of the First International Multi-Symposium of Computer and Computational Sciences (IMSCCS|06), June 20-24, 2006, Zhejiang University, Hangzhou, China, Vol. 1, pp. 236-242, 2006, IEEE Computer Society, 0-7695-2581-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Mahdi Nazm Bojnordi, Nariman Moezzi Madani, Mehdi Semsarzadeh, Ali Afzali-Kusha |
An Efficient Clocking Scheme for On-Chip Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 119-122, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Enrico Giunchiglia, Marco Maratea |
On the Relation Between Answer Set and SAT Procedures (or, Between cmodels and smodels). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICLP ![In: Logic Programming, 21st International Conference, ICLP 2005, Sitges, Spain, October 2-5, 2005, Proceedings, pp. 37-51, 2005, Springer, 3-540-29208-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Wern-Ho Sheen, Ming-Jou Chang, Cheng-Shong Wu |
Performance analysis of noncoherent digital delay locked loops for direct sequence spread spectrum systems with Doppler shift and quantized adaptation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 3(6), pp. 2108-2118, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Ajay Askoolum |
Building C# COM DLLs for APL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGAPL APL Quote Quad ![In: ACM SIGAPL APL Quote Quad 34(4), pp. 18-26, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Daniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors |
A Mixed-Mode Delay-Locked-Loop Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 261-263, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Pascal Vander-Swalmen, Gilles Dequen, Michaël Krajecki |
On Multi-threaded Satisfiability Solving with OpenMP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWOMP ![In: OpenMP in a New Era of Parallelism, 4th International Workshop, IWOMP 2008, West Lafayette, IN, USA, May 12-14, 2008, Proceedings, pp. 146-157, 2008, Springer, 978-3-540-79560-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
collaborative, parallel, combinatorial optimization, satisfiability, OpenMP, dll |
26 | Richard J. Busman, Walter G. Fil, Andrei V. Kondrashev |
Recycling APL Code into Client/Server Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APL ![In: Proceedings of the 1995 International Conference on Applied Programming Languages, APL 1995, San Antonio, Texas, USA, June 4-8, 1995., pp. 20-27, 1995, ACM, 0-89791-722-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
APL/W, DDE, Dyalog, MS Windows, ODBC, SHARP APL, downsizing APL applications, APL, SQL, client/server, DB2, DLL |
25 | James R. Burnham, Chih-Kong Ken Yang, Haitham A. Hindi |
A stochastic jitter model for analyzing digital timing-recovery circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 116-121, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
delay-locked loop (DLL), mean-time-between-failures (MTBF), timing margins, timing recovery circuits, Markov chain, stochastic model, jitter, bit-error-rate (BER) |
19 | Mohamed Kas, Abderrazak Chahi, Ibrahim Kajo, Yassine Ruichek |
DLL-GAN: Degradation-level-based learnable adversarial loss for image enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Expert Syst. Appl. ![In: Expert Syst. Appl. 237(Part C), pp. 121666, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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19 | Jonas Pelgrims, Kris Myny, Wim Dehaene |
An Ultrasonic Driver Array in Metal-Oxide Thin-Film Technology Using a Hybrid TFT-Si DLL Locking Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(2), pp. 516-527, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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19 | Tao Wang, Jieyang Li, Di Hua, Liangbo Lei, Peng Cao, Peng Xu, Jiawei Xu 0001, Zhiliang Hong |
A Fully Integrated Digital Polar Transmitter With Single-Ended Doherty PA and DLL-Based Three-Segment Hybrid DTC in 28 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(2), pp. 388-399, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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19 | Jisu Park, DaYeon Yoo, Nara Yun, Jihoon Lee, DaeYoub Kim |
A Thread Chaining Attack for Bypassing a DLL Injection Monitoring System*. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE ![In: IEEE International Conference on Consumer Electronics, ICCE 2024, Las Vegas, NV, USA, January 6-8, 2024, pp. 1-4, 2024, IEEE, 979-8-3503-2413-6. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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19 | Pedro Fernández-Álvarez, Ricardo J. Rodríguez |
Module extraction and DLL hijacking detection via single or multiple memory dumps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Forensic Sci. Int. Digit. Investig. ![In: Forensic Sci. Int. Digit. Investig. 44(Supplement), pp. 301505, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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19 | Zhaowen Wang, Peter R. Kinget |
A Very High Linearity Twin Phase Interpolator With a Low-Noise and Wideband Delta Quadrature DLL for High-Speed Data Link Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(4), pp. 1172-1184, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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19 | Saurabh Kumar, Yatendra Kumar Singh |
A Low-Phase-Noise Self-Aligned Sub-Harmonically Injection-Locked PLL Using Aperture Phase Detector-Based DLL Windowing Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 6641-6655, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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19 | Sundaresan Ramachandran, Jeet Rami, Abhinav Shah, Kyounggon Kim, Digvijaysinh Rathod |
Defence against crypto-ransomware families using dynamic binary instrumentation and DLL injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Electron. Secur. Digit. Forensics ![In: Int. J. Electron. Secur. Digit. Forensics 15(4), pp. 424-442, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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19 | Teng-Shen Yang, Huai-Yuan Hsieh, Liang-Hung Lu |
A 2.4-GHz Ring-VCO-Based Sub-Sampling PLL With a -70-dBc Reference Spur by Adopting a Capacitor-Multiplier-Based Sub-Sampling DLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(9), pp. 3545-3556, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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19 | Shenglong Zhuo, Yuwei Wang, Tao Xia, Yifan Wu, Wei Zheng, Miao Sun, Zhihong Lin, Patrick Yin Chiang |
A 200 MHz 14 W Pulsed Optical Illuminator With Laser Driver ASIC and On-Chip DLL-Based Time Interpolator for Indirect Time-of-Flight Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(2), pp. 396-400, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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19 | Shahram Modanlou, Gholamreza Ardeshir, Mohammad Gholami |
A general jitter analysis of DLL considering the jitter accumulation effect of loop capacitor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 103, pp. 104943, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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19 | Yung-Chuan Su, Shi-Yu Huang |
Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8), pp. 2761-2765, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Andres Asprilla, Andreia Cathelin, Yann Deval |
0.45-mW 2.35-3.0 GHz Multiplying DLL with Calibration Loop in 28nm CMOS FD-SOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023, Lisbon, Portugal, September 11-14, 2023, pp. 269-272, 2023, IEEE, 979-8-3503-0420-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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19 | Daehyun Kwon, Heon Su Jeong, Jaemin Choi, Wijong Kim, Jae Woong Kim, Junsub Yoon, Jungmin Choi, Sanguk Lee, Hyunsub Norbert Rie, Jin-Il Lee, Jongbum Lee, Taeseong Jang, JunHyung Kim, Sanghee Kang, Jung-Bum Shin, Yanggyoon Loh, Chang-Yong Lee, Junmyung Woo, Hye-Seung Yu, Changhyun Bae, Reum Oh, Young-Soo Sohn, Changsik Yoo, Jooyoung Lee |
A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023, pp. 412-413, 2023, IEEE, 978-1-6654-9016-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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19 | Gaoyuan Pang, Brian Lee 0003, Jake Jung, Chris Eom |
A Fast-Lock DLL with Prediction-Based Fast-Track FDL Structure for DDR5 SDRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 15th IEEE International Conference on ASIC, ASICON 2023, Nanjing, China, October 24-27, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-1298-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Antonin Verdier, Romain Laborde, Mohamed Ali Kandi, Abdelmalek Benzekri |
A SLAHP in the Face of DLL Search Order Hijacking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UbiSec ![In: Ubiquitous Security - Third International Conference, UbiSec 2023, Exeter, UK, November 1-3, 2023, Revised Selected Papers, pp. 177-190, 2023, Springer, 978-981-97-1273-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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19 | Zhaowen Wang, Yudong Zhang 0006, Yuka Onizuka, Peter R. Kinget |
Multi-Phase Clock Generation for Phase Interpolation With a Multi-Phase, Injection-Locked Ring Oscillator and a Quadrature DLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(6), pp. 1776-1787, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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19 | Dong-Hyun Yoon, Dong-Kyu Jung, Kiho Seong, Jae-Soub Han, Keun-Yong Chung, Ju Eon Kim, Tony Tae-Hyoung Kim, Kwang-Hyun Baek |
A 3.2-GHz 178-fsrms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 30(7), pp. 915-925, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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19 | Yuan Cheng Qian, Yen-Yu Chao, Shen-Iuan Liu |
A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 69(2), pp. 269-273, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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19 | Xingyuan Tong, Jinwu Wu, Dong Chen |
Low-Phase-Error Small-Area 4-Phase DLL With a Single-Ended-Differential-Single-Ended Voltage-Controlled Delay Line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 69(1), pp. 25-29, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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19 | Jun-Yu Yang, Shi-Yu Huang |
Tiny Phase-Error Monitor for Fault and Soft-Error-Tolerant DLL to Support Graceful Degradation and Module-Level Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7), pp. 2337-2347, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Yuhang Xie, Xufeng Liao, Xincai Liu, Lianxi Liu |
A DLL-Based Offset Calibration Loop Technology for Wake-Up Receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTA ![In: 2022 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2022, Xi'an, China, October 28-30, 2022, pp. 42-43, 2022, IEEE, 978-1-6654-9269-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Jonas Pelgrims, Kris Myny, Wim Dehaene |
A 24V Thin-Film Ultrasonic Driver for Haptic Feedback in Metal-Oxide Thin-Film Technology using Hybrid DLL Locking Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 48th IEEE European Solid State Circuits Conference, ESSCIRC 2022, Milan, Italy, September 19-22, 2022, pp. 69-72, 2022, IEEE, 978-1-6654-8494-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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19 | Jeewan Lee, Yoonjae Choi, Chulwoo Kim |
A 266-3750 MHz Wide-Range Adaptive Phase-Rotator-Based All Digital DLL for LPDDR5 Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 2177-2181, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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19 | Shenglong Zhuo, Yuwei Wang, Tao Xia, Yifan Wu, Lichun Xie, Wei Zheng, Zhihong Lin, Miao Sun, Lei Zhao, Yajie Qin, Rui Bai 0001, Patrick Yin Chiang |
An Integrated 200MHz 4A Pulsed Laser Driver with DLL-Based Time Interpolator for Indirect Time-of-Flight Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 3493-3497, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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19 | Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Gyutae Park, Jinil Chung, Kyeong-Min Kim, Hae-Kang Jung, Hyungsoo Kim, Junhyun Chun, Chulwoo Kim |
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 56(6), pp. 1886-1896, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Ching-Yuan Yang, Miao-Shan Li, Ai-Jia Chuang |
A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 29(5), pp. 883-894, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Andres Asprilla, David Cordova, Yann Deval, Hervé Lapuyade, François Rivet |
28nm FDSOI Ultra Low Power 1.5-2.0 GHz Factorial-DLL Frequency Synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 68(2), pp. 602-606, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Fernando Caballero, Luis Merino |
DLL: Direct LIDAR Localization. A map-based localization approach for aerial robots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2103.06112, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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19 | Kentaro Nagai, Jun Shiomi, Hidetoshi Onodera |
A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 104-C(10), pp. 617-624, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Duo Sheng, Chih-Hao Liu, Sih-Ying Chen, Bin-Yang Song, Ying-Chi Chiu, Ming-Han Cai |
DLL-Based Transmit Beamforming IC for High -Frequency Ultrasound Medical Imaging System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE-TW ![In: IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2021, Penghu, Taiwan, September 15-17, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-3328-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Fernando Caballero, Luis Merino |
DLL: Direct LIDAR Localization. A map-based localization approach for aerial robots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IROS ![In: IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS 2021, Prague, Czech Republic, September 27 - Oct. 1, 2021, pp. 5491-5498, 2021, IEEE, 978-1-6654-1714-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Taeyeon Kim, Jongsun Kim |
A 0.8-3.5 GHz Shared TDC-Based Fast-Lock All-Digital DLL with a Built-in DCC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pp. 1-4, 2021, IEEE, 978-1-7281-9201-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Siman Li, Chris Eom, Jake Jung, Brian Lee 0003, Edwin Kim, Kanyu Cao |
Adaptive DLL Update Scheme for Power Fluctuation Immunity Using Phase Error Detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3867-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Dong-Hyun Yoon, Dong-Kyu Jung, Kiho Seong, Tae-Hyeok Eom, Jae-Soub Han, Ju Eon Kim, Tony Tae-Hyoung Kim, Kwang-Hyun Baek |
A 3.2 GHz 178fsrms Jitter Injection Locked Clock Multiplier Using Sub-Sampling FTL and DLL for In-Band Noise Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2021, Busan, Korea, Republic of, November 7-10, 2021, pp. 1-3, 2021, IEEE, 978-1-6654-4350-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Yen-Kuei Lu, Miao-Shan Li, Ching-Yuan Yang, Chin-Lung Lin |
A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2021, Busan, Korea, Republic of, November 7-10, 2021, pp. 1-3, 2021, IEEE, 978-1-6654-4350-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Raman Thukral, Mohit Goswami, Sharayu Jagtap, Sandeep Goyal, Shalabh Gupta |
A Multi-Octave Frequency Range SerDes with a DLL Free Receiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Wafa Feneniche, Khaled Rouabah, Mustapha Flissi, Salim Atia, Salah Eddine Mezaache, Sabrina Meguellati |
Unambiguous method for DLL BOC signals tracking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Commun. Syst. ![In: Int. J. Commun. Syst. 33(9), 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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19 | Dongkyun Kim, Kibong Koo, Yongmi Kim, Dong-Uk Lee, Jaejin Lee, Ki Hun Kwon, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Jong-Sam Kim, Seungwook Oh, Minsu Park, Dain Im, Yongsung Lee, Mingyu Park, Jonghyuck Choi, Junhyun Chun, Kyowon Jin, Sungchun Jang, Jun-Yong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Changhyun Kim, Minsik Han |
A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 55(1), pp. 167-177, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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19 | Wataru Matsuda, Mariko Fujimoto, Takuho Mitsunaga |
Detection of Malicious Tools by Monitoring DLL Using Deep Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Process. ![In: J. Inf. Process. 28, pp. 1052-1064, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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19 | Kyungho Ryu, Kil-Hoon Lee, Jung-Pil Lim, Jinho Kim, Han Su Pae, Junho Park, Hyun-Wook Lim, Jae-Youl Lee |
An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 28(11), pp. 2257-2267, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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19 | Dongjun Park, Jongsun Kim |
A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 39(4), pp. 1715-1734, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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19 | Nico Angeli, Klaus Hofmann |
Low-Power All-Digital Multiphase DLL Design Using a Scalable Phase-to-Digital Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Fundam. Theory Appl. ![In: IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(4), pp. 1158-1168, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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19 | Youngbog Yoon, Hyunsu Park, Chulwoo Kim |
A DLL-Based Quadrature Clock Generator With a 3-Stage Quad Delay Unit Using the Sub-Range Phase Interpolator for Low-Jitter and High-Phase Accuracy DRAM Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. ![In: IEEE Trans. Circuits Syst. 67-II(11), pp. 2342-2346, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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19 | Soyeong Shin, Han-Gon Ko, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Doobock Lee, Hae-Kang Jung, Suhwan Kim, Deog-Kyoon Jeong |
A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 67-II(10), pp. 1814-1818, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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19 | Jaehong Jung, Sangdon Jung, Kyungmin Lee, Jun-Hee Jung, Seungjin Kim, Byungki Han, Seunghyun Oh, Jongwoo Lee |
A 4GHz 0.73psrms-Integrated-Jitter PVT-Insensitive Fractional-N Sub-Sampling Ring PLL with a Jitter-Tracking DLL-Assisted DTC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Honolulu, HI, USA, June 16-19, 2020, pp. 1-2, 2020, IEEE, 978-1-7281-9942-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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19 | Junwon Kim, Jiho Shin, Jung-Taek Seo |
Research on PEB-LDR Data Analysis Technique for DLL Injection Detection on ICS Engineering Workstation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEA ![In: ACM ICEA '20: 2020 ACM International Conference on Intelligent Computing and its Emerging Applications, GangWon Republic of Korea, December 12 - 15, 2020, pp. 35:1-35:7, 2020, ACM, 978-1-4503-8304-2. The full citation details ...](Pics/full.jpeg) |
2020 |
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