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Publication years (Num. hits)
1964-1986 (16) 1987-1990 (15) 1991-1994 (17) 1995-1996 (21) 1997 (19) 1998 (17) 1999 (35) 2000 (36) 2001 (25) 2002 (43) 2003 (37) 2004 (44) 2005 (43) 2006 (44) 2007 (35) 2008 (27) 2009 (22) 2010 (16) 2011 (16) 2012 (15) 2013 (20) 2014-2015 (34) 2016-2017 (27) 2018 (28) 2019 (31) 2020 (23) 2021 (20) 2022 (40) 2023 (39) 2024 (8)
Publication types (Num. hits)
article(378) book(1) incollection(2) inproceedings(430) phdthesis(2)
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Found 824 publication records. Showing 813 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
114Gin Yee, Carl Sechen Clock-Delayed Domino for Adder and Combinational Logic Desig. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
110Kazuya Shimizu, Masaya Takamura, Takanori Shirai, Noriyoshi Itazaki, Kozo Kinoshita Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits. Search on Bibsonomy DELTA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Clock-delayed domino circuit, Fault simulation, crosstalk fault
107David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah Timing verification of sequential domino circuits. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF domino gates, sequential domino circuits, static timing verification, logic testing, input signals
103Jovanka Ciric, Gin Yee, Carl Sechen Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
103Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang Charge sharing fault analysis and testing for CMOS domino logic circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF charge sharing fault analysis, CMOS domino logic circuits, domino logic design, sensitivity measurement, domino gate, fault diagnosis, logic testing, delays, delay, automatic testing, CMOS logic circuits, logic gates, test vectors
100Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone Charge Sharing Fault Detection for CMOS Domino Logic Circuits. Search on Bibsonomy DFT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF charge sharing, cs-vulnerability, pseudo gate, ATPG, domino circuit
92Seoksoo Yoon, Seok-Ryong Yoon, Seon Wook Kim, Chulwoo Kim Charge-Sharing-Problem Reduced Split-Path Domino Logic. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
92Min Zhao 0001, Sachin S. Sapatnekar Timing-driven partitioning and timing optimization of mixedstatic-domino implementations. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
92Maik Bollmann, Rainer Hoischen, Michael Jesikiewicz, Christoph Justkowski, Bärbel Mertsching Playing Domino: A Case Study for an Active Vision System. Search on Bibsonomy ICVS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
92Hans L. Bodlaender, Joost Engelfriet Domino Treewith (Extended Abstract). Search on Bibsonomy WG The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
89Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh Low-power dual Vth pseudo dual Vdd domino circuits. Search on Bibsonomy SBCCI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF NMOS pull-up, low power, domino logic, dual supply voltages, dual threshold voltages
89Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang Optimal Timing for Skew-Tolerant High-Speed Domino Logic. Search on Bibsonomy ISVLSI The full citation details ... 2002 DBLP  DOI  BibTeX  RDF keeper, optimal timing, noise, skew, domino logic, dynamic circuit
87Rouwaida Kanj, Elyse Rosenbaum Critical evaluation of SOI design guidelines. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
82Alexey Glebov, Sergey Gavrilov, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer False-Noise Analysis for Domino Circuits. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
82Gin Yee, Carl Sechen Clock-delayed domino for dynamic circuit design. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
82Erich Grädel Domino Games with an Application to the Complexity of Boolean Algebras with Bounded Quantifier Alternations. Search on Bibsonomy STACS The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
78Aiqun Cao, Ruibing Lu, Chen Li 0004, Cheng-Kok Koh Postlayout optimization for synthesis of Domino circuits. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF optimization, synthesis, Domino logic
78Andrea Frosini, Giulia Simi The Reconstruction of a Bicolored Domino Tiling from Two Projections. Search on Bibsonomy DGCI The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Domino tiling, Reconstruction Problem, NP-completeness
76Mohab Anis, Mohamed W. Allam, Mohamed I. Elmasry Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
71Peiyi Zhao, Jason McNeely, Magdy A. Bayoumi, Pradeep Kumar Golconda, Weidong Kuang A Low Power Domino with Differential-Controlled-Keeper. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
71Wei Ling, Yvon Savaria Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
71Kwang-Il Oh, Lee-Sup Kim A clock delayed sleep mode domino logic for wide dynamic OR gate. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF clock delay, low power, leakage, sleep mode, dynamic circuits
71Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain. Search on Bibsonomy DATE The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
71Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
71Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang Charge-sharing alleviation and detection for CMOS domino circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
71Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang Skew-tolerant high-speed (STHS) domino logic. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
67Zhiyu Liu, Volkan Kursun Leakage current starved domino logic. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF gate oxide tunneling, sleep mode, domino logic, subthreshold leakage current, dual threshold voltage
67Zhiyu Liu, Volkan Kursun Leakage Biased Sleep Switch Domino Logic. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF gate oxide tunneling, sleep mode, Domino logic, subthreshold leakage current, dual threshold voltage
67Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell Electrical Behavior of GOS Fault affected Domino Logic Cell. Search on Bibsonomy DELTA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Gate-Oxide Short (GOS), Electrical analysis Boolean test, Domino logic, Defect modeling
67Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peiravi A high speed and leakage-tolerant domino logic for high fan-in gates. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF high speed, noise immunity, deep submicron, fan-in, domino
67Aiqun Cao, Cheng-Kok Koh Post-layout logic optimization of domino circuits. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF optimization, synthesis, layout, domino logic
67Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang Low-swing clock domino logic incorporating dual supply and dual threshold voltages. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF low swing clock, low power, domino logic, dual supply voltage, dual threshold voltage
67Eric W. MacDonald, Nur A. Touba Testing domino circuits in SOI technology. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF silicon-on-insulator, SOI technology, dynamic circuit styles, fault modeling analysis, overall fault coverage, parasitic bipolar leakage, CMOS logic, logic testing, integrated circuit testing, automatic testing, fault simulation, CMOS logic circuits, leakage currents, domino circuits
67Alvernon Walker, Algernon P. Henry, Parag K. Lala An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring. Search on Bibsonomy DFT The full citation details ... 1997 DBLP  DOI  BibTeX  RDF bridging faults detection, CMOS domino logic circuits, dynamic power supply current monitoring, CMOS logic circuits, transient current
65Debasis Samanta, Nishant Sinha 0001, Ajit Pal Synthesis of High Performance Low Power Dynamic CMOS Circuits. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
64Malgorzata Domino, Krzysztof Domino, Zdzislaw Gajewski An application of higher order multivariate cumulants in modelling of myoelectrical activity of porcine uterus during early pregnancy. Search on Bibsonomy Biosyst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
61Alvaro A. Cárdenas, Svetlana Radosavac, John S. Baras Evaluation of detection algorithms for MAC layer misbehavior: theory and experiments. Search on Bibsonomy IEEE/ACM Trans. Netw. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF CUSUM, SPRT, intrusion detection, DOMINO, misbehavior, IEEE 802.11 MAC
60Hadrien Cambazard, John Horan, Eoin O'Mahony, Barry O'Sullivan Fast and Scalable Domino Portrait Generation. Search on Bibsonomy CPAIOR The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
60Massimo Alioto, Gaetano Palumbo, Melita Pennisi Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic. Search on Bibsonomy PATMOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
60Dhiren M. Parmar, Monalisa Sarma, Debasis Samanta A Novel Approach to Domino Circuit Synthesis. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
60Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy 0001 Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies. Search on Bibsonomy ISQED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
60Ge Yang 0004, Zhongda Wang, Sung-Mo Kang Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
60Volkan Kursun, Eby G. Friedman Domino logic with variable threshold voltage keeper. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
60Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang Timing constraints for domino logic gates with timing-dependent keepers. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
60Rahul Kundu, R. D. (Shawn) Blanton ATPG for Noise-Induced Switch Failures in Domino Logic. Search on Bibsonomy ICCAD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
60Roy Mader, Ivan S. Kourtev Reduced dynamic swing domino logic. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
60Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang Noise constrained transistor sizing and power optimization for dual Vst domino logic. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
60Sungwook Kim, Gerald E. Sobelman Efficient digit-serial FIR filters with skew-tolerant domino. Search on Bibsonomy ISCAS (4) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
60Ramin Rafati, A. Z. Charaki, G. R. Chaji, Seid Mehdi Fakhraie, Kenneth Carless Smith Comparison of a 17 b multiplier in Dual-rail domino and in Dual-rail D3L (D4L) logic styles. Search on Bibsonomy ISCAS (3) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
60Hendrawan Soeleman, Kaushik Roy 0001, Bipul Chandra Paul Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic. Search on Bibsonomy VLSI Design The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
60Jonathan T.-Y. Chang, Edward J. McCluskey Detecting resistive shorts for CMOS domino circuits. Search on Bibsonomy ITC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
60Niraj K. Jha Testing for multiple faults in domino-CMOS logic circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
56Jinhui Wang, Lei Zuo, Na Gong, Daming Gao, Shuqin Geng, Wang Zhang, Ligang Hou, Xiaohong Peng, Wuchen Wu Estimation for Speed and Leakage Power of Dual Threshold Domino OR Based on Wavelet Neural Networks. Search on Bibsonomy ISNN (1) The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Dual threshold domino OR, Leakage power, Speed, Wavelet Neural Networks
56Bo Fu, Qiaoyan Yu, Paul Ampadu Energy-delay minimization in nanoscale domino logic. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF delay, energy, leakage, low voltage, domino
56Zhiyu Liu, Volkan Kursun Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Low Voltage Swing, Gate Oxide Leakage, Domino Logic, Subthreshold Leakage, Dual Threshold Voltage
56Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang Minimum delay optimization for domino circuits - a coupling-aware approach. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Logic synthesis, coupling, domino logic, delay minimization
56Jung-Lin Yang, Erik Brunvand Using dynamic domino circuits in self-timed systems. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF asynchronous circuits, domino logic, self-timed circuits
56Ayoob E. Dooply, Kenneth Y. Yun Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines. Search on Bibsonomy ARVLSI The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Self-resetting domino, time borrowing, roadblock, skew tolerance design-for-testability, scan register, multiple stuck fault
56Ron Lin Shift Switching with Domino Logic: Asynchronous VLSI Comparator Schemes. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF shift switching, asynchronous VLSI comparator, precharged CMOS domino logic, VLSI, semaphore
54Min Zhao 0001, Sachin S. Sapatnekar Timing-driven partitioning for two-phase domino and mixed static/domino implementations. Search on Bibsonomy ICCAD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
54Volkan Kursun, Eby G. Friedman Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits. Search on Bibsonomy ISQED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
54Mohamed W. Allam, Mohab Anis, Mohamed I. Elmasry High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies. Search on Bibsonomy ISLPED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
49Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
49Yi Liang, Lei Wang 0004, Jianfeng Zhan, Ruihua Di A Performance Model for Domino Mail Server. Search on Bibsonomy CSSE (3) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
49Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou Testable Designs of Multiple Precharged Domino Circuits. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
49Zhiyu Liu, Volkan Kursun PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
49Yi-Yu Liu, TingTing Hwang Crosstalk-Aware Domino-Logic Synthesis. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
49Yi-Yu Liu, TingTing Hwang Crosstalk-aware domino logic synthesis. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
49Chris Worman, Boting Yang On the Computation of Colored Domino Tilings of Simple and Non-simple Orthogonal Polygons. Search on Bibsonomy ISAAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
49William J. Cook, Daniel G. Espinoza, Marcos Goycoolea A Study of Domino-Parity and k-Parity Constraints for the TSP. Search on Bibsonomy IPCO The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
49Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh Low-power domino circuits using NMOS pull-up on off-critical paths. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
49Amir Amirabadi, Y. Mortazavi, Nariman Moezzi Madani, Ali Afzali-Kusha, Mehrdad Nourani Domino logic with an efficient variable threshold voltage keeper. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
49Yonghee Im, Kaushik Roy 0001 LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits. Search on Bibsonomy ISVLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
49P. C. Chen, James B. Kuo Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
49Yonghee Im, Kaushik Roy 0001 A logic-aware layout methodology to enhance the noise immunity of domino circuits. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
49Rahul Kundu, R. D. (Shawn) Blanton Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
49Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm A technique for Improving dual-output domino logic. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
49B. Chappell, Xinning Wang, Priyadarsan Patra, Prashant Saxena, J. Vendrell, Satyanarayan Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain A System-Level Solution to Domino Synthesis with 2 GHz Application. Search on Bibsonomy ICCD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
49Volkan Kursun, Eby G. Friedman Low swing dual threshold voltage domino logic. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
49Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou On Testability of Multiple Precharged Domino Logic. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
49Tan-Li Chou, Kaushik Roy 0001 Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
49Niraj K. Jha Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
49Alan M. Sykes A second generation DOMINO for statisticians. Search on Bibsonomy APL The full citation details ... 1987 DBLP  DOI  BibTeX  RDF APL
45Rong Lin, Koji Nakano, Stephan Olariu, Albert Y. Zomaya An Efficient Parallel Prefix Sums Architecture with Domino Logic. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF shift switching, binary prefix sums, binary counting, VLSI design, scalable architectures, domino logic, Hardware-algorithms
45Min Zhao 0001, Sachin S. Sapatnekar Technology mapping algorithms for domino logic. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF XOR/XNOR logic, dual-monotonic gates, parameterized library, phase assignment, synthesis, technology mapping, Domino logic
45C. Mohan 0001 A Database Perspective on Lotus Domino/Notes. Search on Bibsonomy SIGMOD Conference The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Lotus Domino, heterogeneous data access, groupware, replication, recovery, logging, semi-structured data, Lotus Notes, ARIES, Notes
45Rong Lin, Koji Nakano, Stephan Olariu, Albert Y. Zomaya An Efficient VLSI Architecture Parallel Prefix Counting With Domino Logic. Search on Bibsonomy IPPS/SPDP The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Special-purpose parallel architectures, digital signal processing, computer arithmetic, VLSI design, domino logic
43Volkan Kursun, Zhiyu Liu Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43T. J. Thorp, G. S. Yee, Carl M. Sechen Design and synthesis of dynamic circuits. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
43Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy 0001 Synthesis of Selectively Clocked Skewed Logic Circuits. Search on Bibsonomy ISQED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
43Alexandre Solomatnikov, Kaushik Roy 0001, Cheng-Kok Koh, Dinesh Somasekhar Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. Search on Bibsonomy ICCD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
43Eric Gayles, Kevin P. Acken, Robert Michael Owens, Mary Jane Irwin A Clocked, Static Circuit Technique for Building Efficient High Frequency Pipelines. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
43Norman D. Thomson Applying Matrix Divide in APL and J. Search on Bibsonomy APL The full citation details ... 1994 DBLP  DOI  BibTeX  RDF APL, J
40Walid Elgharbawy, Pradeep Golconda, Magdy A. Bayoumi Noise-tolerant high fan-in dynamic CMOS circuit design. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF high fan-in domino, CMOS, noise-tolerant, subthreshold leakage, dynamic circuits
40Fatih Hamzaoglu, Mircea R. Stan Circuit-level techniques to control gate leakage for sub-100nm CMOS. Search on Bibsonomy ISLPED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF low power, MTCMOS, gate leakage, domino circuits
40Ruchir Puri, Andrew Bjorksten, Thomas E. Rosser Logic optimization by output phase assignment in dynamic logic synthesis. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF dynamic logic synthesis, logic duplication, minimum logic duplication penalty, output phase assignment, logic design, heuristic algorithms, optimal algorithms, domino logic, logic optimization, area overhead, logic functions, inverters
38Maxim Raya, Imad Aad, Jean-Pierre Hubaux, Alaeddine El Fawal DOMINO: Detecting MAC Layer Greedy Behavior in IEEE 802.11 Hotspots. Search on Bibsonomy IEEE Trans. Mob. Comput. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF greedy behavior, IEEE 802.11, medium access control, network monitoring, wireless local-area networks, Public networks
38Amir Amirabadi, A. Chehelcheraghi, S. H. Rasouli, A. Seyedi, Ali Afzali-Kusha Low power and high performance clock delayed domino logic using saturated keeper. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
38Jo C. Ebergen, Jonathan Gainsley, Jon K. Lexau, Ivan E. Sutherland GasP Control for Domino Circuits. Search on Bibsonomy ASYNC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
38Aiqun Cao, Ruibing Lu, Cheng-Kok Koh Post-layout logic duplication for synthesis of domino circuits with complex gates. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
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