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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 147 occurrences of 98 keywords
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Results
Found 384 publication records. Showing 350 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
147 | Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Chu |
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 422-427, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
94 | Yehea I. Ismail, Eby G. Friedman, José Luis Neves |
Equivalent Elmore delay for RLC trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1), pp. 83-97, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
94 | Nevine Nassif, Madhav P. Desai, Dale H. Hall |
Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 230-235, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
reconstruction, emulation, visibility, functional simulation |
94 | Rohini Gupta, Bogdan Tutuianu, Lawrence T. Pileggi |
The Elmore delay as a bound for RC trees with generalized input signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(1), pp. 95-104, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
81 | Satoshi Tayu, Mineo Kaneko |
Characterization and computation of Steiner wiring based on Elmore's delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (2) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 335-340, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
76 | Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao |
Bounded-skew clock and Steiner routing under Elmore delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 66-71, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
bounded-skew, pathlength delay, VLSI, global routing, Elmore delay, zero-skew, zero-skew, clock routing, routing trees |
67 | Andrew B. Kahng, Chung-Wen Albert Tsao |
Low-cost single-layer clock trees with exact zero Elmore delay skew. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 213-218, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
67 | Youxin Gao, D. F. Wong 0001 |
Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 512-516, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
67 | Yehea I. Ismail, Eby G. Friedman, José Luis Neves |
Signal waveform characterization in RLC trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 190-193, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
67 | Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins |
Near-optimal critical sink routing tree constructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12), pp. 1417-1436, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
63 | Youxin Gao, D. F. Wong 0001 |
Optimal shape function for a bi-directional wire under Elmore delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 622-627, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Bi-directional wire, Optimal shape, Elmore Delay |
63 | Chung-Ping Chen, Hai Zhou 0001, D. F. Wong 0001 |
Optimal non-uniform wire-sizing under the Elmore delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 38-43, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Elmore delay model, IBM RS/6000 workstation, NWSA-db, NWSA-md, NWSA-wd algorithm, general routing trees, maximum sink delay, minimization objectives, optimal nonuniform wire sizing, routing-tree problem, sink-delay bounds, total area, total weighted sink-delays, wire-sizing formula, circuit analysis computing, Lagrangian relaxation |
54 | Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman 0001, Parthasarathi Dasgupta |
Revisiting fidelity: a case of elmore-based Y-routing trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 27-34, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
routing, Steiner trees, fidelity, rank correlation |
54 | Quming Zhou, Kartik Mohanram |
Elmore model for energy estimation in RC trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 965-970, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
RC trees, interconnect, Energy estimation |
54 | Arif Ishaq Abou-Seido, Brian Nowak, Chris Chong-Nuen Chu |
Fitted Elmore delay: a simple and accurate interconnect delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(7), pp. 691-696, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
54 | Manjit Borah, Robert Michael Owens, Mary Jane Irwin |
A fast algorithm for minimizing the Elmore delay to identified critical sinks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7), pp. 753-759, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
54 | John P. Fishburn |
Shaping a VLSI wire to minimize Elmore delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 244-251, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
54 | Jason Cong, Kwok-Shing Leung |
Optimal wiresizing under Elmore delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3), pp. 321-336, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
53 | Kanak Agarwal, Dennis Sylvester, David T. Blaauw |
A simple metric for slew rate of RC circuits based on two circuit moments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(9), pp. 1346-1354, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
53 | Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap |
RC delay metrics for performance optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5), pp. 571-582, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
53 | Youxin Gao, Martin D. F. Wong |
Wire-sizing optimization with inductance consideration using transmission-line model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(12), pp. 1759-1767, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
53 | John Lillis, Premal Buch |
Table-Lookup Methods for Improved Performance-Driven Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 368-373, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
logic synthesis, gate-sizing, fanout optimization |
53 | Andrew B. Kahng, Sudhakar Muddu |
An analytical delay model for RLC interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(12), pp. 1507-1514, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
53 | Chung-Ping Chen, D. F. Wong 0001 |
Optimal Wire-Sizing Function with Fringing Capacitance Consideration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 604-607, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
53 | Andrew B. Kahng, Chung-Wen Albert Tsao |
Planar-DME: a single-layer zero-skew clock tree router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(1), pp. 8-19, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
49 | Lieven Vandenberghe, Stephen P. Boyd, Abbas El Gamal |
Optimal wire and transistor sizing for circuits with non-tree topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 252-259, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
optimal circuit sizing, crosstalk, Elmore delay, clock distribution networks |
49 | Andrew B. Kahng, Kei Masuko, Sudhakar Muddu |
Analytical delay models for VLSI interconnects under ramp input. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 30-36, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
SPICE-computed delay, VLSI routing topologies layout, analytical delay models, arbitrary interconnect trees, interconnect transfer function, performance-driven synthesis, ramp input, source-sink delays, VLSI, Elmore delay, interconnect delays, VLSI interconnects, RLC interconnections |
41 | Min Ni, Seda Ogrenci Memik |
Self-heating-aware optimal wire sizing under Elmore delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1373-1378, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Shuji Tsukiyama, Masahiko Tomita |
An algorithm for calculating correlation coefficients between Elmore interconnect delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Youxin Gao, Martin D. F. Wong |
Optimal shape function for a bidirectional wire under Elmore delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7), pp. 994-999, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
41 | Youxin Gao, D. F. Wong 0001 |
Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 217-220, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
40 | Tao Lin, Lawrence T. Pileggi |
RC(L) interconnect sizing with second order considerations via posynomial programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001, pp. 16-21, 2001, ACM, 1-58113-347-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
RC trees, VLSI design automation, central moments, posynomiality, convex programming, interconnect optimization |
40 | Huibo Hou, Jiang Hu, Sachin S. Sapatnekar |
Non-Hanan routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4), pp. 436-444, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
40 | Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng |
RLC interconnect delay estimation via moments of amplitude and phase response. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 208-213, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
40 | Emrah Acar, Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi |
S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 60-63, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
40 | Noel Menezes, Chung-Ping Chen |
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 476-, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
35 | Dukgwon Lee, Seunghyun Beak, Youngmin Lee, Eunser Lee, Jungkook Kim, Gyung-Leen Park, Taikyeong Jeong |
Minimize the delay of parasitic capacitance and modeling in RLC circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICHIT ![In: Proceedings of the 2009 International Conference on Hybrid Information Technology, ICHIT 2009, Daejeon, Korea, August 27-29, 2009, pp. 614-620, 2009, ACM, 978-1-60558-662-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Elmore, parasitic capacitance, delay, interconnection, oscillator |
35 | Yen-Hung Lin, Shu-Hsin Chang, Yih-Lang Li |
Critical-trunk based obstacle-avoiding rectilinear steiner tree routings for delay and slack optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 151-158, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
elmore delay model, obstacle-avoiding rectilinear steiner tree, performance-driven routing, worst negative slack, timing constraint |
35 | Soroush Abbaspour, Hanif Fatemi, Massoud Pedram |
VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 426-430, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
moment calculation, sources of variation, sensitivity, statistical timing analysis, elmore delay |
35 | Soroush Abbaspour, Amir H. Ajami, Massoud Pedram, Emre Tuncer |
TFA: a threshold-based filtering algorithm for propagation delay and slew calculation of high-speed VLSI interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 19-24, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
elmore, threshold-based filtering algorithm, static timing analysis, moments, AWE |
35 | Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu 0001, Anirudh Devgan |
Closed form expressions for extending step delay and slew metrics to ramp inputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003, pp. 24-31, 2003, ACM, 1-58113-650-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Elmore, slew, delay, timing, interconnects, PDF, moments, median, skewness |
35 | Vasant B. Rao, Jeffrey Soreff, Ravichander Ledalla, Fred L. Yang |
Aggressive crunching of extracted RC netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 70-77, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
RC reduction, TICER, crunching, node elimination, resistor shorting, time constants, interconnect modeling, elmore delay |
35 | Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu 0001, Anirudh Devgan |
PERI: a technique for extending delay and slew metrics to ramp inputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 57-62, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Elmore, slew, delay, interconnects, PDF, moments, median, skewness, standard deviation |
35 | Anirudh Devgan |
Efficient coupled noise estimation for on-chip interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 147-151, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
coupled noise estimation, dynamic logic circuit families, noise criticality pruning, physical design based noise avoidance, circuit simulation, on-chip interconnects, Elmore delay, noise analysis, timing simulation, integrated circuit noise, deep submicron design |
35 | Jason Cong, Lei He 0001 |
Optimal wiresizing for interconnects with multiple sources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 1(4), pp. 478-511, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
bundled refinement, decomposition of multi-source routing tree, dominance property, multi-source net, multi-source routing tree, optimal wiresizing, variable segment-division, high performance, SPICE, fidelity, interconnect optimization, Elmore delay, local refinement, layout optimization |
35 | Manjit Borah, Robert Michael Owens, Mary Jane Irwin |
Fast algorithm for performance-oriented Steiner routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 198-203, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
performance-oriented Steiner routing, fast routing algorithm, Elmore delay minimisation, layout generators, computational complexity, VLSI, data structures, data structures, delays, iterative methods, network routing, circuit layout CAD, integrated circuit layout, iterative techniques |
27 | Ahmed Soltan, Ahmed G. Radwan, Alex Yakovlev |
Elmore delay in the fractional order domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: 2017 European Conference on Circuit Theory and Design, ECCTD 2017, Catania, Italy, September 4-6, 2017, pp. 1-4, 2017, IEEE, 978-1-5386-3974-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
27 | Jiani Xie, C. Y. Roger Chen |
Lookup Table Based Discrete Gate Sizing for Delay Minimization with Modified Elmore Delay Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20 - 22, 2015, pp. 361-366, 2015, ACM, 978-1-4503-3474-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
27 | Mutlu Avci, Serhan Yamaçli |
An improved Elmore delay model for VLSI interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Comput. Model. ![In: Math. Comput. Model. 51(7-8), pp. 908-914, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
27 | Glauco Borges Valim dos Santos, Tiago Reimann, Marcelo O. Johann, Ricardo Reis 0001 |
The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 28th International Conference on Computer Design, ICCD 2010, 3-6 October 2010, Amsterdam, The Netherlands, Proceedings, pp. 195-202, 2010, IEEE Computer Society, 978-1-4244-8936-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
27 | Glauco B. V. dos Santos, Tiago Reimann, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis |
On the accuracy of Elmore-based Delay Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, Yasmine Hammamet, Tunisia, 13-19 December, 2009, pp. 447-450, 2009, IEEE, 978-1-4244-5090-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Satoshi Tayu, Mineo Kaneko |
Characterization and Computation of Steiner Routing Based on Elmore's Delay Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12), pp. 2764-2774, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
27 | Clayton B. McDonald, Randal E. Bryant |
Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001, pp. 283-288, 2001, ACM, 1-58113-297-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Tetsushi Koide, Shin'ichi Wakabayashi |
A timing-driven floorplanning algorithm with the Elmore delay model for building block layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 27(1), pp. 57-76, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Youxin Gao, D. F. Wong 0001 |
Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 27(2), pp. 165-178, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Yehea I. Ismail, Eby G. Friedman, José Luis Neves |
Equivalent Elmore Delay for RLC Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999., pp. 715-720, 1999, ACM Press. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Tetsushi Koide, Shin'ichi Wakabayashi, Mitsuhiro Ono, Yutaka Nishimaru, Noriyoshi Yoshida |
A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 24(1), pp. 53-77, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
27 | Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru |
Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997, pp. 133-140, 1997, IEEE, 0-7803-3663-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
27 | Chung-Ping Chen, Yao-Ping Chen, D. F. Wong 0001 |
Optimal Wire-Sizing Formular Under the Elmore Delay Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996., pp. 487-490, 1996, ACM Press, 0-89791-779-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
27 | Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru |
A new performance driven placement method with the Elmore delay model for row based VLSIs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995, 1995, ACM, 0-89791-766-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
27 | Rohini Gupta, Byron Krauter, Bogdan Tutuianu, John Willis, Lawrence T. Pileggi |
The Elmore Delay as a Bound for RC Trees with Generalized Input Signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 32st Conference on Design Automation, San Francisco, California, USA, Moscone Center, June 12-16, 1995., pp. 364-369, 1995, ACM Press, 0-89791-725-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
27 | Todd D. Hodes, Bernard A. McCoy, Gabriel Robins |
Dynamically-Wiresized Elmore-Based Routing Constructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994, pp. 463-466, 1994, IEEE, 0-7803-1916-8. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
27 | Sachin S. Sapatnekar |
RC Interconnect Optimization Under the Elmore Delay Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 31st Conference on Design Automation, San Diego, California, USA, June 6-10, 1994., pp. 387-391, 1994, ACM Press, 0-7803-1836-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
27 | Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins |
Rectilinear Steiner Trees with Minimum Elmore Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 31st Conference on Design Automation, San Diego, California, USA, June 6-10, 1994., pp. 381-386, 1994, ACM Press, 0-7803-1836-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
27 | Jason Cong, Kwok-Shing Leung |
Optimal wiresizing under the distributed Elmore delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993, Santa Clara, California, USA, November 7-11, 1993, pp. 634-639, 1993, IEEE Computer Society / ACM, 0-8186-4490-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
27 | Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins |
Fidelity and Near-Optimality of Elmore-Based Routing Constructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '93, Cambridge, MA, USA, October 3-6, 1993, pp. 81-84, 1993, IEEE Computer Society, 0-8186-4230-0. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
27 | Zhuo Li 0001, Nancy Ying Zhou, Weiping Shi |
Wire Sizing for Non-Tree Topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5), pp. 872-880, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen |
An efficient gate delay model for VLSI design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 450-455, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Chandramouli V. Kashyap |
Fast Interconnect and Gate Timing Analysis for Performance Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(12), pp. 1383-1388, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Weixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu |
High performance clock routing in X-architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Li-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao |
Maze routing with buffer insertion under transition time constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1), pp. 91-95, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Minghorng Lai, Martin D. F. Wong |
Maze routing with buffer insertion and wiresizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10), pp. 1205-1209, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Li-Da Huang, Minghorng Lai, D. F. Wong 0001, Youxin Gao |
Maze Routing with Buffer Insertion under Transition Time Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 702-707, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Masud H. Chowdhury, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter |
Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 197-200, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Minghorng Lai, D. F. Wong 0001 |
Maze routing with buffer insertion and wiresizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 374-378, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Lieven Vandenberghe, Stephen P. Boyd, Abbas A. El Gamal |
Optimizing dominant time constant in RC circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(2), pp. 110-125, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
27 | Rony Kay, Lawrence T. Pileggi |
EWA: efficient wiring-sizing algorithm for signal nets and clock nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(1), pp. 40-49, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
27 | Rony Kay, Lawrence T. Pileggi |
PRIMO: Probability Interpretation of Moments for Delay Calculation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 463-468, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band |
27 | Noel Menezes, Ross Baldick, Lawrence T. Pileggi |
A sequential quadratic programming approach to concurrent gate and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(8), pp. 867-881, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
27 | Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi |
Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(2), pp. 210-215, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
27 | Noel Menezes, Ross Baldick, Lawrence T. Pileggi |
A sequential quadratic programming approach to concurrent gate and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 144-151, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
RC interconnect, optimization, sequential quadratic programming |
27 | Jirí Vlach, James A. Barby, Anthony Vannelli, T. Talkhan, C.-J. Richard Shi |
Group delay as an estimate of delay in logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(7), pp. 949-953, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
27 | Jean Paul Caisso, Eduard Cerny, Nicholas C. Rumin |
A recursive technique for computing delays in series-parallel MOS transistor circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(5), pp. 589-595, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
27 | Steven Paul McCormick, Jonathan Allen |
Waveform Moment Methods for Improved Interconnection Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 406-412, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
26 | Tad T. Brunyé, Kelsey Booth, Dalit D. Hendel, Kathleen F. Kerr, Hannah Shucard, Donald L. Weaver, Joann G. Elmore |
Machine learning classification of diagnostic accuracy in pathologists interpreting breast biopsies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Am. Medical Informatics Assoc. ![In: J. Am. Medical Informatics Assoc. 31(3), pp. 552-562, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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26 | Nicoleta J. Economou-Zavlanos, Sophia Bessias, Michael P. Cary, Armando Bedoya, Benjamin Goldstein 0001, John Eric Jelovsek, Cara O'Brien, Nancy Walden, Matthew Elmore, Amanda B. Parrish, Scott Elengold, Kay S. Lytle, Suresh Balu, Michael E. Lipkin, Afreen Idris Shariff, Michael Gao, David Leverenz, Ricardo Henao, David Y. Ming, David M. Gallagher, Michael J. Pencina, Eric G. Poon |
Translating ethical and quality principles for the effective, safe and fair development, deployment and use of artificial intelligence technologies in healthcare. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Am. Medical Informatics Assoc. ![In: J. Am. Medical Informatics Assoc. 31(3), pp. 705-713, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
26 | Rui Liu, Jun Hyuk Chang, Riki Otaki, Zhe Heng Eng, Aaron J. Elmore, Michael J. Franklin, Sanjay Krishnan |
Towards Resource-adaptive Query Execution in Cloud Native Databases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIDR ![In: 14th Conference on Innovative Data Systems Research, CIDR 2024, Chaminade, HI, USA, January 14-17, 2024, 2024, www.cidrdb.org. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP BibTeX RDF |
|
26 | John Paparrizos, Chunwei Liu, Aaron J. Elmore, Michael J. Franklin |
Querying Time-Series Data: A Comprehensive Comparison of Distance Measures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Data Eng. Bull. ![In: IEEE Data Eng. Bull. 46(3), pp. 69-88, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
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26 | Benjamin Williams 0003, Will Palmquist, Ryan Elmore |
Simulation-based decision making in the NFL using NFLSimulatoR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 325(1), pp. 731-742, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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26 | John S. Schreck, David John Gagne II, Charlie Becker, William E. Chapman, Kim Elmore, Gabrielle Gantos, Eliot Kim, Dhamma Kimpara, Thomas Martin, Maria J. Molina, Vanessa M. Pryzbylo, Jacob Radford, Belen Saavedra, Justin Willson, Christopher D. Wirz |
Evidential Deep Learning: Enhancing Predictive Uncertainty Estimation for Earth System Science Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2309.13207, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Siyuan Xia, Zhiru Zhu, Chris Zhu, Jinjin Zhao, Kyle Chard, Aaron J. Elmore, Ian T. Foster, Michael J. Franklin, Sanjay Krishnan, Raul Castro Fernandez |
Data Station: Delegated, Trustworthy, and Auditable Computation to Enable Data-Sharing Consortia with a Data Escrow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2305.03842, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Raul Castro Fernandez, Aaron J. Elmore, Michael J. Franklin, Sanjay Krishnan, Chenhao Tan |
How Large Language Models Will Disrupt Data Management. (PDF / PS) ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. VLDB Endow. ![In: Proc. VLDB Endow. 16(11), pp. 3302-3309, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | John Paparrizos, Kaize Wu, Aaron J. Elmore, Christos Faloutsos, Michael J. Franklin |
Accelerating Similarity Search for Elastic Measures: A Study and New Generalization of Lower Bounding Distances. (PDF / PS) ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. VLDB Endow. ![In: Proc. VLDB Endow. 16(8), pp. 2019-2032, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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26 | Georgia Koutrika, Jun Yang 0001, Manos Athanassoulis, Kostas Stefanidis, Ju Fan, Abdul Quamar, Yuanyan Tian, Alekh Jindal, Carsten Binnig, Jennie Rogers, Senjuti Basu Roy, Steven Euijong Whang, Matthias Boehm 0001, Aaron J. Elmore, Vasilis Efthymiou, Xiao Hu 0005, Xiaofang Zhou 0001, Alan D. Fekete |
Front Matter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. VLDB Endow. ![In: Proc. VLDB Endow. 16(12), 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
|
26 | Rui Liu 0002, Aaron J. Elmore, Michael J. Franklin, Sanjay Krishnan |
Rotary: A Resource Arbitration Framework for Progressive Iterative Analytics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDE ![In: 39th IEEE International Conference on Data Engineering, ICDE 2023, Anaheim, CA, USA, April 3-7, 2023, pp. 2140-2153, 2023, IEEE, 979-8-3503-2227-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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26 | Kechun Liu, Beibin Li, Wenjun Wu, Caitlin J. May, Oliver Chang, Stevan Knezevich, Lisa M. Reisch, Joann G. Elmore, Linda G. Shapiro |
VSGD-Net: Virtual Staining Guided Melanocyte Detection on Histopathological Images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WACV ![In: IEEE/CVF Winter Conference on Applications of Computer Vision, WACV 2023, Waikoloa, HI, USA, January 2-7, 2023, pp. 1918-1927, 2023, IEEE, 978-1-6654-9346-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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26 | Cangjiao Wang, Andrew J. Elmore, Izaya Numata, Mark A. Cochrane, Shaogang Lei, Christopher R. Hakkenberg, Yuanyuan Li, Yibo Zhao, Yu Tian |
A Framework for Improving Wall-to-Wall Canopy Height Mapping by Integrating GEDI LiDAR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Remote. Sens. ![In: Remote. Sens. 14(15), pp. 3618, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Andre Kleyner, David Elmore |
Warranty data maturity - Effect of observation time on reliability prediction and the warranty management process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Qual. Reliab. Eng. Int. ![In: Qual. Reliab. Eng. Int. 38(5), pp. 2388-2404, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Sachin Mehta, Ximing Lu, Wenjun Wu, Donald L. Weaver, Hannaneh Hajishirzi, Joann G. Elmore, Linda G. Shapiro |
End-to-End diagnosis of breast biopsy images with transformers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Medical Image Anal. ![In: Medical Image Anal. 79, pp. 102466, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Shima Nofallah, Wenjun Wu, Kechun Liu, Fatemeh Ghezloo, Joann G. Elmore, Linda G. Shapiro |
Automated analysis of whole slide digital skin biopsy images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Frontiers Artif. Intell. ![In: Frontiers Artif. Intell. 5, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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