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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 61 occurrences of 36 keywords
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Results
Found 43 publication records. Showing 43 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
75 | Frank te Beest, Kees van Berkel 0001, Ad M. G. Peeters |
Adding Synchronous and LSSD Modes to Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK, pp. 161-170, 2002, IEEE Computer Society, 0-7695-1540-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
design for testability, asynchronous circuits, scan test, LSSD |
66 | Thomas M. Storey, Bruce McWilliam |
A Test Methodology for High Performance MCMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 10(1-2), pp. 109-118, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
LOCST, AC BIST, delay testing, boundary scan, LSSD, MCM testing |
51 | Kamran Zarrineh, Shambhu J. Upadhyaya, Vivek Chickermane |
System-on-Chip Testability Using LSSD Scan Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 18(3), pp. 83-97, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
45 | Kazuhiro Yamada, Yoshikazu Takahashi |
Vector Memory Expansion System For T33xx Logic Tester. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 392-, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
T33XX LSSD vector pattern DFT |
45 | Jacob Savir |
Distributed Generation of Weighted Random Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(12), pp. 1364-1368, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
WRP, BIST, detection probability, signal probability, LSSD, SRL |
45 | Jacob Savir |
On-Chip Weighted Random Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(1), pp. 41-50, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
WRP, BIST, detection probability, signal probability, LSSD, SRL |
41 | Yu Huang 0005, Keith Gallie |
Diagnosis of defects on scan enable and clock trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 436-437, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards |
Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 672-673, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Yeong-Ruey Shieh, Cheng-Wen Wu |
DC control and observation structures for analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 120-126, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
level-sensitive scan-design, test points, DC voltage levels, diagnosis capability, calibration process, read-out voltage levels, VLSI, VLSI, fault diagnosis, controllability, controllability, integrated circuit testing, calibration, observability, observability, analog circuits, mixed signal circuits, mixed analogue-digital integrated circuits |
30 | Hugo Ruiz, Mehdi Yedroudj, Marc Chaumont, Frédéric Comby, Gérard Subsol |
LSSD: a Controlled Large JPEG Image Database for Deep-Learning-based Steganalysis "into the Wild". ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2101.01495, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
30 | Hugo Ruiz, Mehdi Yedroudj, Marc Chaumont, Frédéric Comby, Gérard Subsol |
LSSD: A Controlled Large JPEG Image Database for Deep-Learning-Based Steganalysis "Into the Wild". ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPR Workshops (6) ![In: Pattern Recognition. ICPR International Workshops and Challenges - Virtual Event, January 10-15, 2021, Proceedings, Part VI, pp. 470-483, 2020, Springer, 978-3-030-68779-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
30 | Leonardo Rezende Juracy, Matheus T. Moreira, Felipe A. Kuentzer, Fernando Gehm Moraes, Alexandre M. Amory |
An LSSD Compliant Scan Cell for Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Leonardo Rezende Juracy, Matheus Trevisan Moreira, Felipe Augusto Kuentzer, Alexandre de Morais Amory |
Optimized Design of an LSSD Scan Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(2), pp. 765-768, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Kees van Berkel 0001, Ad M. G. Peeters, Frank te Beest |
Adding synchronous and LSSD modes to asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 27(9), pp. 461-471, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Thomas A. Ziaja |
Using LSSD to test modules at the board level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1999, Atlantic City, NJ, USA, 27-30 September 1999, pp. 163-170, 1999, IEEE Computer Society, 0-7803-5753-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Pamela S. Gillis, Francis Woytowich, Kevin McCauley, Ulrich Baur |
Delay test of chip I/Os using LSSD boundary scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 83-90, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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30 | Bernd Könemann, J. Barlow, Paul Chang, R. Gabrielson, C. Goertz, Brion L. Keller, Kevin McCauley, J. Tischer, Vijay S. Iyengar, Barry K. Rosen, T. Williams |
Delay Test: The Next Frontier for LSSD Test Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992, pp. 578-587, 1992, IEEE Computer Society, 0-7803-0760-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
30 | Hideshi Maeno, Koji Nii, S. Sakayanagi, S. Kato |
LSSD Compatible and Concurrently Testable Ram. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992, pp. 608-614, 1992, IEEE Computer Society, 0-7803-0760-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
30 | David M. Wu |
An optimized delay testing technique for LSSD-based VLSI logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 9th IEEE VLSI Test Symposium (VTS'91), 15-17 Apr 1991, Atlantic City, NJ, USA, pp. 239-248, 1991, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
30 | David M. Wu, Charles E. Radke |
Delay Test Effectiveness Evaluation of LSSD-Based VLSI Vogic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 28th Design Automation Conference, San Francisco, California, USA, June 17-21, 1991., pp. 291-295, 1991, ACM, 0-89791395-7. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
30 | Anthony Correale |
Design Considerations of a Static LSSD Polarity Hold Latch Pair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 28(4), pp. 370-378, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
|
30 | D. Leet, P. Shearon, R. France |
A CMOS LSSD Test Generation System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 28(5), pp. 625-635, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
|
30 | Edward B. Eichelberger, Eric Lindbloom |
Random-Pattern Coverage Enhancement and Diagnosis for LSSD Logic Self-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 27(3), pp. 265-272, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
|
30 | Peter Hansen |
New Techniques for Manufacturing Test and Diagnosis of LSSD Boards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1983, Philadelphia, PA, USA, October 1983, pp. 40-45, 1983, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP BibTeX RDF |
|
30 | Franco Motika, John A. Waicukauski, Edward B. Eichelberger, Eric Lindbloom |
An LSSD Pseudo Random Pattern Test System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1983, Philadelphia, PA, USA, October 1983, pp. 283-288, 1983, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP BibTeX RDF |
|
30 | Sumit DasGupta, Prabhakar Goel, Ron G. Walther, Tom W. Williams |
A Variation of LSSD and Its Implications on Design and Test Pattern Generation in VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1982, Philadelphia, PA, USA, November 1982, pp. 63-66, 1982, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP BibTeX RDF |
|
30 | Kewal K. Saluja |
An enhancement of lssd to reduce test pattern generation effort and increase fault coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 19th Design Automation Conference, DAC '82, Las Vegas, Nevada, USA, June 14-16, 1982, pp. 489-494, 1982, ACM/IEEE. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
|
30 | Y. Arzoumanian, John A. Waicukauski |
Fault Diagnosis in an LSSD Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1981, Philadelphia, PA, USA, October 1981, pp. 86-88, 1981, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP BibTeX RDF |
|
30 | Frank C. Hsu, Peter Solecky, Robert E. Beaudoin |
Structured trace diagnosis for LSSD board testing - an alternative to full fault simulated diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 18th Design Automation Conference, DAC '81, Nashville, Tennessee, USA, June 29 - July 1, 1981, pp. 891-897, 1981, ACM/IEEE. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP BibTeX RDF |
|
24 | Amit M. Sheth, Jacob Savir |
Scan Latch Design for Test Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(2), pp. 213-216, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
shift register latch, scan design, hardware overhead, LSSD |
24 | Frank te Beest, Ad M. G. Peeters, Kees van Berkel 0001, Hans G. Kerkhoff |
Synchronous Full-Scan for Asynchronous Handshake Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(4), pp. 397-406, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
L1L2*, DFT, asynchronous circuits, scan design, LSSD |
24 | Jacob Savir |
Distributed BIST Architecture to Combat Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(4), pp. 369-380, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
BIST, LFSR, delay test, MISR, LSSD, SRL |
24 | Jacob Savir |
Design for Testability to Combat Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 407-411, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
BIST, LFSR, Delay Test, MISR, LSSD, SRL |
24 | Jacob Savir |
Reduced Latch Count Shift Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(2), pp. 183-185, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
shift register latch, scan register, shifting clocks, STUMPS architecture, LSSD |
24 | Jacob Savir |
The Bidirectional Double Latch (BDDL). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(1), pp. 65-66, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
shift register latch, shift register failure diagnostics, Design for testability, hardware overhead, LSSD |
24 | Thomas W. Williams, Kenneth P. Parker |
Design for Testability - A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(1), pp. 2-15, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
Built-In Logic Block Observation (BILBO), Level Sensitive Scan Design (LSSD), Random Access Scan, Scan/Set Logic, testing, test generation, self test, Signature Analysis, Scan Path |
21 | Aristides Efthymiou, John Bainbridge, Douglas A. Edwards |
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(12), pp. 1384-1393, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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21 | Aristides Efthymiou, John Bainbridge, Douglas A. Edwards |
Adding Testability to an Asynchronous Interconnect for GALS SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 20-23, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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21 | Thomas W. Williams |
Testing in Nanometer Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 5-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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21 | Jacob Savir |
On Chip Weighted Random Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 343-352, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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21 | Hakim Bederr, Michael Nicolaidis, Alain Guyot |
Analytic approach for error masking elimination in on-line multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 30-37, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
error masking elimination, online multipliers, high precision numbers, scan design approach, internal state observability, DFT approach, sequential circuits, digital arithmetic, fault coverage, multiplying circuits, area overhead |
21 | Sybille Hellebrand, Hans-Joachim Wunderlich |
Tools and devices supporting the pseudo-exhaustive test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 13-17, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
automatic design for testability, Pseudo-exhaustive test |
21 | Paolo Camurati, Paolo Gianoglio, Renato Gianoglio, Paolo Prinetto |
ESTA: an expert system for DFT rule verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(11), pp. 1172-1180, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
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