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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 13 occurrences of 13 keywords
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Results
Found 50 publication records. Showing 50 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
200 | Jeng-Jie Peng, Ming-Dou Ker, Hsin-Chin Jiang |
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 537-540, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
122 | Michael Nicolaidis |
A Low-Cost Single-Event Latchup Mitigation Sscheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, pp. 111-118, 2006, IEEE Computer Society, 0-7695-2620-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Latchup, Single-event effects, singleevent lathcup, SEL, mitigation of single-event effects |
122 | Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh |
A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 μm CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 192-, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
integrated circuit technology, n-guardring, p-guardring, latchup prevention, remote transient, I/O buffer n-channel transistor, 2D device simulator, TMA-MEDICI, substrate resistance, 0.8 micron, VLSI, circuit analysis computing, CMOS integrated circuits, CMOS technology, transients, steady state simulation |
90 | Ming-Dou Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S.-S. Chen, Mu-Chun Wang |
Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 267-272, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
90 | William M. Coughran Jr., Mark R. Pinto, R. Kent Smith |
Computation of steady-state CMOS latchup characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(2), pp. 307-323, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
69 | Nadine Buard, Florent Miller, Cédric Ruby, Rémi Gaillard |
Latchup effect in CMOS IC: a solution for crypto-processors protection against fault injection attacks? ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 63-70, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
69 | Franco Stellari, Peilin Song, Moyra K. McManus, Robert Gauthier 0002, Alan J. Weger, Kiran V. Chatty, Mujahid Muhammad, Pia N. Sanda |
Optical and Electrical Testing of Latchup in I/O Interface Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 236-245, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
54 | Steven H. Voldman |
A review of CMOS latchup and electrostatic discharge (ESD) in bipolar complimentary MOSFET (BiCMOS) Silicon Germanium technologies: Part II - Latchup. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 45(3-4), pp. 437-455, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Gildas Léger, Antonio J. Ginés, Eduardo J. Peralías, Valentin Gutierrez, C. Dominguez, Maria Angeles Jalón, L. Carranza |
A Single-Event Latchup setup for high-precision AMS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: IEEE European Test Symposium, ETS 2023, Venezia, Italy, May 22-26, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-3634-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
27 | Nicholas J. Pieper, Yoni Xiong, Alexandra Feeley, Dennis R. Ball, Bharat L. Bhuva |
Single-Event Latchup Vulnerability at the 7-nm FinFET Node. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2022, Dallas, TX, USA, March 27-31, 2022, pp. 5, 2022, IEEE, 978-1-6654-7950-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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27 | Chao-Yang Chen, Jian-Hsing Lee, Karuna Nidhi, Tzer-Yaa Bin, Geeng-Lih Lin, Ming-Dou Ker |
Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-µm BCD Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2021, Monterey, CA, USA, March 21-25, 2021, pp. 1-4, 2021, IEEE, 978-1-7281-6893-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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27 | Bahar Ajdari, Samwel Sekwao, Ricardo Ascázubi, Adam Neale, Norbert Seifert |
On the Correlation of Laser-induced and High-Energy Proton Beam-induced Single Event Latchup. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: 2020 IEEE International Reliability Physics Symposium, IRPS 2020, Dallas, TX, USA, April 28 - May 30, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-3199-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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27 | S. Guagliardo, Frederic Wrobel, Ygor Q. Aguiar, Jean-Luc Autran, Paul Leroux, Frédéric Saigné, Vincent Pouget, Antoine D. Touboul |
Effect of Temperature on Single Event Latchup Sensitivity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 15th Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2020, Marrakech, Morocco, April 1-3, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-5426-8. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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27 | Guido Quax, Theo Smedes |
An integral injector-victim current transfer model for latchup design rule optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018, pp. 2, 2018, IEEE, 978-1-5386-5479-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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27 | Marko S. Andjelkovic, Vladimir Petrovic, Zoran Stamenkovic, Goran S. Ristic, Goran S. Jovanovic |
Circuit-Level Simulation of the Single Event Transients in an On-Chip Single Event Latchup Protection Switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 31(3), pp. 275-289, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
27 | Marko S. Andjelkovic, Vladimir Petrovic, Zoran Stamenkovic, Goran S. Ristic, Goran S. Jovanovic |
Simulation-Based Analysis of the Single Event Transient Response of a Single Event Latchup Protection Switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015, pp. 255-258, 2015, IEEE Computer Society, 978-1-4799-6779-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
27 | Hui-Wen Tsai, Ming-Dou Ker |
Compensation circuit with additional junction sensor to enhance latchup immunity for CMOS integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: European Conference on Circuit Theory and Design, ECCTD 2015, Trondheim, Norway, August 24-26, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-9877-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
27 | Vladimir Petrovic, Günter Schoof, Zoran Stamenkovic |
Fault-tolerant TMR and DMR circuits with latchup protection switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 54(8), pp. 1613-1626, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
27 | Vladimir Petrovic, Günter Schoof, Zoran Stamenkovic |
Redundant circuits with latchup protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 20th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2013, Abu Dhabi, UAE, December 8-11, 2013, pp. 117-120, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
27 | Hui-Wen Tsai, Ming-Dou Ker, Yi-Sheng Liu, Ming-Nan Chuang |
Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-DAT ![In: 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013, pp. 1-4, 2013, IEEE, 978-1-4673-4435-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
27 | Pan Dong, Long Fan, Suge Yue, Hongchao Zheng, Shougang Du |
Analysis of the New Latchup Model for Deep Sub-micron Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASC ![In: IEEE Ninth International Conference on Dependable, Autonomic and Secure Computing, DASC 2011, 12-14 December 2011, Sydney, Australia, pp. 56-62, 2011, IEEE Computer Society, 978-0-7695-4612-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
27 | Ming-Dou Ker, Che-Lun Hsu, Wen-Yi Chen |
ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 989-992, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
27 | Farzan Farbiz |
Modeling and suppression of latchup ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2010 |
RDF |
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27 | Jae-Young Park, Jong-Kyu Song, Chang-Soo Jang, San-Hong Kim, Won-Young Jung, Taek-Soo Kim |
A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 92-C(5), pp. 671-675, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Farzan Farbiz, Elyse Rosenbaum |
A new compact model for external latchup. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 49(12), pp. 1447-1454, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Ming-Dou Ker, Cheng-Cheng Yen |
Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 43(11), pp. 2533-2545, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Ciaran J. Brennan, Kiran V. Chatty, Jeff Sloan, Paul Dunn, Mujahid Muhammad, Robert Gauthier 0002 |
Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 47(7), pp. 1069-1073, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Shih-Hung Chen, Ming-Dou Ker |
Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 46(7), pp. 1042-1049, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Ming-Dou Ker, Kun-Hsien Lin |
The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 40(8), pp. 1751-1759, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Steven H. Voldman |
A review of latchup and electrostatic discharge (ESD) in BiCMOS RF silicon germanium technologies: Part I - ESD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 45(2), pp. 323-340, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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27 | Chih-Yao Huang, Wei-Fang Chen, Song-Yu Chuan, Fu-Chien Chiu, Jeng-Chou Tseng, I-Cheng Lin, Chuan-Jane Chao, Len-Yi Leu, Ming-Dou Ker |
Design optimization of ESD protection and latchup prevention for a serial I/O IC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 44(2), pp. 213-221, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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27 | Jorge Salcedo-Suñer, Charvaka Duvvury, Roger Cline, Alfonso Cadena-Hernandez |
Latchup in voltage tolerant circuits: a new phenomenon. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 44(4), pp. 549-562, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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27 | Ming-Dou Ker, Kuo-Chun Hsu |
Latchup-free ESD protection design with complementary substrate-triggered SCR devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 38(8), pp. 1380-1392, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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27 | I-Cheng Lin, Chih-Yao Huang, Chuan-Jane Chao, Ming-Dou Ker |
Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 43(8), pp. 1295-1301, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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27 | Franco Stellari, Peilin Song, Moyra K. McManus, Alan J. Weger, Robert Gauthier 0002, Kiran V. Chatty, Mujahid Muhammad, Pia N. Sanda, Philip Wu, Steve Wilson |
Latchup Analysis Using Emission Microscopy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 43(9-11), pp. 1603-1608, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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27 | Ming-Dou Ker, Hsin-Chin Jiang, Jeng-Jie Peng, Tzay-Luen Shieh |
Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001, pp. 113-116, 2001, IEEE, 0-7803-7057-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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27 | Ming-Dou Ker, Wen-Yu Lo, Chung-Yu Wu |
New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, CICC 1999, San Diego, CA, USA, May 16-19, 1999, pp. 143-146, 1999, IEEE, 0-7803-5443-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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27 | Tong Li, Ching-Han Tsai, Elyse Rosenbaum, Sung-Mo Kang |
Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999., pp. 549-554, 1999, ACM Press. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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27 | Ming-Dou Ker, Jeng-Jie Peng |
Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, CICC 1998, Santa Clara, CA, USA, May 11-14, 1998, pp. 537-540, 1998, IEEE, 0-7803-4292-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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27 | Bulent Basaran, Rob A. Rutenbar, L. Richard Carley |
Latchup-aware placement and parasitic-bounded routing of custom analog cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993, Santa Clara, California, USA, November 7-11, 1993, pp. 415-421, 1993, IEEE Computer Society / ACM, 0-8186-4490-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
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27 | Aditya Agrawal, P. V. Srinivas, Gade Sreenivas, Uttiya Dasgupta |
LATCHECK: A Latchup Checker for VLSI Layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 230-235, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
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27 | Enrico Sangiorgi, Mark R. Pinto, Stanley E. Swirhun, Robert W. Dutton |
Two-Dimensional Numerical Analysis of Latchup in a VLSI CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(4), pp. 561-574, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
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21 | Han Liang, Piyush Mishra, Kaijie Wu 0001 |
Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(2), pp. 243-252, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Concurrent error detection, register-transfer level, single-event upsets, hardware redundancy |
21 | Kun-Hsien Lin, Ming-Dou Ker |
ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1182-1185, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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21 | David A. Rennels, Riki Hwang |
Recovery in Fault-Tolerant Distributed Microcontrollers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2001 International Conference on Dependable Systems and Networks (DSN 2001) (formerly: FTCS), 1-4 July 2001, Göteborg, Sweden, Proceedings, pp. 475-480, 2001, IEEE Computer Society, 0-7695-1101-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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21 | Kwan-Do Kim, Young-Kwan Park, Jun-Ha Lee, Jeong-Taek Kong, Hee-Sung Kang, Young-Wug Kim, Seok-Jin Kim |
Three Dimensional Analysis of Thermal Degradation Effects in FDSOI MOSFET's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 87-, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FDSOI, self-heating, finger type, bar type |
21 | Jaume Segura 0001, Carol de Benito, Antonio Rubio 0001, Charles F. Hawkins |
A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(3), pp. 229-239, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
fault modeling, physical defects, gate oxide short |
21 | Ronald J. G. Goossens, Stephen G. Beebe, Zhiping Yu, Robert W. Dutton |
An automatic biasing scheme for tracing arbitrarily shaped I-V curves. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3), pp. 310-317, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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21 | Ke-Chih Wu, Goodwin R. Chin, Robert W. Dutton |
A STRIDE towards practical 3-D device simulation-numerical and visualization considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(9), pp. 1132-1140, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
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21 | Jue-Hsien Chern, John T. Maeda, Lawrence A. Arledge Jr., Ping Yang 0001 |
SIERRA: a 3-D device simulator for reliability modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(5), pp. 516-527, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
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