Search results for "Latchup"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
200	Jeng-Jie Peng, Ming-Dou Ker, Hsin-Chin Jiang	Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
122	Michael Nicolaidis	A Low-Cost Single-Event Latchup Mitigation Sscheme.	IOLTS	2006	DBLP DOI BibTeX RDF	Latchup, Single-event effects, singleevent lathcup, SEL, mitigation of single-event effects
122	Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh	A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 μm CMOS technology.	VLSI Design	1995	DBLP DOI BibTeX RDF	integrated circuit technology, n-guardring, p-guardring, latchup prevention, remote transient, I/O buffer n-channel transistor, 2D device simulator, TMA-MEDICI, substrate resistance, 0.8 micron, VLSI, circuit analysis computing, CMOS integrated circuits, CMOS technology, transients, steady state simulation
90	Ming-Dou Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S.-S. Chen, Mu-Chun Wang	Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process.	ISQED	2001	DBLP DOI BibTeX RDF
90	William M. Coughran Jr., Mark R. Pinto, R. Kent Smith	Computation of steady-state CMOS latchup characteristics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
69	Nadine Buard, Florent Miller, Cédric Ruby, Rémi Gaillard	Latchup effect in CMOS IC: a solution for crypto-processors protection against fault injection attacks?	IOLTS	2007	DBLP DOI BibTeX RDF
69	Franco Stellari, Peilin Song, Moyra K. McManus, Robert Gauthier 0002, Alan J. Weger, Kiran V. Chatty, Mujahid Muhammad, Pia N. Sanda	Optical and Electrical Testing of Latchup in I/O Interface Circuits.	ITC	2003	DBLP DOI BibTeX RDF
54	Steven H. Voldman	A review of CMOS latchup and electrostatic discharge (ESD) in bipolar complimentary MOSFET (BiCMOS) Silicon Germanium technologies: Part II - Latchup.	Microelectron. Reliab.	2005	DBLP DOI BibTeX RDF
27	Gildas Léger, Antonio J. Ginés, Eduardo J. Peralías, Valentin Gutierrez, C. Dominguez, Maria Angeles Jalón, L. Carranza	A Single-Event Latchup setup for high-precision AMS circuits.	ETS	2023	DBLP DOI BibTeX RDF
27	Nicholas J. Pieper, Yoni Xiong, Alexandra Feeley, Dennis R. Ball, Bharat L. Bhuva	Single-Event Latchup Vulnerability at the 7-nm FinFET Node.	IRPS	2022	DBLP DOI BibTeX RDF
27	Chao-Yang Chen, Jian-Hsing Lee, Karuna Nidhi, Tzer-Yaa Bin, Geeng-Lih Lin, Ming-Dou Ker	Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-µm BCD Process.	IRPS	2021	DBLP DOI BibTeX RDF
27	Bahar Ajdari, Samwel Sekwao, Ricardo Ascázubi, Adam Neale, Norbert Seifert	On the Correlation of Laser-induced and High-Energy Proton Beam-induced Single Event Latchup.	IRPS	2020	DBLP DOI BibTeX RDF
27	S. Guagliardo, Frederic Wrobel, Ygor Q. Aguiar, Jean-Luc Autran, Paul Leroux, Frédéric Saigné, Vincent Pouget, Antoine D. Touboul	Effect of Temperature on Single Event Latchup Sensitivity.	DTIS	2020	DBLP DOI BibTeX RDF
27	Guido Quax, Theo Smedes	An integral injector-victim current transfer model for latchup design rule optimization.	IRPS	2018	DBLP DOI BibTeX RDF
27	Marko S. Andjelkovic, Vladimir Petrovic, Zoran Stamenkovic, Goran S. Ristic, Goran S. Jovanovic	Circuit-Level Simulation of the Single Event Transients in an On-Chip Single Event Latchup Protection Switch.	J. Electron. Test.	2015	DBLP DOI BibTeX RDF
27	Marko S. Andjelkovic, Vladimir Petrovic, Zoran Stamenkovic, Goran S. Ristic, Goran S. Jovanovic	Simulation-Based Analysis of the Single Event Transient Response of a Single Event Latchup Protection Switch.	DDECS	2015	DBLP DOI BibTeX RDF
27	Hui-Wen Tsai, Ming-Dou Ker	Compensation circuit with additional junction sensor to enhance latchup immunity for CMOS integrated circuits.	ECCTD	2015	DBLP DOI BibTeX RDF
27	Vladimir Petrovic, Günter Schoof, Zoran Stamenkovic	Fault-tolerant TMR and DMR circuits with latchup protection switches.	Microelectron. Reliab.	2014	DBLP DOI BibTeX RDF
27	Vladimir Petrovic, Günter Schoof, Zoran Stamenkovic	Redundant circuits with latchup protection.	ICECS	2013	DBLP DOI BibTeX RDF
27	Hui-Wen Tsai, Ming-Dou Ker, Yi-Sheng Liu, Ming-Nan Chuang	Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
27	Pan Dong, Long Fan, Suge Yue, Hongchao Zheng, Shougang Du	Analysis of the New Latchup Model for Deep Sub-micron Integrated Circuits.	DASC	2011	DBLP DOI BibTeX RDF
27	Ming-Dou Ker, Che-Lun Hsu, Wen-Yi Chen	ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup.	ISCAS	2010	DBLP DOI BibTeX RDF
27	Farzan Farbiz	Modeling and suppression of latchup		2010	RDF
27	Jae-Young Park, Jong-Kyu Song, Chang-Soo Jang, San-Hong Kim, Won-Young Jung, Taek-Soo Kim	A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits.	IEICE Trans. Electron.	2009	DBLP DOI BibTeX RDF
27	Farzan Farbiz, Elyse Rosenbaum	A new compact model for external latchup.	Microelectron. Reliab.	2009	DBLP DOI BibTeX RDF
27	Ming-Dou Ker, Cheng-Cheng Yen	Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
27	Ciaran J. Brennan, Kiran V. Chatty, Jeff Sloan, Paul Dunn, Mujahid Muhammad, Robert Gauthier 0002	Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs.	Microelectron. Reliab.	2007	DBLP DOI BibTeX RDF
27	Shih-Hung Chen, Ming-Dou Ker	Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
27	Ming-Dou Ker, Kun-Hsien Lin	The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
27	Steven H. Voldman	A review of latchup and electrostatic discharge (ESD) in BiCMOS RF silicon germanium technologies: Part I - ESD.	Microelectron. Reliab.	2005	DBLP DOI BibTeX RDF
27	Chih-Yao Huang, Wei-Fang Chen, Song-Yu Chuan, Fu-Chien Chiu, Jeng-Chou Tseng, I-Cheng Lin, Chuan-Jane Chao, Len-Yi Leu, Ming-Dou Ker	Design optimization of ESD protection and latchup prevention for a serial I/O IC.	Microelectron. Reliab.	2004	DBLP DOI BibTeX RDF
27	Jorge Salcedo-Suñer, Charvaka Duvvury, Roger Cline, Alfonso Cadena-Hernandez	Latchup in voltage tolerant circuits: a new phenomenon.	Microelectron. Reliab.	2004	DBLP DOI BibTeX RDF
27	Ming-Dou Ker, Kuo-Chun Hsu	Latchup-free ESD protection design with complementary substrate-triggered SCR devices.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
27	I-Cheng Lin, Chih-Yao Huang, Chuan-Jane Chao, Ming-Dou Ker	Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product.	Microelectron. Reliab.	2003	DBLP DOI BibTeX RDF
27	Franco Stellari, Peilin Song, Moyra K. McManus, Alan J. Weger, Robert Gauthier 0002, Kiran V. Chatty, Mujahid Muhammad, Pia N. Sanda, Philip Wu, Steve Wilson	Latchup Analysis Using Emission Microscopy.	Microelectron. Reliab.	2003	DBLP DOI BibTeX RDF
27	Ming-Dou Ker, Hsin-Chin Jiang, Jeng-Jie Peng, Tzay-Luen Shieh	Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's.	ICECS	2001	DBLP DOI BibTeX RDF
27	Ming-Dou Ker, Wen-Yu Lo, Chung-Yu Wu	New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's.	CICC	1999	DBLP DOI BibTeX RDF
27	Tong Li, Ching-Han Tsai, Elyse Rosenbaum, Sung-Mo Kang	Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation.	DAC	1999	DBLP DOI BibTeX RDF
27	Ming-Dou Ker, Jeng-Jie Peng	Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology.	CICC	1998	DBLP DOI BibTeX RDF
27	Bulent Basaran, Rob A. Rutenbar, L. Richard Carley	Latchup-aware placement and parasitic-bounded routing of custom analog cells.	ICCAD	1993	DBLP DOI BibTeX RDF
27	Aditya Agrawal, P. V. Srinivas, Gade Sreenivas, Uttiya Dasgupta	LATCHECK: A Latchup Checker for VLSI Layouts.	VLSI Design	1993	DBLP DOI BibTeX RDF
27	Enrico Sangiorgi, Mark R. Pinto, Stanley E. Swirhun, Robert W. Dutton	Two-Dimensional Numerical Analysis of Latchup in a VLSI CMOS Technology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1985	DBLP DOI BibTeX RDF
21	Han Liang, Piyush Mishra, Kaijie Wu 0001	Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Concurrent error detection, register-transfer level, single-event upsets, hardware redundancy
21	Kun-Hsien Lin, Ming-Dou Ker	ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
21	David A. Rennels, Riki Hwang	Recovery in Fault-Tolerant Distributed Microcontrollers.	DSN	2001	DBLP DOI BibTeX RDF
21	Kwan-Do Kim, Young-Kwan Park, Jun-Ha Lee, Jeong-Taek Kong, Hee-Sung Kang, Young-Wug Kim, Seok-Jin Kim	Three Dimensional Analysis of Thermal Degradation Effects in FDSOI MOSFET's.	ISQED	2000	DBLP DOI BibTeX RDF	FDSOI, self-heating, finger type, bar type
21	Jaume Segura 0001, Carol de Benito, Antonio Rubio 0001, Charles F. Hawkins	A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	fault modeling, physical defects, gate oxide short
21	Ronald J. G. Goossens, Stephen G. Beebe, Zhiping Yu, Robert W. Dutton	An automatic biasing scheme for tracing arbitrarily shaped I-V curves.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
21	Ke-Chih Wu, Goodwin R. Chin, Robert W. Dutton	A STRIDE towards practical 3-D device simulation-numerical and visualization considerations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
21	Jue-Hsien Chern, John T. Maeda, Lawrence A. Arledge Jr., Ping Yang 0001	SIERRA: a 3-D device simulator for reliability modeling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF