Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
141 | Hui Min Wang, Chung-Len Lee 0001, Jwu E. Chen |
Factorization of Multi-Valued Logic Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 164-169, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
multi-valued logic function factorization, multi valued logic functions, rectangular covering problem, MVL algebraic factorization algorithm, MVL Boolean properties, purely algebraic factorization algorithm, multilevel implementation, Boolean method, MVL example functions, computational complexity, complexity, Boolean functions, multivalued logic |
115 | Vlad P. Shmerko, Svetlana N. Yanushkevich, Vitaly G. Levashenko, I. Bondar |
Technique of Computing Logic Derivatives for MVL-Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 267-272, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
logic derivatives, partial direct, inverse derivatives, matrix approach, MVL switching circuit, truth vectors, multivalued logic, logic processing, MVL-functions |
110 | Svetlana N. Yanushkevich, Piotr Dziurzanski, Vlad P. Shmerko |
The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 1: LAR Based Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), May 15-18, 2002, Boston, Massachusetts, USA, pp. 202-208, 2002, IEEE Computer Society, 0-7695-1462-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
multiple-valued logic functions, linear word-level expressions, word-level decision diagrams |
110 | Jing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka |
Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 15-20, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
94 | K. Wayne Current, Vojin G. Oklobdzija, Dragan Maksimovic |
Low-Energy Logic Circuit Techniques for Multiple-Valued Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 86-91, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
94 | Zheng Tang, Okihiko Ishizuka, Koichi Tanno |
Learning Multiple-Valued Logic Networks Based on Back Propagation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 270-275, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
multiple-valued logic networks learning, canonical realization, initial parameters, neural nets, simulation results, backpropagation, backpropagation, multivalued logic, parameter space, functional completeness |
94 | Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan |
New MVL-PLA Structures Based on Current-Mode CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 98-103, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic |
80 | Michael S. Wills |
A behavioral model and triggering modes for MVL R-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 226-234, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
73 | Tetsuro Ogi, Takuro Kayahara, Toshio Yamada, Michitaka Hirose |
MVL Toolkit: Software Library for Constructing an Immersive Shared Virtual World. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VR ![In: IEEE Virtual Reality Conference 2004 (VR 2004), 27-31 March 2004, Chicago, IL, USA, Proceedings, pp. 249-250, 2004, IEEE Computer Society, 0-7803-8415-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
73 | Arkadij Zakrevskij, Lev Zakrevski |
Fast Algorithm for Minimizing Reed-Muller Expansions of Systems of Incompletely Specified MVL Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 27th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1997, Antigonish, Nova Scotia, Canada, May 28-30, 1997, Proceedings, pp. 61-65, 1997, IEEE Computer Society, 0-8186-7910-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
63 | Christian Lang 0001, Bernd Steinbach |
Bi-Decomposition of Function Sets in Multiple-Valued Logic for Circuit Design and Data Mining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Artif. Intell. Rev. ![In: Artif. Intell. Rev. 20(3-4), pp. 233-267, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
bi-decomposition, differential calculus, multi-level circuit design, data mining, machine learning, logic synthesis, multiple-valued logic |
63 | Liam P. Maguire, T. Martin McGinnity, L. J. McDaid |
From a Fuzzy Flip-Flop to a MVL Flip-Flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 29th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1999, Freiburg im Breisgau, Germany, May 20-22, 1999, Proceedings, pp. 294-299, 1999, IEEE Computer Society, 0-7695-0161-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
MVL flip-flop, MOS implementation, fuzzy reasoning |
63 | Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan, G. A. Hamid |
On the Synthesis of MVL Functions Using Input and Output Phase Assignments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 27th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1997, Antigonish, Nova Scotia, Canada, May 28-30, 1997, Proceedings, pp. 253-258, 1997, IEEE Computer Society, 0-8186-7910-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
MVL functions synthesis, phase assignments, decomposition based mapping, input matrix, output matrix, matching-count matrix, output function number, maximum matching count, switching operations, switching operators, r-valued functions, logic synthesis, minimization, multivalued logic |
63 | Elena Dubrova, Dilian Gurov, Jon C. Muzio |
The Evaluation of Full Sensitivity for Test Generation in MVL Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 104-111, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
full sensitivity evaluation, MVL circuits, functional level, m-valued n-variable functions, multi-valued logic circuits, fault diagnosis, logic testing, test generation, circuit analysis computing, multivalued logic circuits |
57 | Mostafa I. H. Abd-El-Barr, Bambang A. B. Sarif |
Weighted and Ordered Direct Cover Algorithms for Minimization of MVL Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 48, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
57 | Mitchell A. Thornton |
Spectral Transforms of Mixed-radix MVL Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 16-19 May 2003, Tokyo, Japan, pp. 329-333, 2003, IEEE Computer Society, 0-7695-1918-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
57 | Rolf Drechsler, Dragan Jankovic, Radomir S. Stankovic |
Generic Implementation of DD Packages in MVL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1352-1359, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
54 | |
Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978 ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![IEEE Computer Society Press The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | André Thayse, Marc Davio, Jean-Pierre Deschamps |
Optimization of multivalued decision algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 171-178, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Serge Perrine |
A new aspect of Some Post algebras. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 259, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Tatsuo Higuchi 0001, Hisamitsu Hoshi |
Special-purpose ternary computer for digital filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 47-54, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | James R. Armstrong |
The modular complexity of a tree structured higher radix multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 101-103, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Steve Winker, Larry Wos |
Automated generation of models and counterexamples and its application to open questions in Ternary Boolean algebra. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 251-256, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Malcolm H. Steward |
The arithmetic properties of certain number systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 122-127, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Louis H. Kauffman |
De Morgan Algebras - completeness and recursion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 82-86, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | George Epstein |
A summary of investigations into three and four valued logics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 257, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | K. Wayne Current, Douglas A. Mow |
Applications of multivalued threshold logic in large-scale-intergrated, digital signal processing circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 187, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Louise Martin, Corina Reischer, Ivo G. Rosenberg |
Completeness problems for switching circuits constructed from delayed gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 142-148, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Samuel C. Lee, Yousef M. Ajabnoor |
Digital calculus: ss. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 128-141, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Stanley J. Krolikoski |
A proposed interpretation of lukasiewicz's four-valued system of modal logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 258, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Marc Davio, Jean-Pierre Deschamps |
Addition in signed digit number systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 104-113, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Vason P. Srini |
Iterative realization of multivalued logic systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 188-194, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Abraham Kandel |
On the compactification and enumeration of distinct fuzzy switching functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 87-90, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Stephen C. Crist |
A tri-state logic family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 1-6, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | James H. Pugsley, Charles B. Silio Jr. |
Some I2L circuits for multiple-valued logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 23-31, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Ytzhak H. Levendel, Melvin A. Breuer |
Vector representation of switching and three-valued functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 202-207, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Adit D. Singh, James R. Armstrong |
A simultaneous, radix four, I2L multiplier mechanized via repeated addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 114-121, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Luisa Iturrioz |
Two typical representation theorems for symmetrical Heyting algebras of order n. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 76-81, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Tsutomu Sasao |
An application of multiple-valued logic to a design of programmable logic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 65-72, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Tich T. Dao |
Design and implementation of a non-binary code for byte-organized memory with binary and quaternary logics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 55-64, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Edward J. McCluskey |
Logic design of multi-valued I2L logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 14-22, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | José Luis Huertas, José I. Acha, L. Macias |
On the synthesis of multivalued circuits using principally binary elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 32, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | K. Wayne Current, Douglas A. Mow |
Four-valued threshold logic full adder circuit implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 95-100, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Masao Mukaidono |
The B-ternary logic and its applications to the detection of hazards in combinational switching circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 269-275, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Daniel Etiemble |
TTL circuits for a 4-valued bus a way to reduce package and interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 7-13, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Ira Howard Sack |
Prefilters over an arbitrary Boolean Algebra. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 242-250, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Daniel E. Atkins |
A suggested approach to computer arithmetic for designers of multi-valued logic processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 33-46, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Majid A. H. Abdul-Karim, N. E. Berbat |
A simulataneous analog/ternary converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 73-75, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | David Rine |
Possibility theory: As a means for modeling computer security and protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 276-286, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Motinori Goto, Shinji Kao, Tomoko Ninomiya |
Determination of the fittest number of truth-values and canonical forms of logical functions for a many-valued axiom set by a computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 195-201, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Mark E. Stickel |
Fuzzy four-valued logic for inconsistency and uncertainty. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 91-94, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Jon C. Muzio, T. C. Wesselkamper |
Generalized finite Post algebras. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 235-241, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | James E. Smith, Jean-Pierre Dussault |
Fault secure multiple-valued logic networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 287-297, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | John R. Miller |
Use of an infinite-valued propositional calculus in a document retrieval system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 157-162, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Ytzhak H. Levendel, Melvin A. Breuer |
Mathematical properties of Boolean transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 163-170, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Majid A. H. Abdul-Karim |
A ternary J - K memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 221-225, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Claudio Moraga |
Complex spectral logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 149-156, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Jürgen Fricke |
Decomposition of multiple-valued logic functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 208-212, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | T. C. Yang, Anthony S. Wojcik |
Parallel and serial decompositions of multi-valued sequential machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 179-186, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | Ladislav J. Kohout |
Analysis of computing protection structures by means of multi-valued logic systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 260-268, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
54 | José Luis Huertas, José I. Acha, G. Sanchez Gomez |
Theory and design of multivalued memory elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVL ![In: Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978, pp. 213-220, 1978, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP BibTeX RDF |
|
52 | Ugur Kalay, Marek A. Perkowski, Douglas V. Hall |
Highly Testable Boolean Ring Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 29th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1999, Freiburg im Breisgau, Germany, May 20-22, 1999, Proceedings, pp. 268-274, 1999, IEEE Computer Society, 0-7695-0161-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Boolean Ring Circuits, Easily Testable Multiple-Valued Logic Circuits, Binary Implementation of MVL Circuits |
52 | A. K. Jain, Mostafa I. H. Abd-El-Barr, R. J. Bolton |
Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 216-221, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
current-mode CMOS multiple-valued logic function realization, heuristic based programs, sum of product form expression, HAMLET, Gold heuristic, current mode CMOS, multiple valued logic function realization, direct cover algorithm, logic design, random sample, multivalued logic, CMOS logic circuits, heuristic programming, MVL function |
52 | Zeljko Zilic, Zvonko G. Vranesic |
Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 36-43, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Reed-Muller forms, sparse polynomial interpolation, MVL RM transforms, interpolation, multivalued logic, Reed-Muller codes, polynomial interpolation, incompletely specified functions, computationally efficient algorithm |
52 | Arif Abdul Mannan, Koichi Tanno, Hiroki Tamura, Takako Toyama, Agung Darmawansyah |
Expandable MVL Inverter Compatible with Standard CMOS Process and Its Application to MVL Hysteresis Comparator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 43rd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2013, Toyama, Japan, May 22-24, 2013, pp. 260-265, 2013, IEEE Computer Society, 978-1-4673-6067-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
52 | Peter M. Kelly, T. Martin McGinnity, Liam P. Maguire |
Re-Programmable MVL Circuits and Architecture to Enable Evolvable MVL Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Multiple Valued Log. Soft Comput. ![In: J. Multiple Valued Log. Soft Comput. 9(4), pp. 319-342, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
52 | Gerhard W. Dueck, D. Michael Miller |
RCM-MVL: A Recursive Consensus MVL Minimization Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: Proceedings of the 20th International Symposium on Multiple-Valued Logic, ISMVL 1990, Charlotte, NC, USA, May 23-25, 1990, pp. 136-143, 1990, IEEE Computer Society, 0-8186-2046-3. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
47 | Daniel H.-Y. Teng, Ronald J. Bolton |
Estimation of Average Multiple-Valued Logic Circuit Size Using Monte Carlo Simulation Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 18-21 May 2005, Calgary, Canada, pp. 276-281, 2005, IEEE Computer Society, 0-7695-2336-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Svetlana N. Yanushkevich, Denis V. Popel, Vlad P. Shmerko, V. Cheushev, Radomir S. Stankovic |
Information Theoretic Approach to Minimization of Polynomial Expressions over GF(4). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 265-272, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
multiple-valued logic functions, information theory measures, decision trees, minimization |
47 | Mostafa I. H. Abd-El-Barr, Maher Al-Sherif, Mohamed Osman |
Fault Characterization and Testability Considerations in Multi-Valued Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 29th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1999, Freiburg im Breisgau, Germany, May 20-22, 1999, Proceedings, pp. 262-267, 1999, IEEE Computer Society, 0-7695-0161-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
47 | Takao Waho |
Resonant Tunneling Transistor and Its Application to Multiple-Valued Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 130-139, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
resonant tunnelling transistors, resonant tunneling transistors, multiple-valued logic circuits, multiple stable states, coupled-quantum-well, monostable-multistable logic circuits, multivalued logic circuits, resonant tunneling diodes, circuit stability |
47 | Craig M. Files, Rolf Drechsler, Marek A. Perkowski |
Functional Decomposition of MVL Functions Using Multi-Valued Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 27th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1997, Antigonish, Nova Scotia, Canada, May 28-30, 1997, Proceedings, pp. 27-34, 1997, IEEE Computer Society, 0-8186-7910-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
learning samples, minterms, machine learning, learning (artificial intelligence), minimization, functional decomposition, multi-valued logic, multi-valued decision diagrams, problem complexity, MVL functions |
47 | Mostafa I. H. Abd-El-Barr, Zvonko G. Vranesic, Safwat G. Zaky |
Algorithmic Synthesis of MVL Functions for CCD Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 40(8), pp. 977-986, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
algorithmic synthesis, CCD implementation, sum of products, logic design, many-valued logics, logic circuits, charge-coupled devices, MVL functions, literals |
42 | Dan Olson, K. Wayne Current |
Hardware Implementation of "Supplementary Symmetrical Logic Circuit Structure" Concepts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 371-376, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
MVL Hardware, Ternary Addition, MVL Structure, SUS-LOC |
42 | Elena N. Zaitseva, Tatiana Kalganova, Evgeny G. Kochergov |
Logical Not Polynomial Forms to Represent Multiple-Valued Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 302-307, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
logical not polynomial forms of MVL function, fast discrete orthogonal transform, genetic algorithms, MVL function |
37 | Omid Mirmotahari, Yngvar Berg |
Proposal for a Bidirectional Gate Using Pseudo Floating-Gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 196-200, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
floating-gate (FG), multiple-valued logic (MVL), bidirectional |
37 | Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko |
Experiments on FPRM Expressions for Partially Symmetric Logic Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 141-146, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fixed polarity Reed-Muller expression, symmetric functions, MVL functions |
37 | Lutz J. Micheel, Hans L. Hartnagel |
Interband RTDs with Nanoelectronic HBT-LED Structures for Multiple-Valued Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 80-85, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
heterojunction bipolar transistors, resonant tunnelling devices, light emitting devices, interband RTDs, resonant tunnelling devices, nanoelectronic HBT-LED structures, multiple-valued computation, nanoelectronic arrays, complex signal processing methods, HBT-LED-RTD circuitry, heterojunction bipolar transistors, light emitting devices, internal optical methods, signal summation, precision photon streams, positive-digit radix-2 MVL, A/D conversion capability, optical isolation, buried optical interconnects, microcavity lasers, signal processing, optical interconnections, optical interconnects, multiple-valued logic, multivalued logic circuits, thresholding functions, analogue-digital conversion |
31 | Mark H. Nodine, Craig M. Files |
A Mature Methodology for Implementing Multi-Valued Logic in Silicon. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 2-7, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
one-hot encoding, 1-of-N encoding, domino logic, null value |
31 | Silvia Gabrielli, Markus Hodapp, Roberto Ranon |
Designing a Multipurpose Virtual Laboratory to Support Communities of Practice in Physics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
e-Science ![In: Second International Conference on e-Science and Grid Technologies (e-Science 2006), 4-6 December 2006, Amsterdam, The Netherlands, pp. 139, 2006, IEEE Computer Society, 0-7695-2734-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | M. S. Bhat 0001, H. S. Jamadagni |
Static power minimization in current-mode circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1220-1223, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | M. S. Bhat 0001, H. S. Jamadagni |
Power Optimization in Current Mode Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 175-180, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Soo Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung Soo Kim |
Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 19-22 May 2004, Toronto, Canada, pp. 198-203, 2004, IEEE Computer Society, 0-7695-2130-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Hiroshi Inokawa, Yasuo Takahashi |
Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 16-19 May 2003, Tokyo, Japan, pp. 259-266, 2003, IEEE Computer Society, 0-7695-1918-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Anna M. Tomaszewska, Svetlana N. Yanushkevich, Vlad P. Shmerko |
The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 2: LWL Based Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), May 15-18, 2002, Boston, Massachusetts, USA, pp. 209-215, 2002, IEEE Computer Society, 0-7695-1462-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
multiple-valued logic circuits, word-level decision diagrams |
31 | Makoto Syuto, Jing Shen, Koichi Tanno, Okihiko Ishizuka |
Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 27-32, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
31 | Jong O. Kim, Parag K. Lala, Young Gun Kim, Heung-Soo Kim |
Fault Analysis of the Multiple Valued Logic Using Spectral Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 59-66, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
spectral domain, bridging fault, multiple valued logic, fault analysis |
31 | Gregory E. Beers, Lizy Kurian John |
Novel Memory Bus Driver/Receiver Architecture for Higher Throughput. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 259-264, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
31 | Zeljko Zilic, Zvonko G. Vranesic |
New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 16-23, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
31 | Wenjun Wang, Claudio Moraga |
Design of Multivalued Circuits using Genetic Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 216-223, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
26 | Shulin Zhao 0003, Shibo Huang, Mengting Niu, Lei Xu, Lifeng Xu |
iTTCA-MVL: A multi-view learning model based on physicochemical information and sequence statistical information for tumor T cell antigens identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Biol. Medicine ![In: Comput. Biol. Medicine 170, pp. 107941, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
26 | Jiale Chang, Yanhui Wang, Siya Mi, Yu Zhang 0004 |
MVL-Tra: Multi-view LFM signal source classification using Transformer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 111(Part B), pp. 108967, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | D. Michael Miller, Gerhard W. Dueck |
Function translations and search-based transformation for MVL reversible circuit synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. Comput. Program. ![In: Sci. Comput. Program. 212, pp. 102704, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
26 | D. Michael Miller, Gerhard W. Dueck |
Descending Order Transformation-based Synthesis of MVL Reversible Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 51st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2021, Nur-Sultan, Kazakhstan, May 25-27, 2021, pp. 107-112, 2021, IEEE, 978-1-7281-9224-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
26 | T. Y. S. S. Santosh, Avirup Saha, Niloy Ganguly |
MVL: Multi-View Learning for News Recommendation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGIR ![In: Proceedings of the 43rd International ACM SIGIR conference on research and development in Information Retrieval, SIGIR 2020, Virtual Event, China, July 25-30, 2020, pp. 1873-1876, 2020, ACM, 978-1-4503-8016-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
26 | Mehdi Takbiri, Reza Faghih Mirzaee, Keivan Navi |
Analytical Review of Noise Margin in MVL: Clarification of a Deceptive Matter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 38(9), pp. 4280-4301, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
26 | Ahmad Towhidy, Reza Omidi Gosheblagh, Karim Mohammadi |
An Efficient Current Mode MVL Residue Code Checker for Fault-Tolerant Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 28(14), pp. 1950244:1-1950244:26, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
26 | Mahdieh Nayeri, Peiman Keshavarzian, Maryam Nayeri |
Approach for MVL design based on armchair graphene nanoribbon field effect transistor and arithmetic circuits design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 92, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
26 | Yingchi Mao, Jianhua Zhang, Hai Qi, Longbao Wang |
DNN-MVL: DNN-Multi-View-Learning-Based Recover Block Missing Data in a Dam Safety Monitoring System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 19(13), pp. 2895, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
26 | Nils Przigoda, Judith Przigoda, Robert Wille |
Four-Valued Logic in UML/OCL Models: A "Playground" for the MVL Community. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), Fredericton, NB, Canada, May 21-23, 2019, pp. 61-66, 2019, IEEE, 978-1-7281-0092-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|