Search results for "Macromodel"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
95	Jimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai	Transient analysis of coupled transmission lines characterized with the frequency-dependent losses using scattering-parameter based macromodel.	ICCD	1995	DBLP DOI BibTeX RDF	coupled transmission lines, frequency-dependent losses, scattering-parameter based macromodel, S-parameter macromodel based simulator, circuit analysis computing, transient analysis, transient analysis, transmission lines, losses, S-parameters
92	Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney, Kiran K. Gullapalli	Smoothed form of nonlinear phase macromodel for oscillators.	ICCAD	2008	DBLP DOI BibTeX RDF
92	Chun-Hsu Ko, Jin-Chern Chiou	Fuzzy macromodel for dynamic simulation of microelectromechanical systems.	IEEE Trans. Syst. Man Cybern. Part A	2006	DBLP DOI BibTeX RDF
87	Sudhir Aggarwal	An Enhanced Macromodel for a CMOS Operational Amplifier for HDL Implementation.	VLSI Design	1996	DBLP DOI BibTeX RDF	VHDL-Analog, Non-linear model, Analog IC's, Operational Amplifier, Macromodel
85	Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi	PRIMA: passive reduced-order interconnect macromodeling algorithm.	ICCAD	1997	DBLP DOI BibTeX RDF	MPVL, PRIMA, RLC interconnect circuits, block Arnoldi technique, driver-load models, guaranteed passivity, macromodel passivity, macromodel stability, passive reduced-order interconnect macromodeling algorithm, path tracing algorithm, reduced order N-port models, simulation, CAD, integrated circuit layout, frequency domain, circuit stability
82	Anish Muttreja, Anand Raghunathan, Srivaths Ravi 0001, Niraj K. Jha	Automated Energy/Performance Macromodeling of Embedded Software.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
82	Yunsi Fei, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	A hybrid energy-estimation technique for extensible processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
82	Anish Muttreja, Anand Raghunathan, Srivaths Ravi 0001, Niraj K. Jha	Automated energy/performance macromodeling of embedded software.	DAC	2004	DBLP DOI BibTeX RDF	data serialization, genetic programming, regression, embedded software, symbolic, macromodeling
78	Bing Zhong, Tao Hu, Dawei Fu, Steven L. Dvorak, John L. Prince	A study of a hybrid phase-pole macromodel for transient simulation of complex interconnects structures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
77	Bin Zhang 0011	Online circuit reliability monitoring.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	reliability, circuit, macromodel, online monitoring
69	Tatsuya Koyagi, Masahiro Fukui, Resve A. Saleh	Delay macromodeling and estimation for RTL.	ISCAS	2008	DBLP DOI BibTeX RDF
65	Wei Qiang, Yang Cao, Yuan-yuan Yan, Xun Gao	Power Estimation of CMOS Circuits by Neural Network Macromodel.	ISNN (2)	2006	DBLP DOI BibTeX RDF
65	Xiaolue Lai, Jaijeet S. Roychowdhury	TP-PPV: piecewise nonlinear, time-shifted oscillator macromodel extraction for fast, accurate PLL simulation.	ICCAD	2006	DBLP DOI BibTeX RDF
65	Yang Xu 0017, Xin Li 0001, Peng Li 0001, Lawrence T. Pileggi	Noise Macromodel for Radio Frequency Integrated Circuits.	DATE	2003	DBLP DOI BibTeX RDF
65	Shrutin Ulman	Macromodel for short circuit power dissipation of submicron CMOS inverters and its application to design CMOS buffers.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
65	Jeong-Taek Kong, David Overhauser	Methods to improve digital MOS macromodel accuracy.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
63	Saket Srivastava, Sanjukta Bhanja	Hierarchical Probabilistic Macromodeling for QCA Circuits.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	QCA computing, QCA macromodel, Bayesian networks, Quantum-dot Cellular Automata, probabilistic computing
59	Saurabh K. Tiwary, Rob A. Rutenbar	Scalable trajectory methods for on-demand analog macromodel extraction.	DAC	2005	DBLP DOI BibTeX RDF	trajectory method, analog, SPICE, circuit, macromodel
55	Shweta Chary, Michael L. Bushnell	Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
55	Subodh Gupta, Farid N. Najm	Energy and peak-current per-cycle estimation at RTL.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
51	Mengmeng Ding, Ranga Vemuri	A combined feasibility and performance macromodel for analog circuits.	DAC	2005	DBLP DOI BibTeX RDF	feasibility models, performance macromodeling, active learning
51	Edith Kussener, Hervé Barthélemy, Alexandre Malherbe, Andreas Kaiser	Versatile macromodel for the power supply of submicronic CMOS microprocessors based on voltage down DC-DC converter.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
51	Janusz Zarebski	A new electrothermal dynamic macromodel of the power Darlington transistor for SPICE.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
49	Hao Yu 0001, Yiyu Shi 0001, Lei He 0001, Tanay Karnik	Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power.	ISLPED	2006	DBLP DOI BibTeX RDF	SQP optimization, structured and parameterized macromodel, thermal management and simulation
49	Siddharth Choudhuri, Rabi N. Mahapatra	Energy characterization of filesystems for diskless embedded systems.	DAC	2004	DBLP DOI BibTeX RDF	diskless, flash, macromodel
49	Xin Li 0001, Peng Li 0001, Yang Xu 0017, Lawrence T. Pileggi	Analog and RF circuit macromodels for system-level analysis.	DAC	2003	DBLP DOI BibTeX RDF	analog/RF circuits, macromodel
47	Ming Yang 0033, Wenjian Yu	Reliable Macromodel Generation for the Capacitance Extraction Based on Macromodel-Aware Random Walk Algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
44	Ying Wei 0002, Alex Doboli	Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling.	DAC	2006	DBLP DOI BibTeX RDF	nonlinear macromodel, structural macromodel, analog circuits
41	Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos	On the Limitations of Power Macromodeling Techniques.	ISVLSI	2007	DBLP DOI BibTeX RDF
41	Min Ma, Roni Khazaka	Multi-level Order Reduction with Nonlinear Port Constraints.	ISCAS	2007	DBLP DOI BibTeX RDF
41	Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Anestis Dounavis	Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects.	ASP-DAC	2005	DBLP DOI BibTeX RDF
41	Pavel V. Nikitin, Vikram Jandhyala, Daniel A. White, Nathan Champagne, John D. Rockway, C.-J. Richard Shi, Chuanyi Yang, Yong Wang 0006, Gong Ouyang, Rob Sharpe, John W. Rockway	Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow.	ISQED	2004	DBLP DOI BibTeX RDF
41	Janusz Zarebski, Krzysztof Górecki	The electrothermal model of the linear power supplies.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
41	Ayman I. Kayssi, Karem A. Sakallah	Timing models for gallium arsenide direct-coupled FET logic circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
41	Yun-Cheng Ju, Vasant B. Rao, Resve A. Saleh	Consistency checking and optimization of macromodels.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
37	Chin-Cheng Kuo, Pei-Syun Lin, Chien-Nan Jimmy Liu	A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level.	ASP-DAC	2009	DBLP DOI BibTeX RDF
37	Michael P. Reyes, Ronald S. Fearing	Macromodel for the mechanics of gecko hair adhesion.	ICRA	2008	DBLP DOI BibTeX RDF
37	Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen	SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation.	ICCAD	2003	DBLP DOI BibTeX RDF
37	Adrian Maxim, Danielle Andreu, Marc Cousineau, Jacques Boucher	A novel SPICE behavioral macromodel of operational amplifiers including a high accuracy description of frequency characteristics.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
37	S. Turgis, Daniel Auvergne	A novel macromodel for power estimation in CMOS structures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
37	Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta 0001	A comprehensive fault macromodel for opamps.	ICCAD	1994	DBLP DOI BibTeX RDF
37	Haifang Liao, Wayne Wei-Ming Dai	Capturing time-of-flight delay for transient analysis based on scattering parameter macromodel.	ICCAD	1994	DBLP DOI BibTeX RDF
27	Hao Yu 0001, Yiyu Shi 0001, Lei He 0001, Tanay Karnik	Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
27	Yaseer Arafat Durrani, Ana Abril, Teresa Riesgo	Efficient Power Macromodeling Technique for IP-Based Digital System.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Zhichun Wang, Xiaolue Lai, Jaijeet S. Roychowdhury	PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels.	DAC	2007	DBLP DOI BibTeX RDF
27	Xiaolue Lai, Jaijeet S. Roychowdhury	Fast simulation of large networks of nanotechnological and biochemical oscillators for investigating self-organization phenomena.	ASP-DAC	2006	DBLP DOI BibTeX RDF
27	Min Ma, Alfred Tze-Mun Leung, Roni Khazaka	Sparse macromodels for parametric networks.	ISCAS	2006	DBLP DOI BibTeX RDF
27	Gurpreet Shinh, Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Ihsan Erdin	Efficient and Accurate EMC Analysis of High-Frequency VLSI Subnetworks.	VLSI Design	2006	DBLP DOI BibTeX RDF
27	Hao Yu 0001, Yiyu Shi 0001, Lei He 0001	Fast analysis of structured power grid by triangularization based structure preserving model order reduction.	DAC	2006	DBLP DOI BibTeX RDF	PG grid simulation, model order reduction
27	Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla	Global Passivity Enforcement Algorithm for Macromodels of Interconnect Subnetworks Characterized by Tabulated Data.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
27	Xiaolue Lai, Yayun Wan, Jaijeet S. Roychowdhury	Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise.	ASP-DAC	2005	DBLP DOI BibTeX RDF
27	Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla	Accurate and closed-form SPICE compatible passive macromodels for distributed interconnects with frequency dependent parameters.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
27	Luis Elvira, Ferran Martorell, Xavier Aragonès, José Luis González 0001	A Macromodelling Methodology for Efficient High-Level Simulation of Substrate Noise Generation.	DATE	2004	DBLP DOI BibTeX RDF
27	Jinwoo Choi, Sung-Hwan Min, Joong-Ho Kim, Madhavan Swaminathan, Wendemagegnehu T. Beyene, Chuck Yuan	Modeling and Analysis of Power Distribution Networks for Gigabit Applications.	IEEE Trans. Mob. Comput.	2003	DBLP DOI BibTeX RDF	transmission matrix method, power bus, decoupling, macromodeling, Power distribution network
27	Yuichi Tanji, Akio Ushida, Michel S. Nakhla	Passive closed-form expression of RLCG transmission lines.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
27	Alessandro Bogliolo, Roberto Corgnati, Enrico Macii, Massimo Poncino	Parameterized RTL power models for soft macros.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
27	Alessandro Bogliolo, Roberto Corgnati, Enrico Macii, Massimo Poncino	Parameterized RTL power models for combinational soft macros.	ICCAD	1999	DBLP DOI BibTeX RDF
27	Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi	PRIMA: passive reduced-order interconnect macromodeling algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
27	Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta 0001	Fault macromodeling and a testing strategy for opamps.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	catastrophic fault model, operational amplifier design for testability, analog test, macromodeling, parametric faults
27	Jianfeng Shao, Ramesh Harjani	Macromodeling of analog circuits for hierarchical circuit design.	ICCAD	1994	DBLP DOI BibTeX RDF
27	Dong H. Xie, Michel S. Nakhla	Delay and crosstalk simulation of high-speed VLSI interconnects with nonlinear terminations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
27	Giorgio Casinovi, Alberto L. Sangiovanni-Vincentelli	A macromodeling algorithm for analog circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
24	Ivailo M. Pandiev	Development of PSpice Macromodel for Monolithic Single-Supply Power Amplifiers.	MIXDES	2021	DBLP DOI BibTeX RDF
24	Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov	Development of Time-Varying PLL Macromodel for Jitter Evaluation.	EWDTS	2018	DBLP DOI BibTeX RDF
24	Carlos Sánchez-López, Miguel Ángel Carrasco-Aguilar, F. E. Morales-Lopez	A SPICE-Compatible Nonlinear CCII Macromodel.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
24	Guoyong Shi, Hanbin Hu, Shuwen Deng	Topological Approach to Automatic Symbolic Macromodel Generation for Analog Integrated Circuits.	ACM Trans. Design Autom. Electr. Syst.	2017	DBLP DOI BibTeX RDF
24	Luis A. Duffaut Espinosa, Mads Almassalkhi, Paul Hines, Shoeib Heydari, Jeff Frolik	Towards a macromodel for Packetized Energy Management of resistive water heaters.	CISS	2017	DBLP DOI BibTeX RDF
24	Ailin Zhang, Guoyong Shi	An Automatic Integrator Macromodel Generation Method for Behavioral Simulation of SC Sigma-Delta Modulators.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2016	DBLP DOI BibTeX RDF
24	Eduardo Ortega-Torres, Sergio Ruíz-Hernández, Carlos Sánchez-López	A nonlinear macromodel for current-feedback operational amplifiers.	Microelectron. J.	2015	DBLP DOI BibTeX RDF
24	K. Shawn Watts, Pranav Dalal, Andrew J. Tebben, Daniel L. Cheney, John C. Shelley	Macrocycle Conformational Sampling with MacroModel.	J. Chem. Inf. Model.	2014	DBLP DOI BibTeX RDF
24	Linbin Chen, Fabrizio Lombardi, Jie Han 0001	An enhanced HSPICE macromodel of a PCM cell with threshold switching and recovery behavior.	MWSCAS	2014	DBLP DOI BibTeX RDF
24	Pilin Junsangsri, Fabrizio Lombardi, Jie Han 0001	HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory design.	NANOARCH	2014	DBLP DOI BibTeX RDF
24	Donghwa Shin, Alessandro Sassone, Alberto Bocca, Alberto Macii, Enrico Macii, Massimo Poncino	A compact macromodel for the charge phase of a battery with typical charging protocol.	ISLPED	2014	DBLP DOI BibTeX RDF
24	Konstantin O. Petrosyants, Igor A. Kharitonov, Lev M. Sambursky, V. N. Bogatyrev, Z. M. Povarnitcyna, E. S. Drozdenko	Simulation of total dose influence on analog-digital SOI/SOS CMOS circuits with EKV-RAD macromodel.	EWDTS	2013	DBLP DOI BibTeX RDF
24	Sangho Shin, Kyungmin Kim, Sung-Mo Steve Kang	Memristor macromodel and its application to neuronal spike generation.	ECCTD	2013	DBLP DOI BibTeX RDF
24	Francesc Masana, Javier Chavarria, Domingo Biel, Alberto Poveda, Francesc Guinjoan, Eduard Alarcón	SiC power JFET electrothermal macromodel.	MIXDES	2013	DBLP BibTeX RDF
24	Ting Zhu 0002, Mustafa Berke Yelten, Michael B. Steer, Paul D. Franzon	Application of Surrogate Modeling in Variation-aware Macromodel and Circuit Design.	SIMULTECH	2011	DBLP BibTeX RDF
24	Bhaskar Gopalan	A SPICE Macromodel for the Analysis of Lossy Dispersive Coupled GaAs Interconnect Line System.	VLSI Design	2011	DBLP DOI BibTeX RDF
24	Amir Beygi, Anestis Dounavis	Sensitivity Analysis of Lossy Multiconductor Transmission Lines Based on the Passive Method of Characteristics Macromodel.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
24	José Ángel Díaz-Madrid, Juan Hinojosa, Ginés Doménech-Asensi	Fuzzy logic technique for accurate analog circuits macromodel sizing.	Int. J. Circuit Theory Appl.	2010	DBLP DOI BibTeX RDF
24	Paolo Maffezzoni	Synchronization Analysis of Two Weakly Coupled Oscillators Through a PPV Macromodel.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
24	Paolo Maffezzoni, Dario D'Amore, Saeid Daneshgar, Michael Peter Kennedy	Analysis and Design of Injection-Locked Frequency Dividers by Means of a Phase-Domain Macromodel.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
24	Hao Yu 0001, Xuexin Liu, Hai Wang 0002, Sheldon X.-D. Tan	A fast analog mismatch analysis by an incremental and stochastic trajectory piecewise linear macromodel.	ASP-DAC	2010	DBLP DOI BibTeX RDF
24	Paolo Maffezzoni, Dario D'Amore, Saeid Daneshgar, Michael Peter Kennedy	Estimating the locking range of analog dividers through a phase-domain macromodel.	ISCAS	2010	DBLP DOI BibTeX RDF
24	Shivam Priyadarshi, Nikhil Kriplani, Michael B. Steer, T. Robert Harris	Fast dynamic simulation of VLSI circuits using reduced order compact macromodel of standard cells.	BMAS	2010	DBLP DOI BibTeX RDF
24	Jinghui Xu, Weizheng Yuan, Honglong Chang, Binghe Ma	Angularly parameterized macromodel extraction for microstructures with a large number of terminals.	NEMS	2009	DBLP DOI BibTeX RDF
24	Janusz Zarebski, Krzysztof Górecki	Electrothermal compact macromodel of monolithic switching voltage regulator MC34063A.	Microelectron. Reliab.	2008	DBLP DOI BibTeX RDF
24	Kiran Kumar Garje, Anil Kumar, Santosh Biswas, Amitava Banerjee, Pam Srikanth, Siddhartha Mukhopadhyay	Macromodel Based Fault Simulation of Linear Circuits using Parameter Estimation.	ICIIS	2008	DBLP DOI BibTeX RDF
24	Xiaolue Lai	Frequency-aware PPV: a robust phase macromodel for accurate oscillator noise analysis.	ICCAD	2008	DBLP DOI BibTeX RDF
24	Dimitrios Bountas, Georgios I. Stamoulis, Nestoras E. Evmorfopoulos	A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions.	ICCD	2008	DBLP DOI BibTeX RDF
24	Jin-Gu Lee, Dae Hwan Kim, Jaegab Lee, Dong Myong Kim, Kyeong-Sik Min	A compact HSPICE macromodel of resistive RAM.	IEICE Electron. Express	2007	DBLP DOI BibTeX RDF
24	Chandramouli V. Kashyap, Chirayu S. Amin, Noel Menezes, Eli Chiprout	A nonlinear cell macromodel for digital applications.	ICCAD	2007	DBLP DOI BibTeX RDF
24	Wei Dong 0002, Zhuo Feng, Peng Li 0001	Efficient VCO phase macromodel generation considering statistical parametric variations.	ICCAD	2007	DBLP DOI BibTeX RDF
24	Dmitry Vasilyev, Michal Rewienski, Jacob K. White 0001	Macromodel Generation for BioMEMS Components Using a Stabilized Balanced Truncation Plus Trajectory Piecewise-Linear Approach.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
24	Janusz Zarebski, Krzysztof Górecki	The electrothermal macromodel of voltage mode PWM controllers for SPICE.	Microelectron. J.	2006	DBLP DOI BibTeX RDF
24	Gholamreza Karimi, Sattar Mirzakuchaki	Simulation of substrate coupling in mixed-signal IC's using an efficient and real-time macromodel.	IEICE Electron. Express	2006	DBLP DOI BibTeX RDF
24	Shweta Srivastava, Xiaolue Lai, Jaijeet S. Roychowdhury	Nonlinear Phase Macromodel Based Simulation/Design of PLLs with Superharmonically Locked Dividers.	CICC	2006	DBLP DOI BibTeX RDF
24	B. Haddadin, Min Ma, T. S. Roseanu, Roni Khazaka	Efficient Macromodel for Interconnects Excited by Incident Fields.	CCECE	2006	DBLP DOI BibTeX RDF
24	Dmitry Gorodetsky, Philip Wilsey	Rapid Evaluation of Macromodel Response with the FDTD Method.	CSC	2006	DBLP BibTeX RDF
24	Luis Elvira, Ferran Martorell, Xavier Aragonès, José Luis González 0001	A physical-based noise macromodel for fast simulation of switching noise generation.	Microelectron. J.	2004	DBLP DOI BibTeX RDF