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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 35972 occurrences of 8751 keywords
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Results
Found 74385 publication records. Showing 74378 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
72 | Chuan Yue, Richard Tran Mills, Andreas Stathopoulos, Dimitrios S. Nikolopoulos |
Runtime Support for Memory Adaptation in Scientific Applications via Local Disk and Remote Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPDC ![In: Proceedings of the 15th IEEE International Symposium on High Performance Distributed Computing, HPDC-15, Paris, France, June 19-23, 2006, pp. 183-194, 2006, IEEE, 1-4244-0307-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
memory server, memory adaptation, local disk memory, remote memory capability, shared computational resource, network memory, memory malleability, MPI communication, cache memory, scientific application, virtual memory system |
61 | Chen Ding 0001, Chengliang Zhang, Xipeng Shen, Mitsunori Ogihara |
Gated memory control for memory monitoring, leak detection and garbage collection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance ![In: Proceedings of the 2005 workshop on Memory System Performance, Chicago, Illinois, USA, June 12, 2005, pp. 62-67, 2005, ACM, 1-59593-147-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
memory usage monitoring, object life, preventive memory management, memory leak, program phase |
58 | Justin Teller, Charles B. Silio Jr., Bruce L. Jacob |
Performance characteristics of MAUI: an intelligent memory system architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance ![In: Proceedings of the 2005 workshop on Memory System Performance, Chicago, Illinois, USA, June 12, 2005, pp. 44-53, 2005, ACM, 1-59593-147-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
MAUI memory architecture, SimpleScalar simulator, data-intensive calculations, intelligent memory, memory architecture, vector processing, SIMD processing |
57 | Gertrud S. Joachim |
Memory Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 6(2), pp. 172-175, 1959. The full citation details ...](Pics/full.jpeg) |
1959 |
DBLP DOI BibTeX RDF |
|
56 | Masato Oguchi, Hitoshi Aida, Tadao Saito |
A Proposal for a DSM Architecture Suitable for a Widely Distributed Environment and its Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPDC ![In: Proceedings of the 4th International Symposium on High Performance Distributed Computing (HPDC '95), Washington, DC, USA, August 2-4, 1995., pp. 32-39, 1995, IEEE Computer Society, 0-8186-7088-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
distributed shared memory architecture, widely distributed environment, functionally distributed computing, software programming, replicated shared memory, internal machine memory, SPARCstations, SCRAMNet, latency hiding techniques, performance evaluation, parallel architectures, shared memory systems, distributed memory systems, data prefetching, multi-thread programming, shared virtual memory |
56 | John G. Cleary, Murray Pearson, Husam Kinawi |
The architecture of an optimistic CPU: the WarpEngine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 163-172, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
optimistic CPU, WarpEngine, shared memory CPU, single instructions, memory latency tolerance, executable instructions, TimeWarp algorithm, optimistic, single linear address space, single thread of control, reliability, caches, parallel architectures, fault tolerant computing, concurrency control, synchronisation, synchronisation, shared memory systems, memory architecture, cache storage, memory system, memory model, time stamped, memory accesses, local memory |
51 | Mojtaba Mehrara, Todd M. Austin |
Reliability-aware data placement for partial memory protection in embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance and Correctness ![In: Proceedings of the 2006 workshop on Memory System Performance and Correctness, San Jose, California, USA, October 11, 2006, pp. 11-18, 2006, ACM, 1-59593-578-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
memory lifetime, partial memory protection, selective data placement, embedded systems, soft errors |
51 | Richard Tran Mills, Chuan Yue, Andreas Stathopoulos, Dimitrios S. Nikolopoulos |
Runtime and Programming Support for Memory Adaptation in Scientific Applications via Local Disk and Remote Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Grid Comput. ![In: J. Grid Comput. 5(2), pp. 213-234, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Shared computational pools, Network RAM, Scientific libraries, Autonomic computing, Memory management |
50 | Henk L. Muller, Paul W. A. Stallard, David H. D. Warren |
The Role of Associative Memory in Virtual Shared Memory Architectures: A Price-Performance Comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), January 24-26, 1996, Portugal, pp. 41-49, 1996, IEEE Computer Society, 0-8186-7376-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
virtual shared memory architectures, price-performance, set associative memory, large coherent cache, performance evaluation, benchmarks, parallel machines, memory hierarchy, shared memory systems, costing, cost, associative memory, memory architecture, content-addressable storage, application specific, virtual storage, CC-NUMA, COMA, miss ratios |
49 | Sajal K. Das 0001, Sanjoy K. Sen |
Analysis of Memory Interference in Buffered Multiprocessor Systems in Presence of Hot Spots and Favorite Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 281-285, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
buffered multiprocessor systems, discrete Markov chain model, processor-memory interconnections, hot memory, favorite memory, mean queue length, memory request, asymptotic bandwidth, performance evaluation, Markov processes, shared memory systems, upper bound, hot spots, simulation studies, memory interference, mean waiting time |
49 | Peter S. Magnusson, Bengt Werner |
Efficient memory simulation in SimICS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 28st Annual Simulation Symposium (SS '95), April 25-28, 1995, Santa Barbara, California, USA, pp. 62-73, 1995, IEEE Computer Society, 0-8186-7091-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
efficient memory simulation, SimICS, instruction level simulator, complex memory hierarchies, user level code, system level code, software caching mechanism, Simulator Translation Cache, STC, interpreted memory operations, complex memory simulation code, lazy storage allocation, well defined internal interface, generic memory simulation, user extensions, threaded code, runtime selection, statistics gathering, memory profiling, data structures, data structures, virtual machines, multiprocessors, storage management, storage allocation |
48 | Kevin T. Lim, Jichuan Chang, Trevor N. Mudge, Parthasarathy Ranganathan, Steven K. Reinhardt, Thomas F. Wenisch |
Disaggregated memory for expansion and sharing in blade servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 267-278, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
disaggregated memory, memory blades, memory capacity expansion, power and cost efficiencies |
48 | Dhiraj D. Kalamkar, Mainak Chaudhuri, Mark A. Heinrich |
Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, pp. 242-253, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
active memory cluster, directory protocol thread, active memory address remapping, parallel reduction, coherence protocol extension, software protocol, multi-threaded node, dual-core node, active memory architecture, distributed shared memory, multiprocessor architecture, memory controller, matrix transpose |
48 | Marc Leeman, David Atienza, Geert Deconinck, Vincenzo De Florio, José M. Mendías, Chantal Ykman-Couvreur, Francky Catthoor, Rudy Lauwereins |
Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 40(3), pp. 383-396, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dynamic data types, multimedia, low power, memory management, memory hierarchy, memory bandwidth, dynamic memory management, system-level exploration, memory footprint |
48 | Wei Zhao, Christos A. Papachristou |
Architectural partitioning of control memory for application specific programmable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 521-526, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
application specific programmable processors, control memory, distributed microcode memory model, microcode memory, repetitive microcodes, distributed memory systems, memory architecture, programmability, microprogram, datapaths, firmware, memory module |
47 | Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatani |
Instruction combining for coalescing memory accesses using global code motion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance ![In: Proceedings of the 2004 workshop on Memory System Performance, Washington, DC, USA, June 8, 2004, pp. 2-11, 2004, ACM, 1-58113-941-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
instruction combining, memory access coalescing, Java, JIT compilers, IA-64, 64-bit architectures |
47 | Ross McIlroy, Peter Dickman, Joe Sventek |
Efficient dynamic heap allocation of scratch-pad memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMM ![In: Proceedings of the 7th International Symposium on Memory Management, ISMM 2008, Tucson, AZ, USA, June 7-8, 2008, pp. 31-40, 2008, ACM, 978-1-60558-134-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
on-core memory, concurrency, memory management |
47 | Betty Prince |
Embedded non-volatile memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 9, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FeRAM, MONOS, PC-RAM, SONOS, floating gate memory, nanocrystal memory, nitride storage memory, trapping site memory, flash memory, embedded memory, non-volatile memory, MRAM |
46 | Xiaogang Qiu, Michel Dubois 0001 |
Tolerating Late Memory Traps in Dynamically Scheduled Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(6), pp. 732-743, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
46 | Lixin Zhang 0002, John B. Carter, Wilson C. Hsieh, Sally A. McKee |
Memory System Support for Image Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 98-107, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
bus utilization, image processing, virtual memory, memory architecture, memory bandwidth, memory latency, cache efficiency |
46 | Peter Grun, Nikil D. Dutt, Alexandru Nicolau |
Aggressive Memory-Aware Compilation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Intelligent Memory Systems ![In: Intelligent Memory Systems, Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers, pp. 147-151, 2000, Springer, 3-540-42328-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
46 | Mary W. Hall, Craig S. Steele |
Memory Management in a PIM-Based Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Intelligent Memory Systems ![In: Intelligent Memory Systems, Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers, pp. 104-121, 2000, Springer, 3-540-42328-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
46 | Yi Feng, Emery D. Berger |
A locality-improving dynamic memory allocator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance ![In: Proceedings of the 2005 workshop on Memory System Performance, Chicago, Illinois, USA, June 12, 2005, pp. 68-77, 2005, ACM, 1-59593-147-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
vam, memory management, virtual memory, paging, fragmentation, allocator, cache locality |
44 | Bülent Abali, Mohammad Banikazemi, Xiaowei Shen, Hubertus Franke, Dan E. Poff, T. Basil Smith |
Hardware Compressed Main Memory: Operating System Support and Performance Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(11), pp. 1219-1233, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Memory compression, memory and cache performance, webserver performance, memory management |
44 | Feng Qin, Shan Lu 0001, Yuanyuan Zhou 0001 |
SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA, pp. 291-302, 2005, IEEE Computer Society, 0-7695-2275-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
44 | Gary S. Tyson, Todd M. Austin |
Improving the Accuracy and Performance of Memory Communication Through Renaming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 218-227, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
data fetching, data value speculation, heap segment, instruction loading, memory access latency, memory communication, memory references, memory renaming, memory segments, processor pipeline, register access techniques, stores, performance, delays, accuracy, instruction-level parallelism, execution time, storage allocation, data dependence speculation, address calculation |
44 | Stephen Lucci, Izidor Gertner, Anil Gupta, Uday Hegde |
Reflective-memory multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 85-94, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
reflective-memory multiprocessor, hardware-supported data replication, multiple computers, memory semantics, reflective memory implementation, Encore Infinity, spinlocks, cache coherency problems, massive replication, recovery procedure, crashed nodes, reliability, fault tolerant computing, shared memory systems, distributed memory systems, system recovery, cache storage, cached architectures, distributed shared memory multiprocessor |
43 | Mark S. Ackerman, Eric Mandel |
Memory in the small: an application to provide task-based organizational memory for a scientific community . ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (4) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 323-332, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
astronomy computing, scientific community, performance support mechanism, memory-in-the-small, astrophysicists, knowledge based systems, memory architecture, organizational memory, task performance, ASSIST |
43 | Easwaran Raman, David I. August |
Recursive data structure profiling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance ![In: Proceedings of the 2005 workshop on Memory System Performance, Chicago, Illinois, USA, June 12, 2005, pp. 5-14, 2005, ACM, 1-59593-147-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
RDS, dynamic shape graph, list linearization, memory profiling, shape profiling |
43 | Leonidas I. Kontothanassis, Michael L. Scott |
Using Memory-Mapped Network Interfaces to Improve the Performance of Distributed Shared Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Second International Symposium on High-Performance Computer Architecture, San Jose, CA, USA, February 3-7, 1996, pp. 166-177, 1996, IEEE Computer Society, 0-8186-7237-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
memory-mapped network interfaces, cache fills, fine-grain access faults, parallel algorithms, protocols, message passing, latency, bandwidth, shared memory systems, distributed shared memory, distributed memory systems, network interfaces, network interfaces, memory-mapped |
43 | Matthew E. Tolentino, Joseph Turner, Kirk W. Cameron |
Memory-miser: a performance-constrained runtime system for power-scalable clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 4th Conference on Computing Frontiers, 2007, Ischia, Italy, May 7-9, 2007, pp. 237-246, 2007, ACM, 978-1-59593-683-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
resource allocation, control, power management, memory |
42 | Jeonghun Cho, Yunheung Paek |
Run-Time Memory Optimization for DDMB Architecture Through a CCB Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC Workshops ![In: Emerging Directions in Embedded and Ubiquitous Computing, EUC 2006 Workshops: NCUS, SecUbiq, USN, TRUST, ESO, and MSA, Seoul, Korea, August 1-4, 2006, Proceedings, pp. 775-784, 2006, Springer, 3-540-36850-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
dual data memory banks, compiler and on-chip memory, DSP, Run-time environment |
42 | Ke Ning, David R. Kaeli |
External memory page remapping for embedded multimedia systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 185-194, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
memory coloring, memory page remapping, embedded systems, memory controllers |
42 | Thomas Stricker, Thomas R. Gross |
Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), San Antonio, Texas, USA, February 1-5, 1997, pp. 168-179, 1997, IEEE Computer Society, 0-8186-7764-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
nonuniform bandwidth, memory system performance characterization, local memory accesses, remote write, cost benefit model, DEC Alpha based parallel systems, DEC-Alpha processor architecture, DEC 8400, scalability, compiler, parallel systems, empirical evaluation, memory architecture, coherency, cache storage, access pattern, spatial locality, local memory, global address space, Cray T3E, Cray T3D, clock speed |
42 | Milan M. Jovanovic, Milo Tomasevic, Veljko M. Milutinovic |
A simulation-based comparison of two reflective memory approaches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 140-152, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
simulation-based comparison, reflective memory approaches, Reflective Memory/Memory Channel, RM/MC system, bus-based system architecture, update consistency mechanism, block transfers, simulation analysis, synthetic workload model, real-time response, run-time actions, compile-time actions, performance evaluation, real-time systems, virtual machines, shared memory systems, distributed memory systems, system buses, message latency, data handling, distributed shared memory systems, shared data |
42 | Kunal Agrawal, Charles E. Leiserson, Jim Sukha |
Memory models for open-nested transactions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance and Correctness ![In: Proceedings of the 2006 workshop on Memory System Performance and Correctness, San Jose, California, USA, October 11, 2006, pp. 70-81, 2006, ACM, 1-59593-578-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Kartik Sudeep, Ahmed Gheith |
Application analysis using memory pressure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance ![In: Proceedings of the 2005 workshop on Memory System Performance, Chicago, Illinois, USA, June 12, 2005, pp. 15-21, 2005, ACM, 1-59593-147-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
42 | Hiroshi Nakamura, Masaaki Kondo, Taisuke Boku |
Software Controlled Reconfigurable On-Chip Memory for High Performance Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Intelligent Memory Systems ![In: Intelligent Memory Systems, Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers, pp. 15-32, 2000, Springer, 3-540-42328-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
41 | Sze Wei Lee, Soon-Chieh Lim |
An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 47(3), pp. 201-221, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
2-D DWT processing systems, memory mapping scheme, memeory access, memory bandwidth |
41 | Chitra Natarajan, Bruce Christenson, Faye A. Briggs |
A study of performance impact of memory controller features in multi-processor server environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WMPI ![In: Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction with the 31st International Symposium on Computer Architecture 2004, Munich, Germany, June 20, 2004, pp. 80-87, 2004, ACM, 1-59593-040-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
memory transaction scheduling, server systems, multi-processors, memory controller, memory subsystem, performance impact |
41 | Robert Cooksey, Dennis Colarelli, Dirk Grunwald |
Content-Based Prefetching: Initial Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Intelligent Memory Systems ![In: Intelligent Memory Systems, Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers, pp. 33-55, 2000, Springer, 3-540-42328-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
41 | Samir Ranjan Das, Richard Fujimoto |
An Empirical Evaluation of Performance-Memory Trade-Offs in Time Warp. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 8(2), pp. 210-224, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
performance evaluation, Discrete event simulation, memory management, checkpointing, Time Warp, rollback, parallel and distributed simulation, virtual time |
41 | Matthew Hertz, Emery D. Berger |
Quantifying the performance of garbage collection vs. explicit memory management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OOPSLA ![In: Proceedings of the 20th Annual ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications, OOPSLA 2005, October 16-20, 2005, San Diego, CA, USA, pp. 313-326, 2005, ACM, 1-59593-031-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
explicit memory management, oracular memory management, performance analysis, throughput, garbage collection, paging, time-space tradeoff |
41 | Mohamed Shalan, Vincent John Mooney III |
Hardware support for real-time embedded multiprocessor system-on-a-chip memory management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, Estes Park, Colorado, USA, May 6-8, 2002, pp. 79-84, 2002, ACM, 1-58113-542-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Atalanta, SoCDMMU, real-time operating systems., two-level memory management, real-time systems, embedded systems, System-on-a-Chip, dynamic memory management |
40 | Gab Joong Jeong, Kyoung Hwan Kwon, Moon Key Lee, Seung Han An |
A Scalable Memory System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 257-260, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
scalable memory system, pipeline technique, systolic data flow, sub-memory blocks, partial binary tree structure, multidirectional data flow, chip size, 4 kbit, 0.8 micron, 5.1 ns, 3.5 mm, throughput, latency, memory architecture, memory architecture, CMOS technology, communication channel, access time, operating speed, clock speed |
40 | Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad H. Hammoud, Rami G. Melhem |
CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, pp. 230-241, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
high-performance search accelerator, high-performance memory substrate, search-intensive application, content addressable random access memory, search operation, memory hierarchy concept, direct hardware implementation, parallel key matching operation, hash function, memory access, application-specific processor, memory structure, hashing technique |
40 | Dae Wook Bang, Yoo Kun Cho |
Distributed shared memory for function-grained graph reduction machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), January 25-27, 1995, San Remo, Italy, pp. 148-155, 1995, IEEE Computer Society, 0-8186-7031-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
function-grained graph reduction machine, efficient DSM system, virtual global memory, function grained graph reduction machine, graph nodes, function applications, global memory access system, distributed graph nodes, H-object, memory coherence problem, weak coherence semantics, read operations, transputer network system, graph theory, resource allocation, parallel machines, parallel machine, distributed shared memory, distributed memory systems, processing elements, virtual storage, transputer systems |
40 | Ian Watson, Alasdair Rawsthorne |
Decoupled pre-fetching for distributed shared memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 252-261, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
partial evaluation (compilers), distributed shared memory environment, decoupled pre-fetching, global view, remote memory copies, user annotations, compile-time analysis, run-time prediction, irregular access patterns, dual processor structure, partial program evaluation, data fetches, parallel architectures, parallel machine, shared memory systems, distributed memory systems, memory architecture |
40 | Lixin Zhang 0002, Venkata K. Pingali, Bharat Chandramouli, John B. Carter |
Memory System Support for Dynamic Cache Line Assembly. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Intelligent Memory Systems ![In: Intelligent Memory Systems, Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers, pp. 56-70, 2000, Springer, 3-540-42328-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
40 | Caroline Benveniste, Peter A. Franaszek, John T. Robinson |
Cache-Memory Interfaces in Compressed Memory Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(11), pp. 1106-1116, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
memory compression, performance analysis, trace-driven simulation, cache design, Memory system design |
40 | Andreas Jürgen Lachenmann, Pedro José Marrón, Matthias Gauger, Daniel Minder, Olga Saukh, Kurt Rothermel |
Removing the memory limitations of sensor networks with flash-based virtual memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroSys ![In: Proceedings of the 2007 EuroSys Conference, Lisbon, Portugal, March 21-23, 2007, pp. 131-144, 2007, ACM, 978-1-59593-636-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
wireless sensor networks, flash memory, virtual memory, memory layout |
39 | Darren J. Kerbyson, Michael Lang 0003, Gene Patino, Hossein Amidi |
An empirical performance analysis of commodity memories in commodity servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance ![In: Proceedings of the 2004 workshop on Memory System Performance, Washington, DC, USA, June 8, 2004, pp. 42-50, 2004, ACM, 1-58113-941-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
performance analysis, performance measurement, memory modules, memory system performance |
39 | Michael C. Huang 0001, Jose Renau, Seung-Moon Yoo, Josep Torrellas |
Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Intelligent Memory Systems ![In: Intelligent Memory Systems, Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers, pp. 152-159, 2000, Springer, 3-540-42328-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
39 | Yoonseo Choi, Hwansoo Han |
Shared heap management for memory-limited java virtual machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 7(2), pp. 13:1-13:32, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
heap sharing, memory protection unit, garbage collection, Dynamic memory management |
39 | Amin Firoozshahian, Alex Solomatnikov, Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz |
A memory system design framework: creating smart memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 406-417, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
memory access protocol, protocol controller, transactional memory, reconfigurable architecture, cache coherence, memory systems, multi-core processors, stream programming |
39 | Jung-Hoon Lee |
Next High Performance and Low Power Flash Memory Package Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 22(4), pp. 515-520, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
NAND-type, NOR-type, memory localities, buffer or cache memory, flash memory |
39 | Huu Hai Nguyen, Martin C. Rinard |
Detecting and eliminating memory leaks using cyclic memory allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMM ![In: Proceedings of the 6th International Symposium on Memory Management, ISMM 2007, Montreal, Quebec, Canada, October 21-22, 2007, pp. 15-30, 2007, ACM, 978-1-59593-893-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
cyclic memory allocation, failure-oblivious computing, memory leaks |
38 | Shoaib Kamil 0001, Parry Husbands, Leonid Oliker, John Shalf, Katherine A. Yelick |
Impact of modern memory subsystems on cache optimizations for stencil computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance ![In: Proceedings of the 2005 workshop on Memory System Performance, Chicago, Illinois, USA, June 12, 2005, pp. 36-43, 2005, ACM, 1-59593-147-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
performance modeling, prefetch, stencil, cache blocking |
38 | Richard C. Murphy, Peter M. Kogge, Arun Rodrigues |
The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Intelligent Memory Systems ![In: Intelligent Memory Systems, Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers, pp. 85-103, 2000, Springer, 3-540-42328-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
38 | Quan T. Tran, Elizabeth D. Mynatt, Gina Calcaterra |
Using Memory Aid to Build Memory Independence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HCI (1) ![In: Human-Computer Interaction. Interaction Design and Usability, 12th International Conference, HCI International 2007, Beijing, China, July 22-27, 2007, Proceedings, Part I, pp. 959-965, 2007, Springer, 978-3-540-73104-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
memory aid, personal autonomy, Home, self-efficacy, cooking |
38 | Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang 0010, Howard David |
DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, pp. 94-104, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
channel bandwidth utilization, DRAM-level prefetching, dynamic random access memory, fully-buffered DIMM, dual in-line memory module, redundant bandwidth, memory block, L2 cache block, DRAM power consumption, SPEC2000 program, software cache prefetching, idle memory latency, power saving, multicore processor, memory controller, interconnect structure, DRAM chip |
38 | Nicholas Freitag McPhee, Riccardo Poli |
Memory with memory: soft assignment in genetic programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2008, Proceedings, Atlanta, GA, USA, July 12-16, 2008, pp. 1235-1242, 2008, ACM, 978-1-60558-130-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
linear GP, memory with memory, soft assignment, genetic programming, symbolic regression |
38 | Junkil Ryu, Chanik Park |
Fast Initialization and Memory Management Techniques for Log-Based Flash Memory File Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, [Third] International Conference, ICESS 2007, Daegu, Korea, May 14-16, 2007, Proceedings, pp. 219-228, 2007, Springer, 978-3-540-72684-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
log-based file system, file system initialization, efficient memory management, flash memory, high performance |
38 | Bernhard Egger 0002, Jaejin Lee, Heonshik Shin |
Scratchpad memory management for portable systems with a memory management unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: Proceedings of the 6th ACM & IEEE International conference on Embedded software, EMSOFT 2006, October 22-25, 2006, Seoul, Korea, pp. 321-330, 2006, ACM, 1-59593-542-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
compilers, virtual memory, paging, scratchpad, code placement, postpass optimization, portable systems, heterogeneous memory |
38 | Xiaogang Qiu, Michel Dubois 0001 |
Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 16(7), pp. 612-623, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dynamic address translation, virtual-address caches, simulations, Multiprocessors, distributed shared memory, virtual memory |
38 | Mark S. Ackerman, Christine Halverson |
Organizational Memory as Objects, Processes, and Trajectories: An Examination of Organizational Memory in Use. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Support. Cooperative Work. ![In: Comput. Support. Cooperative Work. 13(2), pp. 155-189, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
memory reuse, trajectories of information, knowledge management, distributed cognition, organizational memory, contextualization, boundary objects, corporate memory, information reuse, collective memory |
37 | Hongzhong Zheng, Jiang Lin, Zhao Zhang 0010, Zhichun Zhu |
Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 255-266, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
bandwidth decoupling, decoupled DIMM, DRAM memories |
37 | David Elsweiler |
Supporting human memory in personal information management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGIR Forum ![In: SIGIR Forum 42(1), pp. 75-76, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Zuo Wang, Feng Shi 0009, Qi Zuo, Weixing Ji, Mengxiao Liu |
N-port memory mapping for LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 279, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
logical-to-physical mapping, n-port memory, fpga, hierarchy |
37 | Bernhard Egger 0002, Jaejin Lee, Heonshik Shin |
Dynamic scratchpad memory management for code in portable systems with an MMU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 7(2), pp. 11:1-11:38, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
compilers, virtual memory, paging, scratchpad, victim cache, Code placement, postpass optimization, portable systems, heterogeneous memory |
37 | Prabhat Mishra 0001, Mahesh Mamidipaka, Nikil D. Dutt |
Processor-memory coexploration using an architecture description language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 3(1), pp. 140-162, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Processor-memory codesign, memory exploration, design space exploration, architecture description language |
37 | Robert C. Steinke, Gary J. Nutt |
A unified theory of shared memory consistency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 51(5), pp. 800-849, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
memory consistency model lattice, memory consistency models, Distributed shared memory systems |
37 | Andreas Moshovos, Gurindar S. Sohi |
Streamlining Inter-Operation Memory Communication via Data Dependence Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 235-245, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
DEF-store-load-USE chains, address disambiguation, data cache access, data cache bandwidth requirements, data dependence prediction, inter-operation memory communication, memory dependences, memory hierarchy design, transient value cache, storage management, memory architecture, communication latency, instruction window, address calculation |
37 | Anna M. del Corral, José M. Llabería |
Access order to avoid inter-vector-conflicts in complex memory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 404-410, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
access order, inter-vector-conflicts, complex memory systems, vector processor accessing vectors, concurrent memory access, inter-conflicts, performance evaluation, performance, vector processor systems, memory subsystem, memory modules |
37 | Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang |
On Designing of 4-Valued Memory with Double-Gate TFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 187-193, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit |
37 | Jelica Protic, Milo Tomasevic, Veljko M. Milutinovic |
A survey of distributed shared memory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 74-84, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
shared memory programming paradigm, physically distributed memories, classification taxonomy, classification criteria, DSM mechanism, hybrid DSM implementations, distributed systems, parallel programming, shared memory multiprocessors, shared memory systems, distributed memory systems, distributed shared memory systems, DSM systems |
37 | Dan Grossman, Jeremy Manson, William W. Pugh |
What do high-level memory models mean for transactions? ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance and Correctness ![In: Proceedings of the 2006 workshop on Memory System Performance and Correctness, San Jose, California, USA, October 11, 2006, pp. 62-69, 2006, ACM, 1-59593-578-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Vera A. Kazakova, Jena D. Hwang, Bonnie J. Dorr, Yorick Wilks, J. Blake Gage, Alex Memory, Mark A. Clark |
SPLAIN: Augmenting Cybersecurity Warnings with Reasons and Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2311.11215, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
36 | Donald Flywell Malanga, Memory Banda |
ICT Use and Livelihoods of Women Microenterprises in Malawi. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2108.09807, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
36 | Faridah, Sunarno, Sentagi Sesotya Utami, Emilya Nurjani, Muhammad Ilham Hanif, Memory Motivanisman Waruwu, Rony Wijaya |
Optimisation of the data point configurations in a building environmental monitoring system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Commun. Networks Distributed Syst. ![In: Int. J. Commun. Networks Distributed Syst. 27(3), pp. 259-281, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
36 | Mack Blackburn, Ning Yu, Alex Memory, W. Graham Mueller |
Detecting and Annotating Narratives in Social Media: A Vision Paper. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICWSM Workshops ![In: Workshop Proceedings of the 14th International AAAI Conference on Web and Social Media, ICWSM 2020 Workshops, Atlanta, Georgia, USA [virtual], June 8, 2020, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
36 | Angelika Kimmig, Alex Memory, Renée J. Miller, Lise Getoor |
A Collective, Probabilistic Approach to Schema Mapping Using Diverse Noisy Evidence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Knowl. Data Eng. ![In: IEEE Trans. Knowl. Data Eng. 31(8), pp. 1426-1439, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
36 | Memory Rukasha, Felix Olu Bankole |
Impact of e-Commerce on Corporate Governance and Ethics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONF-IRM ![In: 2019 International Conference on Information Resources Management - ICT Research for the New Connected World, CONF-IRM 2019, Auckland, New Zealand, May 27-29, 2019, pp. 40, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
36 | W. Graham Mueller, Alex Memory, Kyle Bartrem |
Causal Discovery of Cyber Attack Phases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMLA ![In: 18th IEEE International Conference On Machine Learning And Applications, ICMLA 2019, Boca Raton, FL, USA, December 16-19, 2019, pp. 1348-1352, 2019, IEEE, 978-1-7281-4550-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
36 | Memory Tauringana |
An investigation into the adoption of e-commerce among older people. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2019 |
RDF |
|
36 | Alex Memory |
Collective Relational Data Integration with Diverse and Noisy Evidence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2019 |
RDF |
|
36 | Laura Smith, Rebecca O'Rourke, Memory Van Beek, Suzanne Bickerdike, Rania Alkhadragy |
Local and Global Dimensions of a Clinical Skills E-book Development Project. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EC-TEL (Practitioner Proceedings) ![In: EC-TEL Practitioner Proceedings 2018: 13th European Conference On Technology Enhanced Learning, Leeds, UK, September 3-6, 2018., 2018, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
36 | Angelika Kimmig, Alex Memory, Renée J. Miller, Lise Getoor |
A Collective, Probabilistic Approach to Schema Mapping: Appendix. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1702.03447, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
36 | Angelika Kimmig, Alex Memory, Renée J. Miller, Lise Getoor |
A Collective, Probabilistic Approach to Schema Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDE ![In: 33rd IEEE International Conference on Data Engineering, ICDE 2017, San Diego, CA, USA, April 19-22, 2017, pp. 921-932, 2017, IEEE Computer Society, 978-1-5090-6543-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
36 | Memory Machiridza |
Misalignment challenges when integrating security requirements into mobile banking application development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONF-IRM ![In: CONF-IRM 2016, The International Conference on Information Resources Management: Digital Emancipation in a Networked Society, Cape Town, South Africa, May 18-20, 2016, pp. 33, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
36 | Henry G. Goldberg, William T. Young, Alex Memory, Ted E. Senator |
Explaining and Aggregating Anomalies to Detect Insider Threats. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 49th Hawaii International Conference on System Sciences, HICSS 2016, Koloa, HI, USA, January 5-8, 2016, pp. 2739-2748, 2016, IEEE Computer Society, 978-0-7695-5670-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
36 | William T. Young, Alex Memory, Henry G. Goldberg, Ted E. Senator |
Detecting Unknown Insider Threat Scenarios. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Security and Privacy Workshops ![In: 35. IEEE Security and Privacy Workshops, SPW 2014, San Jose, CA, USA, May 17-18, 2014, pp. 277-288, 2014, IEEE Computer Society, 978-1-4799-5103-1. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
36 | Ted E. Senator, Henry G. Goldberg, Alex Memory, William T. Young, Brad Rees, Robert Pierce, Daniel Huang 0003, Matthew Reardon, David A. Bader, Edmond Chow, Irfan A. Essa, Joshua Jones, Vinay Bettadapura, Duen Horng Chau, Oded Green, Oguz Kaya, Anita Zakrzewska, Erica Briscoe, Rudolph L. Mappus IV, Robert McColl, Lora Weiss, Thomas G. Dietterich, Alan Fern, Weng-Keen Wong, Shubhomoy Das, Andrew Emmott, Jed Irvine, Jay Yoon Lee, Danai Koutra, Christos Faloutsos, Daniel D. Corkill, Lisa Friedland, Amanda Gentzel, David D. Jensen |
Detecting insider threats in a real corporate database of computer usage activity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KDD ![In: The 19th ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, KDD 2013, Chicago, IL, USA, August 11-14, 2013, pp. 1393-1401, 2013, ACM, 978-1-4503-2174-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
36 | William T. Young, Henry G. Goldberg, Alex Memory, James F. Sartain, Ted E. Senator |
Use of Domain Knowledge to Detect Insider Threats in Computer Activities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Security and Privacy Workshops ![In: 2013 IEEE Symposium on Security and Privacy Workshops, San Francisco, CA, USA, May 23-24, 2013, pp. 60-67, 2013, IEEE Computer Society, 978-1-4799-0458-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
36 | Alex Memory, Angelika Kimmig, Stephen H. Bach, Louiqa Raschid, Lise Getoor |
Graph Summarization in Annotated Data Using Probabilistic Soft Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
URSW ![In: Proceedings of the 8th International Workshop on Uncertainty Reasoning for the Semantic Web, Boston, USA, November 11, 2012, pp. 75-86, 2012, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
36 | Sally A. McKee, William A. Wulf, James H. Aylor, Robert H. Klenke, Maximo H. Salinas, Sung I. Hong, Dee A. B. Weikle |
Dynamic Access Ordering for Streamed Computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(11), pp. 1255-1271, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Memory systems architecture, memory access ordering, memory access scheduling, memory bandwidth, memory latency |
36 | V. Kim, T. Chen |
Assessing SRAM test coverage for sub-micron CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 24-30, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
submicron CMOS technologies, SRAM test coverage assessment, memory fault probability model, memory array, data retention faults, memory fault coverages, memory test algorithms, functional fault class coverages, 0.5 to 1 mum, stuck-at faults, transition faults, stuck-open faults, coupling faults, physical defects, CMOS memory circuits |
36 | Gyungho Lee |
An assessment of COMA multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 388-392, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Cache Only Memory Architecture, Perfect Club Benchmark Suite, coherence policy, performance evaluation, performance, discrete event simulation, memory hierarchy, shared memory systems, distributed memory systems, update, trace driven simulations, cache storage, network traffic, miss ratio, distributed shared memory multiprocessors, shared address space, invalidate |
36 | Hung-Wei Tseng 0001, Han-Lin Li, Chia-Lin Yang |
An energy-efficient virtual memory system with flash memory as the secondary storage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 418-423, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
embedded storages, embedded systems, virtual memory, NAND flash memory, page replacement |
36 | Wolfgang K. Giloi, C. Hastedt, Friedrich Schön, Wolfgang Schröder-Preikschat |
A Distributed Implementation of Shared Virtual Memory with Strong and Weak Coherence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDMCC ![In: Distributed Memory Computing, 2nd European Conference, EDMCC2, Munich, FRG, April 22-24, 1991, Proceedings, pp. 23-31, 1991, Springer, 3-540-53951-4. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
virtual shared memory architecture, strong and weak data coherence, communication hardware, parallelizing compilers, Distributed memory architecture |
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