Search results for "Signed-digit"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
148	Soonhak Kwon	Signed Digit Representation with NAF and Balanced Ternary Form and Efficient Exponentiation in GF(qn) Using a Gaussian Normal Basis of Type II.	WISA	2004	DBLP DOI BibTeX RDF	NAF (nonadjacent form), balanced ternary number system, finite field, exponentiation, optimal normal basis, Gaussian normal basis, signed digit representation
147	Sorin Cotofana, Stamatis Vassiliadis	Signed Digit Addition and Related Operations with Threshold Logic.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	signed-digit arithmetic, redundant adders, redundant multipliers, neural networks, Computer arithmetic, threshold logic, carry-free addition, signed-digit number representation
145	Behrooz Parhami	Carry-Free Addition of Recorded Binary Signed-Digit Numbers.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	string recoding, recoded binary signed-digit numbers, number representation systems, borrow chains, propagation-free addition, signed-digit arithmetic, limited-carry propagation, binary signed-digit numbers, borrow-free subtraction, digital arithmetic, subtraction, annihilation, Carry-free addition, carry-free addition, signed digit number representation
118	Anders Lindström, Michael Nordseth, Lars Bengtsson, Amos Omondi	Arithmetic Circuits Combining Residue and Signed-Digit Representations.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
118	Mark A. Erle, Eric M. Schwarz, Michael J. Schulte	Decimal Multiplication with Efficient Partial Product Generation.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
117	Fanyu Kong, Jia Yu 0003, Zhun Cai, Daxing Li	New Left-to-Right Radix- r Signed-Digit Recoding Algorithm for Pairing-Based Cryptosystems.	TAMC	2007	DBLP DOI BibTeX RDF	Elliptic curve cryptosystems, pairing-based cryptosystems, point multiplication, signed-digit number representations
115	Fanyu Kong, Daxing Li	A Note on Signed Binary Window Algorithm for Elliptic Curve Cryptosystems.	CANS	2005	DBLP DOI BibTeX RDF	signed window algorithm, elliptic curve cryptosystems, point multiplication, signed-digit number representations
110	M. C. Mekhallalati, M. K. Ibrahim	New high radix maximally-redundant signed digit adder.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
102	Jeff Rebacz, Erdal Oruklu, Jafar Saniie	High performance signed-digit decimal adders.	EIT	2009	DBLP DOI BibTeX RDF
94	Jeng-Jong J. Lue, Dhananjay S. Phatak	Area x Delay (A T) Efficient Multiplier Based on an Intermediate Hybrid Signed-Digit (HSD-1) Representation.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
93	Tie Hou	Coinductive Proofs for Basic Real Computation.	CiE	2006	DBLP DOI BibTeX RDF	Real computation, Coinductive proof, Signed digit streams, Minlog, Computability
93	Sung-Ming Yen, Chien-Ning Chen, Sang-Jae Moon, JaeCheol Ha	Improvement on Ha-Moon Randomized Exponentiation Algorithm.	ICISC	2004	DBLP DOI BibTeX RDF	Randomized recoding, Signed-digit recoding, Side-channel attack, Differential power analysis (DPA), Simple power analysis (SPA), Modular exponentiation, Physical cryptanalysis
86	Shugang Wei, Kensuke Shimizu	Error Detection of Arithmetic Circuits Using a Residue Checker with Signed-Digit Number System.	DFT	2001	DBLP DOI BibTeX RDF	residue addition, residue multiplication, signed-digit(SD) number representation, SD adder, error detection, residue number system(RNS)
79	Y. Ibrahim, Graham A. Jullien, William C. Miller	Ultra Low Noise Signed Digit Arithmetic using Cellular Neural Networks.	IWSOC	2004	DBLP DOI BibTeX RDF
78	Kavallur Gopi Smitha, Hossam A. H. Fahmy, A. Prasad Vinod 0001	Redundant Adders Consume Less Energy.	APCCAS	2006	DBLP DOI BibTeX RDF
70	Andreas Persson, Lars Bengtsson	Forward and Reverse Converters and Moduli Set Selection in Signed-Digit Residue Number Systems.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Signed-digit, Moduli-selection, Residue number system, FIR filters, Converters
70	Thambipillai Srikanthan, Siew Kei Lam, Mishra Suman	Area-Time Efficient Sign Detection Technique for Binary Signed-Digit Number System.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	binary signed-digit number system, most significant carry detection, Sign detection
70	Marc Joye, Sung-Ming Yen	Optimal Left-to-Right Binary Signed-Digit Recoding.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	SD2 left-to-right recoding, canonical/minimum-weight/nonadjacent form, cryptography, smart-cards, Computer arithmetic, elliptic curves, exponentiation, converter, redundant number representation, signed-digit representation
70	Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder	Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices.	ISMVL	2000	DBLP DOI BibTeX RDF	signed-digit adder, negative differential-resistance devices, NDR devices, multiple-valued logic, resonant-tunneling diodes, redundant number systems, RTDs
69	Nevine Maurice Ebeid, M. Anwar Hasan	On Randomizing Private Keys to Counteract DPA Attacks.	Selected Areas in Cryptography	2003	DBLP DOI BibTeX RDF	binary signed-digit representation, smart cards, Differential power analysis, elliptic curve cryptosystems, scalar multiplication
64	Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano	A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities.	IOLTS	2004	DBLP DOI BibTeX RDF
63	Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi	A radix-10 SRT divider based on alternative BCD codings.	ICCD	2007	DBLP DOI BibTeX RDF
63	Hosahalli R. Srinivas, Keshab K. Parhi	A Radix 2 Shared Division/Square Root Algorithm and its VLSI Architecture.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
61	Wu-Chuan Yang, Dah-Jyh Guan, Chi-Sung Laih	Fast Multi-computations with Integer Similarity Strategy.	Public Key Cryptography	2005	DBLP DOI BibTeX RDF	ElGamal-like public key cryptosystems, binary signed-digit (BSD) representations, sparse forms, multi-computations, multiexponentiations, multi-scalar multiplications
61	Jen-Shiun Chiang, Min-Shiou Tsai	A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	floating-point division, new Svoboda-Tung division, radix-4, Svoboda-Tung division, computer arithmetic, prescaling, signed digit number system
61	W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi	A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging.	VLSI Design	1995	DBLP DOI BibTeX RDF	CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
56	John Moskal, Erdal Oruklu, Jafar Saniie	Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder.	ISCAS	2007	DBLP DOI BibTeX RDF
56	Brian King	wNAF*, an Efficient Left-to-Right Signed Digit Recoding Algorithm.	ACNS	2008	DBLP DOI BibTeX RDF
56	Nevine Maurice Ebeid, M. Anwar Hasan	On binary signed digit representations of integers.	Des. Codes Cryptogr.	2007	DBLP DOI BibTeX RDF	AMS Classification 11A63
56	Shuangching Chen, Shugang Wei	Weighted-to-residue and residue-to-weighted converters with three-moduli (2n-1, 2n, 2n+1) signed-digit architectures.	ISCAS	2006	DBLP DOI BibTeX RDF
56	Bodo Möller	Fractional Windows Revisited: Improved Signed-Digit Representations for Efficient Exponentiation.	ICISC	2004	DBLP DOI BibTeX RDF	elliptic curve cryptography, Efficient implementations
56	Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano	Error Detection in Signed Digit Arithmetic Circuit with Parity Checker.	DFT	2003	DBLP DOI BibTeX RDF
56	In-Cheol Park, Hyeong-Ju Kang	Digital filter synthesis based on an algorithm to generate all minimal signed digit representations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
56	Siew Kei Lam, Thambipillai Srikanthan, Nitin Goyal, Neeraj Tyagi	Incorporating area-time flexibility to a binary signed-digit adder.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
56	Alejandro F. González, Pinaki Mazumder	Compact Signed-Digit Adder Using Multiple-Valued Logic.	ARVLSI	1997	DBLP DOI BibTeX RDF
55	Alejandro F. González, Pinaki Mazumder	Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	Signed-digit arithmetic, quantum electronic resonant-tunneling circuits, multiple-valued logic
55	F. Pourbigharaz, H. M. Yassine	A Signed-Digit Architecture for Residue to Binary Transformation.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF	VLSI arithmetic algorithms, residue to binary conversion, digital signal processing, Chinese remainder theorem, residue number systems, signed-digit number systems
55	Behrooz Parhami	On the Implementation of Arithmetic Support Functions for Generalized Signed-Digit Number Systems.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	zero detection, arithmetic support functions, generalized signed-digit number systems, OSD number representation, borrow-free subtraction, overflow handling, digital arithmetic, redundant number representations, carry-free addition, sign detection
55	Steven Arno, Ferrell S. Wheeler	Signed Digit Representations of Minimal Hamming Weight.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	minimal Hamming weight, combinatorial techniques, uniform probability space, k-digit integers, online algorithm, digital arithmetic, probability distributions, random variable, Markov chain analysis, signed digit representations
55	Behrooz Parhami	Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	generalised signed-digit number systems, carry, borrow, fast propagation-free addition, digital arithmetic, subtraction, unifying framework, redundant number representations
55	Tony M. Carter, James E. Robertson	Radix-16 Signed-Digit Division.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	radix-16 signed-digit division, digital arithmetic, normalization, design tradeoff, two-stage algorithm
54	Raymond K. W. Chan, Moon-Chuen Lee	Multiplierless Approximation of Fast DCT Algorithms.	ICME	2006	DBLP DOI BibTeX RDF
49	Madhu S. Chakraborty, Sandip K. Sao, Abhoy Chand Mondal	Equivalence of reverse conversion of binary signed-digit number system and two's-complement to canonical signed-digit recording.	RAIT	2018	DBLP DOI BibTeX RDF
49	Yuuki Tanaka	Efficient signed-digit-to-canonical-signed-digit recoding circuits.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
48	Fekri Kharbash, Ghulam M. Chaudhry	Reliable Binary Signed Digit Number Adder Design.	ISVLSI	2007	DBLP DOI BibTeX RDF
48	Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano	Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Fault tolerance, error checking, high-speed arithmetic
48	Shugang Wei	Number conversions between RNS and mixed-radix number system based on Modulo (2p - 1) signed-digit arithmetic.	SBCCI	2005	DBLP DOI BibTeX RDF
48	Shugang Wei, Kensuke Shimizu	Modulo (2p ± 1) multipliers using a three-operand modular addition and Booth recoding based on signed-digit number arithmetic.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
48	Shugang Wei, Shuangching Chen, Kensuke Shimizu	Fast modular multiplication using Booth recoding based on signed-digit number arithmetic.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
47	Sridhar Rajagopal, Joseph R. Cavallaro	On-line Arithmetic for Detection in Digital Communication Receivers.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
47	Hooman Nikmehr, Cheng-Chew Lim	A New On-the-fly Summation Algorithm.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
47	Luke O'Connor	An Analysis of Exponentiation Based on Formal Languages.	EUROCRYPT	1999	DBLP DOI BibTeX RDF
46	Ulrich Berger 0001, Tie Hou	Coinduction for Exact Real Number Computation.	Theory Comput. Syst.	2008	DBLP DOI BibTeX RDF	Exact real number computation, Corecursion, Signed digit streams, Coinduction
46	Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu	Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices.	ISMVL	2008	DBLP DOI BibTeX RDF	differential-pair circuit, radix-2 signed-digit adder, reliability
46	Wu-Chuan Yang, Dah-Jyh Guan, Chi-Sung Laih	Fast Multicomputation with Asynchronous Strategy.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	multi-exponentiations, multiscalar-multiplications, binary signed-digit codes, joint sparse forms, multicomputations, Public key cryptosystems
46	Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama	Fully Source-Coupled Logic Based Multiple-Valued VLSI.	ISMVL	2002	DBLP DOI BibTeX RDF	source-coupled logic, differential-pair circuit, current-source control, radix-2 signed-digit adder, multiple-valued logic, current-mode logic
46	Kiamal Z. Pekmestzi, Paraskevas Kalivas	Constant Number Serial Pipeline Multipliers.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF	constant number multiplication, serial multipliers, systolic circuits, canonic signed digit representation
46	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels.	ISMVL	2000	DBLP DOI BibTeX RDF	dual-rail multiple-valued current-mode logic circuit, two supply voltages, differential-pair circuit, radix-2 signed-digit adder
40	Chia-Long Wu	Fast Parallel Montgomery Binary Exponentiation Algorithm Using Canonical- Signed-Digit Recoding Technique.	ICA3PP	2009	DBLP DOI BibTeX RDF	Montgomery reduction algorithm, cryptography, complexity analysis, number theory, algorithm design
40	Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano	Fault tolerant design of signed digit based FIR filters.	ISCAS	2006	DBLP DOI BibTeX RDF
40	Erik Backenius, Erik Säll, Oscar Gustafsson	Bidirectional conversion to minimum signed-digit representation.	ISCAS	2006	DBLP DOI BibTeX RDF
40	Andreas Persson, Lars Bengtsson	Reverse conversion architectures for signed-digit residue number systems.	ISCAS	2006	DBLP DOI BibTeX RDF
40	Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano	Localization of Faults in Radix-n Signed Digit Adders.	IOLTS	2006	DBLP DOI BibTeX RDF
40	Yi Wang 0016, Douglas L. Maskell, Jussipekka Leiwo, Thambipillai Srikanthan	Unified Signed-Digit Number Adder for RSA and ECC Public-key Cryptosystems.	APCCAS	2006	DBLP DOI BibTeX RDF
40	Andreas Lindahl, Lars Bengtsson	A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation.	DSD	2005	DBLP DOI BibTeX RDF
40	Hideki Fukuda	Signed-digit CMOS (SD-CMOS) Logic Circuits with Dynamic Operation.	ISMVL	2005	DBLP DOI BibTeX RDF
40	Hideki Fukuda	Signed Digit CMOS (SD-CMOS) Logic Circuits with Static Operation.	ISMVL	2004	DBLP DOI BibTeX RDF
40	Andrew G. Dempster, Malcolm D. Macleod	Using all signed-digit representations to design single integer multipliers using subexpression elimination.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
40	Chichyang Chen, Rui-Lin Chen	Performance-Improved Computation of Very Large Word-Length LNS Addition/Subtraction Using Signed-Digit Arithmetic.	ASAP	2003	DBLP DOI BibTeX RDF
40	Chichyang Chen, Liang-An Chen, Jih-Ren Cheng	Architectural Design of a Fast Floating-Point Multiplication-Add Fused Unit Using Signed-Digit Addition.	DSD	2001	DBLP DOI BibTeX RDF
40	Arthur T. G. Fuller, Behrouz Nowrouzian	A novel technique for optimization over the canonical signed-digit number space using genetic algorithms.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
40	Shugang Wei, Kensuke Shimizu	Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
39	Peter Kornerup, Jean-Michel Muller	Leading Guard Digits in Finite Precision Redundant Representations.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	leading guard digits, multioperand additions, pseudo overflows, Redundant representations
39	Valentina P. Markova	Design of High-speed Parallel Arithmetic Algorithms and Architectures.	DIS-RT	1997	DBLP DOI BibTeX RDF
39	Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin	Digit pipelined arithmetic on fine-grain array processors.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
39	Hosahalli R. Srinivas, Keshab K. Parhi	A floating point radix 2 shared division/square root chip.	ICCD	1995	DBLP DOI BibTeX RDF	floating point radix 2 shared division/square root chip, full-custom 1.2 micron CMOS VLSI chip, single precision IEEE 754 std. floating point numbers, square root algorithm, digit-by-digit schemes, quotient/root digit selection, 5.0 V, 66 MHz, VLSI, floating point arithmetic, CMOS integrated circuits, IEEE standards, dividing circuits, 1.2 micron, division algorithm
36	William G. Natter, Behrouz Nowrouzian	A novel algorithm for signed-digit online multiply-accumulate operation and its purely signed-binary hardware implementation.	ISCAS	2000	DBLP DOI BibTeX RDF
31	Chia-Long Wu, Der-Chyuan Lou, Te-Jen Chang	An efficient Montgomery exponentiation algorithm for public-key cryptosystems.	ISI	2008	DBLP DOI BibTeX RDF
31	Vassilliy Tchoumatchenko, Tania Vassileva, P. Gurov	An FPGA-Based Square-Root Co-Processor.	EUROMICRO	1996	DBLP DOI BibTeX RDF
31	Robert Prain, Andrew P. Paplinski	A Distributed Arithmetic Online Rotator for Signal Processing Applications.	DSD	2004	DBLP DOI BibTeX RDF
31	Dhananjay S. Phatak, Israel Koren	Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
30	Ghassem Jaberipur, Behrooz Parhami, Saeid Gorgin 0001	Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	Adder/subtractor, redundant format, computer arithmetic, floating point, rounding, signed-digit number system
30		A Research and Design of Decimal Floating Multiplier Based on FPGA.	WKDD	2010	DBLP DOI BibTeX RDF	Decimal floating multiplier, DPD codec, BCD new codec, Signed-Digit radix-5, Decimal 32:2 CSA
30	Peter J. Grabner, Clemens Heuberger	On the Number of Optimal Base 2 Representations of Integers.	Des. Codes Cryptogr.	2006	DBLP DOI BibTeX RDF	Signed digit expansions, Minimal Hamming weight, Elliptic curve cryptography
30	Ghassem Jaberipur, Behrooz Parhami, Mohammad Ghodsi	An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	(4,2)-compressor, digit set, signed digit, computer arithmetic, redundant number system, carry-free addition
30	Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro 0001	Exploiting general coefficient representation for the optimal sharing of partial products in MCMs.	SBCCI	2006	DBLP DOI BibTeX RDF	common subexpression elimination (CSE), digital filter design, minimal signed digit (MSD), multiple constant multiplication (MCM)
30	Mary D. Brown, Yale N. Patt	Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files.	HPCA	2002	DBLP DOI BibTeX RDF	redundant binary, limited bypass, pipelined register file, signed digit
30	Naofumi Takagi	Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms.	ISMVL	2002	DBLP DOI BibTeX RDF	carry-save form, carry-propagation-free addition, multiplier recoding, computer arithmetic, signed-digit number representation, digit-recurrence algorithm
30	Kavish Seth, S. Srinivasan 0001	VLSI Implementation of 2-D DWT/IDWT Cores Using 9/7-Tap Filter Banks Based on the Non-Expansive Symmetric Extension Scheme.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	2D-DWT/IDWT Hardware, Non-expansive symmetric Extension, Canonic Signed Digit Arithmetic, Sub-expression Sharing, Low Power
30	Dhananjay S. Phatak, Tom Goff, Israel Koren	Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	constant-time addition, simultaneous format conversion, redundant adders, signed-digit addition, 4:2 compressor, Redundant representations, carry-save addition
30	Dietmar Fey, Marko Degenkolb	Digit Pipelined Arithmetic for 3-D Massively Parallel Optoelectronic Circuits.	J. Supercomput.	2000	DBLP DOI BibTeX RDF	optoelectronic VLSI, signed-digit arithmetic, pipeline processing, optical interconnects, superscalar architectures
30	Takafumi Aoki, Kimihiko Nakazawa, Tatsuo Higuchi 0001	High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables.	ISMVL	2000	DBLP DOI BibTeX RDF	Quotient digit selection tables, High-radix division, VLSI, Computer arithmetic, Signed-digit number systems, SRT division
30	Dhananjay S. Phatak	Comments on Duprat and Muller's Branching CORDIC Paper.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	Branching CORDIC, constant scale factor, errata, corrections, signed-digit representation
30	Jean Duprat, Yvan Herreros, Sylvanus Kla	New Redundant Representations of Complex Numbers and Vectors.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	n-dimensional vectors, digital arithmetic, multiplication, redundant representation, complex numbers, carry-free addition, signed-digit number systems, polygonal representation
30	Jean Duprat, Jean-Michel Muller	The CORDIC Algorithm: New Results for Fast VLSI Implementation.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	sign functions, fast VLSI implementation, signed-digit implementation, carry-save representation, branching CORDIC method, constant normalization factor, online delay, cosine functions, VLSI, signal processing, digital arithmetic, CORDIC algorithm
30	Milos D. Ercegovac, Tomás Lang	On-the-Fly Rounding.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	digit rounding, digit-serial form, most significant digit, least significant, redundant addition, result-digit, signed-digit set, computing arithmetic, digital arithmetic, number theory, digit-recurrence algorithms, online arithmetic
30	Milos D. Ercegovac, Tomás Lang	Fast Multiplication Without Carry-Propagate Addition.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	fast multiplication, carry-propagate adder, LRCF scheme, general radix r, radix-4 signed-digit implementation, digital arithmetic
30	Homayoon Sam, Arupratan Gupta	A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	fixed coefficient multiplication, controlled coefficient multiplication, multibit recoding algorithm, signed two's complement binary numbers, radix 2/sup k/, very high speed adders, hardware parallel multipliers, 5-bit recoding, performance, computer arithmetic, digital arithmetic, multiplying circuits, signed-digit representation
30	Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima	High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	binary integer multiplication, carry-propagation-free adder, high-speed multiplier, redundant binary representation, VLSI, Arithmetic operations, hardware algorithm, signed-digit number representation
30	Douglas Stott Parker Jr., Cauligi S. Raghavendra	The Gamma Network.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	Fault-tolerance, reliability, interconnection network, multiprocessors, permutation, signed-digit number system