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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 5 occurrences of 5 keywords
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Results
Found 28 publication records. Showing 28 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
20 | Joseph F. Ryan 0002, Benton H. Calhoun |
Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 127-132, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Sub-threshold Circuits, Sub-Vt, Sense-Amplifiers, Variation, Offset |
15 | Jian Deng, Jean-Luc Nagel, Loïc Zahnd, Marc Pons 0001, David Ruffieux, Claude Arm, Pascal Persechini, Stéphane Emery |
Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019, Lausanne, Switzerland, July 29-31, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-2954-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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13 | Steven C. Jocke, Jonathan F. Bolus, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun |
A 2.6 µW sub-threshold mixed-signal ECG SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 117-118, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
sub-threshold SoC, sub-threshold operation, system on chip, electrocardiogram |
10 | Amit Agarwal 0001, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy 0001 |
A process-tolerant cache architecture for improved yield in nanoscale technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(1), pp. 27-38, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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8 | David Zooker, Yoav Weizman, Alexander Fish, Osnat Keren |
Silicon Proven 1.29 μm × 1.8 μm 65nm Sub-Vt Optical Sensor for Hardware Security Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 136269-136278, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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8 | David Zooker Zabib, Alexander Fish, Osnat Keren, Yoav Weizman |
Compact Sub-Vt Optical Sensor for the Detection of Fault Injection in Hardware Security Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NTMS ![In: 10th IFIP International Conference on New Technologies, Mobility and Security, NTMS 2019, Canary Islands, Spain, June 24-26, 2019, pp. 1-5, 2019, IEEE, 978-1-7281-1542-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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8 | Jiangyi Li, Pavan Kumar Chundi, Sung Kim, Zhewei Jiang, Minhao Yang, Joonseong Kang, Seungchul Jung, Sang Joon Kim, Mingoo Seok |
A 0.78-µW 96-Ch. Deep Sub-Vt Neural Spike Processor Integrated with a Nanowatt Power Management Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018, Dresden, Germany, September 3-6, 2018, pp. 154-157, 2018, IEEE, 978-1-5386-5404-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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8 | Wei Jin 0004, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok |
Near- and Sub-Vt Pipelines Based on Wide-Pulsed-Latch Design Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 52(9), pp. 2475-2487, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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8 | Oskar Andersson, Babak Mohammadi, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues |
A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC 2014 - 40th European Solid State Circuits Conference, Venice Lido, Italy, September 22-26, 2014, pp. 243-246, 2014, IEEE, 978-1-4799-5694-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
8 | Yongtae Kim, Peng Li 0001 |
A 0.38 V near/sub-VT digitally controlled low-dropout regulator with enhanced power supply noise rejection in 90 nm CMOS process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 7(1), 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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8 | S. M. Yasser Sherazi, Joachim Neves Rodrigues, Omer Can Akgun, Henrik Sjöland, Peter Nilsson 0001 |
Ultra low energy design exploration of digital decimation filters in 65 nm dual-VT CMOS in the sub-VT domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 37(4-5), pp. 494-504, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
8 | Christoph Thomas Muller, Steffen Malkowsky, Oskar Andersson, Babak Mohammadi, Jens Sparsø, Joachim Neves Rodrigues |
A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013, pp. 380-385, 2013, IEEE, 978-1-4799-0522-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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8 | Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues |
Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference, Bucharest, Romania, September 16-20, 2013, pp. 197-200, 2013, IEEE, 978-1-4799-0643-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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8 | Ibrahim Kazi, Pascal Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Andreas Burg, Giovanni De Micheli |
A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013, Paris, France, June 16-19, 2013, pp. 1-4, 2013, IEEE, 978-1-4799-0618-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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8 | Chris Winstead, Joachim Neves Rodrigues |
Ultra-Low-Power Error Correction Circuits: Technology Scaling and Sub-VT Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 59-II(12), pp. 913-917, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
8 | Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg |
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC (Selected Papers) ![In: VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers, pp. 88-106, 2012, Springer, 978-3-642-45072-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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8 | S. M. Yasser Sherazi, Peter Nilsson 0001, Henrik Sjöland, Joachim Neves Rodrigues |
A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012, pp. 448-451, 2012, IEEE, 978-1-4673-1261-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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8 | Pascal Andreas Meinerzhagen, Oskar Andersson, Babak Mohammadi, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues |
A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: Proceedings of the 38th European Solid-State Circuit conference, ESSCIRC 2012, Bordeaux, France, September 17-21, 2012, pp. 321-324, 2012, IEEE, 978-1-4673-2212-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
8 | Pascal Andreas Meinerzhagen, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues |
Benchmarking of Standard-Cell Based Memories in the Sub- VT Domain in 65-nm CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Emerg. Sel. Topics Circuits Syst. ![In: IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2), pp. 173-182, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
8 | Oskar Andersson, S. M. Yasser Sherazi, Joachim Neves Rodrigues |
Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCHIP ![In: 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, pp. 1-4, 2011, IEEE, 978-1-4577-0514-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
8 | Pascal Andreas Meinerzhagen, Oskar Andersson, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues |
Synthesis strategies for sub-VT systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: 20th European Conference on Circuit Theory and Design, ECCTD 2011, Linkoping, Sweden, Aug. 29-31, 2011, pp. 552-555, 2011, IEEE, 978-1-4577-0617-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
8 | S. M. Yasser Sherazi, Peter Nilsson 0001, Omer Can Akgun, Henrik Sjöland, Joachim Neves Rodrigues |
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil, pp. 837-840, 2011, IEEE, 978-1-4244-9473-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
8 | Joachim Neves Rodrigues, Omer Can Akgun, Viktor Öwall |
A < 1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 18th IEEE/IFIP VLSI-SoC 2010, IEEE/IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Madrid, Spain, 27-29 September 2010, pp. 253-258, 2010, IEEE. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
8 | Joyce Kwong, Yogesh K. Ramadass, Naveen Verma, Anantha P. Chandrakasan |
A 65 nm Sub-Vt Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 44(1), pp. 115-126, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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8 | Joachim Neves Rodrigues, Omer Can Akgun, Puneet Acharya, Adolfo de la Calle, Yusuf Leblebici, Viktor Öwall |
Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-Vt Domain By Architectural Folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers, pp. 347-356, 2009, Springer, 978-3-642-11801-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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8 | Joyce Kwong, Yogesh K. Ramadass, Naveen Verma, Markus Koesler, Korbinian Huber, Hans Moormann, Anantha P. Chandrakasan |
A 65nm Sub-Vt Microcontroller with Integrated SRAM and Switched-Capacitor DC-DC Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008, pp. 318-319, 2008, IEEE, 978-1-4244-2010-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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8 | Naveen Verma, Anantha P. Chandrakasan |
A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007, pp. 328-606, 2007, IEEE, 1-4244-0853-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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6 | Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici |
Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 11-20, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Sub-VToperation, variation compensation, logic style, active-mode leakage, process variations |
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