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Publication types (Num. hits)
article(1216) book(3) data(1) incollection(12) inproceedings(1348) phdthesis(23)
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Found 2603 publication records. Showing 2603 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
101Jae-Jin Lee, Gi-Yong Song Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
92Nam Ling, Magdy A. Bayoumi Systolic temporal arithmetic: a new formalism for specification and verification of systolic arrays. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
88Oscar H. Ibarra, Stephen M. Sohn On Mapping Systolic Algorithms onto the Hypercube. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1990 DBLP  DOI  BibTeX  RDF parallel to parallel mappings, time-space graph, one way linear systolic array, systolic array algorithms, fixed-size hypercube architecture, two-dimensional systolic arrays, 64-node NCUBE/7 MIMD hypercube machine, shuffle scheduling problem, finite impulse response filtering, linear context-free language recognition, Boolean transitive closure, performance evaluation, parallel algorithms, computational complexity, parallel computers, parallel architectures, hypercube, matrix multiplication, interprocessor communication, cellular arrays, systolic algorithms, local computation
84PeiZong Lee, Zvi M. Kedem Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1990 DBLP  DOI  BibTeX  RDF nested loop algorithms, multidimensional systolic arrays, correct transformation, programmable systolic arrays, general purpose programmable arrays, planar systolic array implementations, three-dimensional cube-graph algorithm, reindexed Warshall-Floyd path-finding algorithm, parallel algorithms, parallel processing, graph theory, matrix multiplication, data dependence, matrix algebra, cellular arrays, sufficient conditions, necessary conditions, algorithm transformations, automatic compilation
80Hyesook Lim, Earl E. Swartzlander Jr. An efficient systolic array for the discrete cosine transform based on prime-factor decomposition . Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF prime-factor decomposition, index mappings, VLSI, discrete cosine transforms, discrete cosine transform, systolic arrays, systolic array, VLSI implementation, array signal processing
76Guy Even, Ami Litman Overcoming chip-to-chip delays and clock skews. Search on Bibsonomy ASAP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF chip-to-chip delays, chip-to-chip interconnections, feasible clock period, large systolic linear arrays, systolic two-dimensional arrays, logic duplication, delays, logic design, systolic arrays, systolic array, functionality, retiming, clock skews
76S. Ramanathan, V. Visvanathan A systolic architecture for LMS adaptive filtering with minimal adaptation delay. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF LMS adaptive filtering, minimal adaptation delay, convergence behaviour, function preserving transformations, SFG representation, carry-save arithmetic, systolic folded pipelined architecture, VLSI, delays, systolic arrays, pipeline processing, adaptive filters, digital filters, digital signal processing chips, convergence of numerical methods, systolic architecture, signal flow graphs, signal flow graph, least mean squares methods, LMS algorithm
75Adrian Vrouwenvelder, Keith R. Allen, Roy P. Pargas Translating systolic arrays into instruction systolic arrays. Search on Bibsonomy ACM Conference on Computer Science The full citation details ... 1988 DBLP  DOI  BibTeX  RDF SAGE
72Jae-Jin Lee, Gi-Yong Song Super Semi-systolic Array-Based Application-Specific PLD Architecture. Search on Bibsonomy ARC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
72Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri Area efficient computing structures for concurrent error detection in systolic arrays. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
72Xiaoxiong Zhong, Sanjay V. Rajopadhye, Ivan Wong Systematic generation of linear allocation functions in systolic array design. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
72G. A. Frank, E. M. Greenawalt, A. V. Kulkarni A systolic processor for signal processing. Search on Bibsonomy AFIPS National Computer Conference The full citation details ... 1982 DBLP  DOI  BibTeX  RDF
67Soonhak Kwon, Chang Kim, Chun Pyo Hong Unidirectional Two Dimensional Systolic Array for Multiplication in GF(2m) Using LSB First Algorithm. Search on Bibsonomy WILF The full citation details ... 2005 DBLP  DOI  BibTeX  RDF LSB first algorithm, VLSI, finite field, Systolic array, data flow, fault tolerant architecture
67N. Ranganathan, K. B. Doreswamy A systolic algorithm and architecture for image thinning. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF image thinning, 4-distance transform, single VLSI chip, 2.59 ms, 0.327 ms, parallel algorithms, image processing, VLSI, parallelism, skeleton, systolic arrays, CMOS, pipeline processing, VLSI architecture, digital signal processing chips, processing elements, CMOS digital integrated circuits, linear time, systolic architecture, systolic algorithm, multiple objects
67E. Pascal Gribomont, Vincent Van Dongen Generic Systolic Arrays: A Methodology for Systolic Design. Search on Bibsonomy TAPSOFT The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
64Vamsi Krishna, Abdel Ejnioui, N. Ranganathan A tree matching chip. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF tree matching chip, online interpreter systems, linear systolic array algorithms, fixed size linear array, Cadence design tools, parallel algorithms, VLSI, compilers, object recognition, image recognition, systolic arrays, digital signal processing chips, code optimization, 3D object recognition, vision systems, systolic architecture
63Hartmut Schmeck, Heiko Schröder 0001 Dictionary Machines for Different Models of VLSI. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1985 DBLP  DOI  BibTeX  RDF VLSI hardware models, Dictionary machines. are taken as an example to demonstrate the implications the choice of the VLSI hardware model has on the design and analysis of algorithms and special purpose architectures, A systolic search tree and a two-dimensional systolic array are used to implement the dictionary machine, If the wire lengths only affect the area, the systolic search tree suggests itself as an efficient realization of a dictionary machine having constant period, linear areS and logarithmic execution t, Algorithms for VLSI, systolic search tree, systolic array, VLSI complexity, dictionary machine
63Vwani P. Roychowdhury, Thomas Kailath Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
63Nikolay Petkov Turkedjiev Synthesis of Systolic Algorithms and Processor Arrays. Search on Bibsonomy CONPAR The full citation details ... 1986 DBLP  DOI  BibTeX  RDF
63Earl E. Swartzlander Jr. Systolic FFT Processors: A Personal Perspective. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF systolic systems, frequency domain adaptive digital filters, systolic FFT, fast fourier transforms
59M. Ch. Karra, M. P. Bekakos A FPGA-Based Systolic Array Prototype Implementing the Quadrant Interlocking Factorization Method. Search on Bibsonomy J. Supercomput. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF FPGA technology, parallelism, finite-state machine, time complexity, systolic arrays, processing elements
59Nuha A. S. Alwan A Fully Pipelined Systolic Array for Sinusoidal Sequence Generation. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Trigonometric series, sinusoidal sequence generation, pipelining, systolic arrays
59Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong Compact Linear Systolic Arrays for Multiplication Using a Trinomial Basis in GF(2m) for High Speed Cryptographic Processors. Search on Bibsonomy ICCSA (1) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF VLSI, finite field, systolic array, irreducible trinomial
59Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong A Linear Systolic Array for Multiplication in GF(2m) for High Speed Cryptographic Processors. Search on Bibsonomy ICCSA (4) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Riemann Hypothesis, Artins conjecture for primitive roots, systolic array, Finite field multiplier, all one polynomial
59Chin-Liang Wang, Jyh-Huei Guo New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m). Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF finite field division, finite field inversion, parallel-in parallel-out architecture, VLSI, systolic array, Finite field arithmetic
59Çetin Kaya Koç, Ching Yu Hung Bit-level systolic arrays for modular multiplication. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF sign estimation, scheduling, systolic array, modular multiplication, carry save adders
59Nuha A. S. Alwan Systematic Design of Systolic Correlators with Application to Parallel Blackman-Tukey Spectral Estimation. Search on Bibsonomy Computing The full citation details ... 2001 DBLP  DOI  BibTeX  RDF Blackman, Tukey spectral estimation, systematic design of systolic arrays, systolic correlators, systolic DFT
59Abdel Ejnioui, N. Ranganathan Systolic algorithms for tree pattern matching. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF pattern tree, subject tree, PRAM model of computation, linear systolic array model, parallel algorithms, parallel algorithms, pattern matching, systolic arrays, SIMD machine, systolic algorithms, tree pattern matching
55Mauricio Ayala-Rincón, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Term Rewriting Systems (TRS), algebraic manipulation, dynamically reconfigurable systems, Fast Fourier Transform (FFT), reconfigurable computing, systolic arrays, rewriting-logic
55Mauricio Ayala-Rincón, Rodrigo Borges Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein Efficient Computation of Algebraic Operations over Dynamically Reconfigurable Systems Specified by Rewriting-Logic Environments. Search on Bibsonomy SCCC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Reconfigurable Systolic Arrays, Fast Fourier Transform, Rewriting-Logic, Term Rewriting Systems
55Eric M. Dowling, Zuqiang Fu, Ron S. Drafz HARP: An Open Architecture for Parallel Matrix and Signal Processing. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF HARP, matrix processing, Hybrid Array RingProcessor, memory mapped processing cells, open backplane, bidirectional systolic ring, bus controller, DMA function, systolic communication, reduced overhead message passing, digital signalprocessor, systolicarray, parallel algorithms, parallel, parallel architectures, multiprocessor, shared memory, signal processing, signal processing, systolic arrays, shared memory systems, interprocessor communication, open architecture, Application specific architecture
55Karl-Heinz Zimmermann A Unifying Lattice-Based Approach for the Partitioning of Systolic Arrays via LPGS and LSGP. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
55Nam Ling A special purpose formal verifier for systolic designs in DSP applications. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
55Monica Lam 0001 Compiler Optimizations for Asynchronous Systolic Array Programs. Search on Bibsonomy POPL The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
54Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr. Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCT. Search on Bibsonomy ASAP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF finite word-length effects, unified systolic array, fixed-point error analysis, inverse discrete cosine transform, fixed-point rounding-errors, minimum word-length, fixed-point error, discrete cosine transforms, discrete cosine transform, systolic arrays, digital simulation, error analysis, simulation results, roundoff errors, closed form expressions, truncation-errors
54V. Visvanathan, S. Ramanathan A modular systolic architecture for delayed least mean squares adaptive filtering. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF modular systolic architecture, delayed least mean squares adaptive filtering, coefficient adaptation, input sampling periods, output latency, convergence behavior, systolization technique, maximum sampling rate, multiply-accumulate processor modules, systolic arrays, pipeline processing, adaptive filters, convergence of numerical methods, least mean squares methods
54Chris J. Scheiman, Peter R. Cappello A Processor-Time-Minimal Systolic Array for Transitive Closure. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF processor-time-minimal multiprocessor schedules, 2-D mesh, parallel algorithms, systolic array, systolic arrays, directed acyclic graph, multiprocessor schedule, transitive closure
51Moha'med O. Al-Jaafreh, Adel Ali Al-Jumaily Type-2 Fuzzy System Based Blood Pressure Parameters Estimation. Search on Bibsonomy Asia International Conference on Modelling and Simulation The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Type-2 Fuzzy System, photo-plethysmography, Heart rate, Blood Pressure
50Risto Honkanen Systolic Routing in an Optical Fat Tree. Search on Bibsonomy ISPA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Optical fat tree, systolic routing, work-optimal routing
50Chien-Hsing Wu 0002, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m). Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Stein's algorithm, Euclid's algorithm, Finite field, systolic array, division
50Chang Hoon Kim, Soonhak Kwon, Chun Pyo Hong, Hiecheol Kim A New Systolic Array for Least Significant Digit First Multiplication in GF(2m). Search on Bibsonomy ICCSA (3) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Digit-Serial Architecture, VLSI, Cryptography, Systolic Array, Finite Field Multiplication
50Pol-Lin Tai, Chii-Tung Liu, Jia-Shung Wang An Integrated Systolic Array Design for Video Compression. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF integrated systolic design, wavelet transform, vector quantization, block-matching
50Soonhak Kwon Low Complexity Bit Serial Systolic Multipliers over GF(2m) for Three Classes of Finite Fields. Search on Bibsonomy ICICS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF systolic multiplier, finite field, basis, all one polynomial
50Fikret Erçal, Mark Allen, Hao Feng 0001 A Systolic Image Difference Algorithm for RLE-Compressed Images. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF image compression, run-length encoding, Systolic algorithm, image difference
50Yen-Chun Lin, Jyh-Chian Chen An Efficient Systolic Algorithm for the Longest Common Subsequence Problem. Search on Bibsonomy J. Supercomput. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF parallel algorithm, VLSI, systolic array, multicomputer, Longest common subsequence
50Peter Kornerup A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF systolic linear-array multiplier, right-shift algorithms, multiplier cell, digit-product terms, least significant digit first, active elements, module-multiplier, Montgomery module-reduction, RSA encryption, modular division, cryptography, logic design, systolic arrays, systolic array, digital arithmetic, multiplying circuits, latches, modular inverses, Hensel codes, digit-serial multiplier
50Elio D. Di Claudio, Gianni Orlandi, Francesco Piazza A Systolic Redundant Residue Arithmetic Error Correction Circuit. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF systolic redundant residue arithmetic error correction circuit, concurrent fault tolerance capability, redundant residue number system, high speed VLSI circuit realization, parallel systolic architecture, parallel algorithms, VLSI, systolic arrays, digital arithmetic, error correction, real-time applications, error recovery, decision table, processing element, transient errors, residue arithmetic, memory element
50Paul S. Lewis, Sun-Yuan Kung An Optimal Systolic Array for the Algebraic Path Problem. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1991 DBLP  DOI  BibTeX  RDF optimal systolic array, orthogonally connected processing elements, systolic implementation, logic design, systolic arrays, processing elements, algebraic path problem
50Rami G. Melhem A Systolic Accelerator for the Iterative Solution of Sparse Linear Systems. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1989 DBLP  DOI  BibTeX  RDF stripe structures, preconditioned conjugate gradient, iterative solution, nonzero elements, systolic accelerator, computationally irregular problems, systolic networks, parallel processing, iterative methods, systolic arrays, matrix algebra, buffering, cellular arrays, sparse matrix, special purpose computers, sparse linear systems, data movement
47Mauricio Ayala-Rincón, Ricardo P. Jacobi, Luis Gustavo A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic. Search on Bibsonomy SBCCI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF configware, morphware, reconfigurable systolic arrays, term rewriting systems (TRS), dynamic programming, rewriting-logic
47Rumen Andonov, Sanjay V. Rajopadhye Knapsack on VLSI: from Algorithm to Optimal Circuit. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Application specific VLSI design, unbounded knapsack problem, space-time transformations, recurrence equations, dynamic dependencies, nonlinear discrete optimization, correctness preserving transformations, systolic arrays
46Antonio E. de la Serna Differential Scoring for Systolic Sequence Alignment. Search on Bibsonomy BIBE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
46Kentaro Sano, Takanori Iizuka, Satoru Yamamoto Systolic Architecture for Computational Fluid Dynamics on FPGAs. Search on Bibsonomy FCCM The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
46Yun Yang, Wenqing Zhao, Yasuaki Inoue High-performance systolic arrays for band matrix multiplication. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
46Gloria Martínez, Germán Fabregat, Vicente Hernández Solving the Generalized Sylvester Equation with a Systolic Library. Search on Bibsonomy VECPAR The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
46Fikret Erçal, Mark Allen, Hao Feng 0001 A Systolic Algorithm to Process Compressed Binary Images. Search on Bibsonomy IPPS/SPDP The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
46Bertil Schmidt, Manfred Schimmler, Heiko Schröder 0001 Long Operand Arithmetic on Instruction Systolic Computer Architectures and Its Application in RSA Cryptography. Search on Bibsonomy Euro-Par The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
46Lynn M. Stauffer, Daniel S. Hirschberg Systolic Self-Organizing Lists Under Transpose. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
46Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri, Dhamin Al-Khalili Design techniques for fault-tolerant systolic arrays. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
46Cheng-Wen Wu, Ming-Kwang Chang Bit-level systolic arrays for finite-field multiplications. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
46Angelo Monti, Adriano Peron Systolic Tree Omega-Languages. Search on Bibsonomy STACS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
46Marc Moonen Implementing the square-root information Kalman filter on a Jacobi-type systolic array. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
46José L. Hueso, Gloria Martínez, Vicente Hernández A systolic algorithm for the triangular Stein equation. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
46Tatyana D. Roziner, Mark G. Karpovsky Multidimensional fourier transforms by systolic architectures. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
46Xiaoxiong Zhong, Sanjay V. Rajopadhye Deriving Fully Efficient Systolic Arrays by Quasi-Linear Allocation Functions. Search on Bibsonomy PARLE (1) The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
46Norihiko Yoshida Transformational Derivation of Systolic Arrays. Search on Bibsonomy Concurrency: Theory, Language, And Architecture The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
46Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero Systematic Hardware Adaptation of Systolic Algorithms. Search on Bibsonomy ISCA The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
46Shek-Wayne Chan, Chin-Long Wey The design of concurrent error diagnosable systolic arrays for band matrix multiplications. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
46Anup B. Sharma, Keith R. Allen, Roy P. Pargas Some new systolic designs for two-dimensional convolution. Search on Bibsonomy ACM Conference on Computer Science The full citation details ... 1988 DBLP  DOI  BibTeX  RDF SAGE, SAGE
46David Y. Y. Yun, Y. Yun, Chang Nian Zhang Formal verification of systolic networks using theorem proving techniques (abstract only). Search on Bibsonomy ACM Conference on Computer Science The full citation details ... 1987 DBLP  DOI  BibTeX  RDF
46Chua-Huang Huang, Christian Lengauer An Implemented Method for Incremmental Systolic Design. Search on Bibsonomy PARLE (1) The full citation details ... 1987 DBLP  DOI  BibTeX  RDF
46Yves Robert Systolic Algorithms for Path- Finding Problems. Search on Bibsonomy Automata Networks The full citation details ... 1986 DBLP  DOI  BibTeX  RDF
46A. A. Abdel Kader OCSAMO - A Systolic Array for Matrix Operations. Search on Bibsonomy CONPAR The full citation details ... 1986 DBLP  DOI  BibTeX  RDF
46Tudor Jebelean Design of a systolic coprocessor for rational addition. Search on Bibsonomy ASAP The full citation details ... 1995 DBLP  DOI  BibTeX  RDF systolic coprocessor, rational addition, exact division, field programmable gate arrays, parallel architectures, systolic arrays, digital arithmetic, multiplication, addition, subtraction, rational numbers, GCD
46Judith O. Berkey, Pearl Y. Wang A Systolic-Based Parallel Bin Packing Algorithm. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF systolic-based parallel bin packing algorithm, asymptotic error bound, execution performance, serial algorithms, parallel algorithms, computational complexity, approximation algorithm, parallelizations, time complexity, systolic arrays, operations research
46Peter R. Cappello A Processor-Time-Minimal Systolic Array for Cubical Mesh Algorithms. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF hexagon shaped, cylinder connected, processor-time-minimal systolic array, cubical meshalgorithms, time-minimal multiprocessor schedules, processor-time-minimal scheduling, triangular shaped 2-D directed mesh, 2-D directed mesh, directedgraphs, parallel algorithms, computational complexity, topology, systolic arrays, directed acyclic graph, processing elements, matrix product
46Christian Lengauer, Jingling Xue A systolic array for pyramidal algorithms. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF pyramid node linking, systolic design, image processing, image segmentation, systolic array
42Sudhir Vinjamuri, Viktor K. Prasanna Hierarchical Dependency Graphs: Abstraction and Methodology for Mapping Systolic Array Designs to Multicore Processors. Search on Bibsonomy PaCT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF systolic array designs, parallel programming, high performance computing, multicore, dependency graphs
42Chiou-Yng Lee, Che Wun Chiou New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2m) Under Polynomial Basis and Normal Basis Representations. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF finite field, normal basis, polynomial basis, bit-parallel systolic multiplier
42Kung Yao, Flavio Lorenzelli Systolic Algorithms and Architectures for High-Throughput Processing Applications. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF recursive least-squares estimation, Kalman filtering, systolic array, linear algebra, QR decomposition, least-squares estimation
42Emina I. Milovanovic, Igor Z. Milovanovic, Michael P. Bekakos, I. N. Tselepis Computing all-pairs shortest paths on a linear systolic array and hardware realization on a reprogrammable FPGA platform. Search on Bibsonomy J. Supercomput. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF FPGA, Parallel computations, Systolic arrays, All-pairs shortest paths, Parallel iterative methods
42Yunbi Chen, Jingsong He Using Systolic Technique to Accelerate an EHW Engine for Lossless Image Compression. Search on Bibsonomy ICES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Image Compression, Systolic Array, Evolvable Hardware, Fitness Evaluation
42Ting Qin, Haitao Zhang, Zonghai Chen, Wei Xiang Continuous CMAC-QRLS and Its Systolic Array. Search on Bibsonomy Neural Process. Lett. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF CMAC-QRLS, systolic array, B-splines, QR decomposition
42Amir K. Daneshbeh, M. Anwarul Hasan A Class of Unidirectional Bit Serial Systolic Architectures for Multiplicative Inversion and Division over GF(2m). Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF field arithmetic, finite fields, systolic arrays, Division, inversion, extended Euclidean algorithm
42Chiou-Yng Lee, Jenn-Shyong Horng, I-Chang Jou, Erl-Huei Lu Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2m). Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF irreducible AOP, finite field, montgomery multiplication, irreducible trinomial, Bit-parallel systolic multiplier
42A. Chorevas, Dionysios I. Reisis Efficient Systolic Array Mapping of FIR Filters Used in PAM-QAM Modulators. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF VLSI, FIR filter, systolic architectures, QAM
42Sek M. Chai, D. Scott Wills Systolic Opportunities for Multidimensional Data Streams. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF area I/O, design and performance evaluation, systolic arrays, parallel computer architecture
42J. H. Weston, Chang N. Zhang, Hua Li Some Space Considerations of VLSI Systolic Array Mappings. Search on Bibsonomy ICPADS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF nested loop algorithm, systolic array, matrix, processing element, space-time mapping
42Jean Frédéric Myoupo, Anne-Cécile Fabret A Modular Systolic Linearization of the Warshall-Floyd Algorithm. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Modular linear systolic algorithms, shortest path, matrix multiplication, transitive closure
42Noriaki Muranaka, Shigenobu Arai, Shigeru Imanishi, D. Michael Miller A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs. Search on Bibsonomy ISMVL The full citation details ... 1996 DBLP  DOI  BibTeX  RDF neuron MOSFET, product sum computation, systolic array, Ternary logic
42Yin Chan, Sun-Yuan Kung Bit Level Block Matching Systolic Arrays. Search on Bibsonomy ASAP The full citation details ... 1995 DBLP  DOI  BibTeX  RDF bit level systolic array, video signal processing architecture, pipeline, block matching
42Catherine Mongenet, Guy-René Perrin Synthesis of Systolic arrays for Inductive Problems. Search on Bibsonomy PARLE (1) The full citation details ... 1987 DBLP  DOI  BibTeX  RDF synthesis, systolic arrays
41I. M. Bland, Graham M. Megson The Systolic Array Genetic Algorithm, An Example of Systolic Arrays as a Reconfigurable Design Methodology. Search on Bibsonomy FCCM The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
38Lejla Batina, Geeke Muurling Montgomery in Practice: How to Do It More Efficiently in Hardware. Search on Bibsonomy CT-RSA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF scalability, performance model, systolic array, Montgomery multiplication, modular exponentiation
38Vera P. Behar, Christo A. Kabakchiev, Lyubka Doukovska Adaptive CFAR PI Processor for Radar Target Detection in Pulse Jamming. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF CFAR API processor, detection in pulse jamming, target detection performance calculation, parallel algorithms, systolic architecture
38J. G. Liu 0001, Francis H. Y. Chan, Francis K. Lam, Hon Fung Li A Novel Approach to Fast Discrete Hartley Transform. Search on Bibsonomy ISPAN The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Hartley transform, parallel processing, systolic array, moment, fast transform
38Jean Frédéric Myoupo A Fully-Pipelined Solutions Constructor for Dynamic Programming Problems. Search on Bibsonomy ICCI The full citation details ... 1991 DBLP  DOI  BibTeX  RDF Modular Arrays, Parallel Algorithms, Complexity, Dynamic Programming, Design of Algorithms, Linear Systolic Arrays
38Alexandre Abellard, Patrick Abellard A Design Methodology of Systolic Architectures Based on a Petri Net Extension. Application to a Stereovision Hardware/Software Processing Improvement. Search on Bibsonomy ICSEA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
38A. Neslin Ismailoglu, Murat Askar SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation. Search on Bibsonomy DSD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
38Laura Ruff Functional-Based Comparison between Two Special Classes of Uni- and Bidirectional Systolic Arrays. Search on Bibsonomy SYNASC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
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