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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 2603 publication records. Showing 2603 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
101 | Jae-Jin Lee, Gi-Yong Song |
Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 249, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
92 | Nam Ling, Magdy A. Bayoumi |
Systolic temporal arithmetic: a new formalism for specification and verification of systolic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8), pp. 804-820, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
88 | Oscar H. Ibarra, Stephen M. Sohn |
On Mapping Systolic Algorithms onto the Hypercube. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 1(1), pp. 48-63, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
parallel to parallel mappings, time-space graph, one way linear systolic array, systolic array algorithms, fixed-size hypercube architecture, two-dimensional systolic arrays, 64-node NCUBE/7 MIMD hypercube machine, shuffle scheduling problem, finite impulse response filtering, linear context-free language recognition, Boolean transitive closure, performance evaluation, parallel algorithms, computational complexity, parallel computers, parallel architectures, hypercube, matrix multiplication, interprocessor communication, cellular arrays, systolic algorithms, local computation |
84 | PeiZong Lee, Zvi M. Kedem |
Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 1(1), pp. 64-76, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
nested loop algorithms, multidimensional systolic arrays, correct transformation, programmable systolic arrays, general purpose programmable arrays, planar systolic array implementations, three-dimensional cube-graph algorithm, reindexed Warshall-Floyd path-finding algorithm, parallel algorithms, parallel processing, graph theory, matrix multiplication, data dependence, matrix algebra, cellular arrays, sufficient conditions, necessary conditions, algorithm transformations, automatic compilation |
80 | Hyesook Lim, Earl E. Swartzlander Jr. |
An efficient systolic array for the discrete cosine transform based on prime-factor decomposition . ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 644-649, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
prime-factor decomposition, index mappings, VLSI, discrete cosine transforms, discrete cosine transform, systolic arrays, systolic array, VLSI implementation, array signal processing |
76 | Guy Even, Ami Litman |
Overcoming chip-to-chip delays and clock skews. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 199-208, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
chip-to-chip delays, chip-to-chip interconnections, feasible clock period, large systolic linear arrays, systolic two-dimensional arrays, logic duplication, delays, logic design, systolic arrays, systolic array, functionality, retiming, clock skews |
76 | S. Ramanathan, V. Visvanathan |
A systolic architecture for LMS adaptive filtering with minimal adaptation delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 286-289, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
LMS adaptive filtering, minimal adaptation delay, convergence behaviour, function preserving transformations, SFG representation, carry-save arithmetic, systolic folded pipelined architecture, VLSI, delays, systolic arrays, pipeline processing, adaptive filters, digital filters, digital signal processing chips, convergence of numerical methods, systolic architecture, signal flow graphs, signal flow graph, least mean squares methods, LMS algorithm |
75 | Adrian Vrouwenvelder, Keith R. Allen, Roy P. Pargas |
Translating systolic arrays into instruction systolic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Conference on Computer Science ![In: Proceedings of the Sixteenth ACM Annual Conference on Computer Science, Atlanta, Georgia, USA, February 23-25, 1988, pp. 357-365, 1988, ACM, 0-89791-260-8. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
SAGE |
72 | Jae-Jin Lee, Gi-Yong Song |
Super Semi-systolic Array-Based Application-Specific PLD Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 461-466, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
72 | Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri |
Area efficient computing structures for concurrent error detection in systolic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 10(3), pp. 237-260, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
72 | Xiaoxiong Zhong, Sanjay V. Rajopadhye, Ivan Wong |
Systematic generation of linear allocation functions in systolic array design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 4(4), pp. 279-293, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
72 | G. A. Frank, E. M. Greenawalt, A. V. Kulkarni |
A systolic processor for signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS National Computer Conference ![In: American Federation of Information Processing Societies: 1982 National Computer Conference, 7-10 June, 1982, Houston, Texas, USA, pp. 225-231, 1982, AFIPS Press, 0-88283-035-X. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
|
67 | Soonhak Kwon, Chang Kim, Chun Pyo Hong |
Unidirectional Two Dimensional Systolic Array for Multiplication in GF(2m) Using LSB First Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WILF ![In: Fuzzy Logic and Applications, 6th International Workshop, WILF 2005, Crema, Italy, September 15-17, 2005, Revised Selected Papers, pp. 420-426, 2005, Springer, 3-540-32529-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
LSB first algorithm, VLSI, finite field, Systolic array, data flow, fault tolerant architecture |
67 | N. Ranganathan, K. B. Doreswamy |
A systolic algorithm and architecture for image thinning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 138-143, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
image thinning, 4-distance transform, single VLSI chip, 2.59 ms, 0.327 ms, parallel algorithms, image processing, VLSI, parallelism, skeleton, systolic arrays, CMOS, pipeline processing, VLSI architecture, digital signal processing chips, processing elements, CMOS digital integrated circuits, linear time, systolic architecture, systolic algorithm, multiple objects |
67 | E. Pascal Gribomont, Vincent Van Dongen |
Generic Systolic Arrays: A Methodology for Systolic Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TAPSOFT ![In: TAPSOFT'93: Theory and Practice of Software Development, International Joint Conference CAAP/FASE, Orsay, France, April 13-17, 1993, Proceedings, pp. 746-761, 1993, Springer, 3-540-56610-4. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
64 | Vamsi Krishna, Abdel Ejnioui, N. Ranganathan |
A tree matching chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 280-285, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
tree matching chip, online interpreter systems, linear systolic array algorithms, fixed size linear array, Cadence design tools, parallel algorithms, VLSI, compilers, object recognition, image recognition, systolic arrays, digital signal processing chips, code optimization, 3D object recognition, vision systems, systolic architecture |
63 | Hartmut Schmeck, Heiko Schröder 0001 |
Dictionary Machines for Different Models of VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 34(5), pp. 472-475, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
VLSI hardware models, Dictionary machines. are taken as an example to demonstrate the implications the choice of the VLSI hardware model has on the design and analysis of algorithms and special purpose architectures, A systolic search tree and a two-dimensional systolic array are used to implement the dictionary machine, If the wire lengths only affect the area, the systolic search tree suggests itself as an efficient realization of a dictionary machine having constant period, linear areS and logarithmic execution t, Algorithms for VLSI, systolic search tree, systolic array, VLSI complexity, dictionary machine |
63 | Vwani P. Roychowdhury, Thomas Kailath |
Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 1(2), pp. 127-142, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
63 | Nikolay Petkov Turkedjiev |
Synthesis of Systolic Algorithms and Processor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: CONPAR 86: Conference on Algorithms and Hardware for Parallel Processing, Aachen, Germany, September 17-19, 1986, Proceedings, pp. 165-172, 1986, Springer, 3-540-16811-7. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
63 | Earl E. Swartzlander Jr. |
Systolic FFT Processors: A Personal Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(1-2), pp. 3-14, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
systolic systems, frequency domain adaptive digital filters, systolic FFT, fast fourier transforms |
59 | M. Ch. Karra, M. P. Bekakos |
A FPGA-Based Systolic Array Prototype Implementing the Quadrant Interlocking Factorization Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 37(3), pp. 319-331, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPGA technology, parallelism, finite-state machine, time complexity, systolic arrays, processing elements |
59 | Nuha A. S. Alwan |
A Fully Pipelined Systolic Array for Sinusoidal Sequence Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(5), pp. 636-639, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Trigonometric series, sinusoidal sequence generation, pipelining, systolic arrays |
59 | Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong |
Compact Linear Systolic Arrays for Multiplication Using a Trinomial Basis in GF(2m) for High Speed Cryptographic Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (1) ![In: Computational Science and Its Applications - ICCSA 2005, International Conference, Singapore, May 9-12, 2005, Proceedings, Part I, pp. 508-518, 2005, Springer, 3-540-25860-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
VLSI, finite field, systolic array, irreducible trinomial |
59 | Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong |
A Linear Systolic Array for Multiplication in GF(2m) for High Speed Cryptographic Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (4) ![In: Computational Science and Its Applications - ICCSA 2004, International Conference, Assisi, Italy, May 14-17, 2004, Proceedings, Part IV, pp. 106-116, 2004, Springer, 3-540-22060-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Riemann Hypothesis, Artins conjecture for primitive roots, systolic array, Finite field multiplier, all one polynomial |
59 | Chin-Liang Wang, Jyh-Huei Guo |
New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(10), pp. 1120-1125, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
finite field division, finite field inversion, parallel-in parallel-out architecture, VLSI, systolic array, Finite field arithmetic |
59 | Çetin Kaya Koç, Ching Yu Hung |
Bit-level systolic arrays for modular multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 3(3), pp. 215-223, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
sign estimation, scheduling, systolic array, modular multiplication, carry save adders |
59 | Nuha A. S. Alwan |
Systematic Design of Systolic Correlators with Application to Parallel Blackman-Tukey Spectral Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computing ![In: Computing 66(4), pp. 395-412, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Blackman, Tukey spectral estimation, systematic design of systolic arrays, systolic correlators, systolic DFT |
59 | Abdel Ejnioui, N. Ranganathan |
Systolic algorithms for tree pattern matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 650-702, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
pattern tree, subject tree, PRAM model of computation, linear systolic array model, parallel algorithms, parallel algorithms, pattern matching, systolic arrays, SIMD machine, systolic algorithms, tree pattern matching |
55 | Mauricio Ayala-Rincón, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein |
Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(2), pp. 251-281, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Term Rewriting Systems (TRS), algebraic manipulation, dynamically reconfigurable systems, Fast Fourier Transform (FFT), reconfigurable computing, systolic arrays, rewriting-logic |
55 | Mauricio Ayala-Rincón, Rodrigo Borges Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein |
Efficient Computation of Algebraic Operations over Dynamically Reconfigurable Systems Specified by Rewriting-Logic Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCCC ![In: 23rd International Conference of the Chilean Computer Science Society (SCCC 2003), 6-7 November 2003, Chillan, Chile, pp. 60-, 2003, IEEE Computer Society, 0-7695-2008-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Reconfigurable Systolic Arrays, Fast Fourier Transform, Rewriting-Logic, Term Rewriting Systems |
55 | Eric M. Dowling, Zuqiang Fu, Ron S. Drafz |
HARP: An Open Architecture for Parallel Matrix and Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(10), pp. 1081-1091, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
HARP, matrix processing, Hybrid Array RingProcessor, memory mapped processing cells, open backplane, bidirectional systolic ring, bus controller, DMA function, systolic communication, reduced overhead message passing, digital signalprocessor, systolicarray, parallel algorithms, parallel, parallel architectures, multiprocessor, shared memory, signal processing, signal processing, systolic arrays, shared memory systems, interprocessor communication, open architecture, Application specific architecture |
55 | Karl-Heinz Zimmermann |
A Unifying Lattice-Based Approach for the Partitioning of Systolic Arrays via LPGS and LSGP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 17(1), pp. 21-41, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
55 | Nam Ling |
A special purpose formal verifier for systolic designs in DSP applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 11(1-2), pp. 169-187, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
55 | Monica Lam 0001 |
Compiler Optimizations for Asynchronous Systolic Array Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POPL ![In: Conference Record of the Fifteenth Annual ACM Symposium on Principles of Programming Languages, San Diego, California, USA, January 10-13, 1988, pp. 309-318, 1988, ACM Press, 0-89791-252-7. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
54 | Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr. |
Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 35-, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
finite word-length effects, unified systolic array, fixed-point error analysis, inverse discrete cosine transform, fixed-point rounding-errors, minimum word-length, fixed-point error, discrete cosine transforms, discrete cosine transform, systolic arrays, digital simulation, error analysis, simulation results, roundoff errors, closed form expressions, truncation-errors |
54 | V. Visvanathan, S. Ramanathan |
A modular systolic architecture for delayed least mean squares adaptive filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 332-337, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
modular systolic architecture, delayed least mean squares adaptive filtering, coefficient adaptation, input sampling periods, output latency, convergence behavior, systolization technique, maximum sampling rate, multiply-accumulate processor modules, systolic arrays, pipeline processing, adaptive filters, convergence of numerical methods, least mean squares methods |
54 | Chris J. Scheiman, Peter R. Cappello |
A Processor-Time-Minimal Systolic Array for Transitive Closure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 3(3), pp. 257-269, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
processor-time-minimal multiprocessor schedules, 2-D mesh, parallel algorithms, systolic array, systolic arrays, directed acyclic graph, multiprocessor schedule, transitive closure |
51 | Moha'med O. Al-Jaafreh, Adel Ali Al-Jumaily |
Type-2 Fuzzy System Based Blood Pressure Parameters Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia International Conference on Modelling and Simulation ![In: Second Asia International Conference on Modelling and Simulation, AMS 2008, Kuala Lumpur, Malaysia, May 13-15, 2008, pp. 953-958, 2008, IEEE Computer Society, 978-0-7695-3136-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Type-2 Fuzzy System, photo-plethysmography, Heart rate, Blood Pressure |
50 | Risto Honkanen |
Systolic Routing in an Optical Fat Tree. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: Parallel and Distributed Processing and Applications, Third International Symposium, ISPA 2005, Nanjing, China, November 2-5, 2005, Proceedings, pp. 514-523, 2005, Springer, 3-540-29769-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Optical fat tree, systolic routing, work-optimal routing |
50 | Chien-Hsing Wu 0002, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang |
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(3), pp. 375-380, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Stein's algorithm, Euclid's algorithm, Finite field, systolic array, division |
50 | Chang Hoon Kim, Soonhak Kwon, Chun Pyo Hong, Hiecheol Kim |
A New Systolic Array for Least Significant Digit First Multiplication in GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (3) ![In: Computational Science and Its Applications - ICCSA 2004, International Conference, Assisi, Italy, May 14-17, 2004, Proceedings, Part III, pp. 656-666, 2004, Springer, 3-540-22057-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Digit-Serial Architecture, VLSI, Cryptography, Systolic Array, Finite Field Multiplication |
50 | Pol-Lin Tai, Chii-Tung Liu, Jia-Shung Wang |
An Integrated Systolic Array Design for Video Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 33(1-2), pp. 157-169, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
integrated systolic design, wavelet transform, vector quantization, block-matching |
50 | Soonhak Kwon |
Low Complexity Bit Serial Systolic Multipliers over GF(2m) for Three Classes of Finite Fields. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICS ![In: Information and Communications Security, 4th International Conference, ICICS 2002, Singapore, December 9-12, 2002, Proceedings, pp. 209-216, 2002, Springer, 3-540-00164-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
systolic multiplier, finite field, basis, all one polynomial |
50 | Fikret Erçal, Mark Allen, Hao Feng 0001 |
A Systolic Image Difference Algorithm for RLE-Compressed Images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 11(5), pp. 433-443, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
image compression, run-length encoding, Systolic algorithm, image difference |
50 | Yen-Chun Lin, Jyh-Chian Chen |
An Efficient Systolic Algorithm for the Longest Common Subsequence Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 12(4), pp. 373-385, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
parallel algorithm, VLSI, systolic array, multicomputer, Longest common subsequence |
50 | Peter Kornerup |
A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(8), pp. 892-898, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
systolic linear-array multiplier, right-shift algorithms, multiplier cell, digit-product terms, least significant digit first, active elements, module-multiplier, Montgomery module-reduction, RSA encryption, modular division, cryptography, logic design, systolic arrays, systolic array, digital arithmetic, multiplying circuits, latches, modular inverses, Hensel codes, digit-serial multiplier |
50 | Elio D. Di Claudio, Gianni Orlandi, Francesco Piazza |
A Systolic Redundant Residue Arithmetic Error Correction Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(4), pp. 427-432, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
systolic redundant residue arithmetic error correction circuit, concurrent fault tolerance capability, redundant residue number system, high speed VLSI circuit realization, parallel systolic architecture, parallel algorithms, VLSI, systolic arrays, digital arithmetic, error correction, real-time applications, error recovery, decision table, processing element, transient errors, residue arithmetic, memory element |
50 | Paul S. Lewis, Sun-Yuan Kung |
An Optimal Systolic Array for the Algebraic Path Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 40(1), pp. 100-105, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
optimal systolic array, orthogonally connected processing elements, systolic implementation, logic design, systolic arrays, processing elements, algebraic path problem |
50 | Rami G. Melhem |
A Systolic Accelerator for the Iterative Solution of Sparse Linear Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(11), pp. 1591-1595, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
stripe structures, preconditioned conjugate gradient, iterative solution, nonzero elements, systolic accelerator, computationally irregular problems, systolic networks, parallel processing, iterative methods, systolic arrays, matrix algebra, buffering, cellular arrays, sparse matrix, special purpose computers, sparse linear systems, data movement |
47 | Mauricio Ayala-Rincón, Ricardo P. Jacobi, Luis Gustavo A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein |
Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 248-253, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
configware, morphware, reconfigurable systolic arrays, term rewriting systems (TRS), dynamic programming, rewriting-logic |
47 | Rumen Andonov, Sanjay V. Rajopadhye |
Knapsack on VLSI: from Algorithm to Optimal Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 8(6), pp. 545-561, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Application specific VLSI design, unbounded knapsack problem, space-time transformations, recurrence equations, dynamic dependencies, nonlinear discrete optimization, correctness preserving transformations, systolic arrays |
46 | Antonio E. de la Serna |
Differential Scoring for Systolic Sequence Alignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BIBE ![In: Proceedings of the 7th IEEE International Conference on Bioinformatics and Bioengineering, BIBE 2007, October 14-17, 2007, Harvard Medical School, Boston, MA, USA, pp. 1204-1208, 2007, IEEE Computer Society, 978-1-4244-1509-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Kentaro Sano, Takanori Iizuka, Satoru Yamamoto |
Systolic Architecture for Computational Fluid Dynamics on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2007, 23-25 April 2007, Napa, California, USA, pp. 107-116, 2007, IEEE Computer Society, 0-7695-2940-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Yun Yang, Wenqing Zhao, Yasuaki Inoue |
High-performance systolic arrays for band matrix multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1130-1133, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
46 | Gloria Martínez, Germán Fabregat, Vicente Hernández |
Solving the Generalized Sylvester Equation with a Systolic Library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VECPAR ![In: Vector and Parallel Processing - VECPAR 2000, 4th International Conference, Porto, Portugal, June 21-23, 2000, Selected Papers and Invited Talks, pp. 403-416, 2000, Springer, 3-540-41999-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
46 | Fikret Erçal, Mark Allen, Hao Feng 0001 |
A Systolic Algorithm to Process Compressed Binary Images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS/SPDP ![In: 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 12-16 April 1999, San Juan, Puerto Rico, Proceedings, pp. 477-484, 1999, IEEE Computer Society, 0-7695-0143-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
46 | Bertil Schmidt, Manfred Schimmler, Heiko Schröder 0001 |
Long Operand Arithmetic on Instruction Systolic Computer Architectures and Its Application in RSA Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '98 Parallel Processing, 4th International Euro-Par Conference, Southampton, UK, September 1-4, 1998, Proceedings, pp. 916-922, 1998, Springer, 3-540-64952-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
46 | Lynn M. Stauffer, Daniel S. Hirschberg |
Systolic Self-Organizing Lists Under Transpose. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 6(1), pp. 102-105, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
46 | Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri, Dhamin Al-Khalili |
Design techniques for fault-tolerant systolic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 11(1-2), pp. 151-168, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
46 | Cheng-Wen Wu, Ming-Kwang Chang |
Bit-level systolic arrays for finite-field multiplications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 10(1), pp. 85-92, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
46 | Angelo Monti, Adriano Peron |
Systolic Tree Omega-Languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STACS ![In: STACS 95, 12th Annual Symposium on Theoretical Aspects of Computer Science, Munich, Germany, March 2-4, 1995, Proceedings, pp. 131-142, 1995, Springer, 3-540-59042-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
46 | Marc Moonen |
Implementing the square-root information Kalman filter on a Jacobi-type systolic array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 8(3), pp. 283-291, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
46 | José L. Hueso, Gloria Martínez, Vicente Hernández |
A systolic algorithm for the triangular Stein equation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 5(1), pp. 49-55, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
46 | Tatyana D. Roziner, Mark G. Karpovsky |
Multidimensional fourier transforms by systolic architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 4(4), pp. 343-354, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
46 | Xiaoxiong Zhong, Sanjay V. Rajopadhye |
Deriving Fully Efficient Systolic Arrays by Quasi-Linear Allocation Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE (1) ![In: PARLE '91: Parallel Architectures and Languages Europe, Volume I: Parallel Architectures and Algorithms, Eindhoven, The Netherlands, June 10-13, 1991, Proceedings, pp. 219-236, 1991, Springer, 3-540-54151-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
46 | Norihiko Yoshida |
Transformational Derivation of Systolic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurrency: Theory, Language, And Architecture ![In: Concurrency: Theory, Language, And Architecture, UK/Japan Workshop, Oxford, UK, September 25-27, 1989, Proceedings, pp. 297-311, 1989, Springer, 3-540-53932-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
46 | Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero |
Systematic Hardware Adaptation of Systolic Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, Israel, June 1989, pp. 96-104, 1989, ACM, 0-89791-319-1. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
46 | Shek-Wayne Chan, Chin-Long Wey |
The design of concurrent error diagnosable systolic arrays for band matrix multiplications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1), pp. 21-37, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
46 | Anup B. Sharma, Keith R. Allen, Roy P. Pargas |
Some new systolic designs for two-dimensional convolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Conference on Computer Science ![In: Proceedings of the Sixteenth ACM Annual Conference on Computer Science, Atlanta, Georgia, USA, February 23-25, 1988, pp. 350-356, 1988, ACM, 0-89791-260-8. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
SAGE, SAGE |
46 | David Y. Y. Yun, Y. Yun, Chang Nian Zhang |
Formal verification of systolic networks using theorem proving techniques (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Conference on Computer Science ![In: Proceedings of the 15th ACM Annual Conference on Computer Science, St. Louis, Missouri, USA, February 16-19, 1987, pp. 362, 1987, ACM, 0-89791-218-7. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
46 | Chua-Huang Huang, Christian Lengauer |
An Implemented Method for Incremmental Systolic Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE (1) ![In: PARLE, Parallel Architectures and Languages Europe, Volume I: Parallel Architectures, Eindhoven, The Netherlands, June 15-19, 1987, Proceedings, pp. 160-177, 1987, Springer, 3-540-17943-7. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
46 | Yves Robert |
Systolic Algorithms for Path- Finding Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Automata Networks ![In: Automata Networks, LITP Spring School on Theoretical Computer Science, Angelès-Village, France, May 12-16, 1986, Proceedings, pp. 68-81, 1986, Springer, 3-540-19444-4. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
46 | A. A. Abdel Kader |
OCSAMO - A Systolic Array for Matrix Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: CONPAR 86: Conference on Algorithms and Hardware for Parallel Processing, Aachen, Germany, September 17-19, 1986, Proceedings, pp. 319-328, 1986, Springer, 3-540-16811-7. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
46 | Tudor Jebelean |
Design of a systolic coprocessor for rational addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 282-289, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
systolic coprocessor, rational addition, exact division, field programmable gate arrays, parallel architectures, systolic arrays, digital arithmetic, multiplication, addition, subtraction, rational numbers, GCD |
46 | Judith O. Berkey, Pearl Y. Wang |
A Systolic-Based Parallel Bin Packing Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(7), pp. 769-772, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
systolic-based parallel bin packing algorithm, asymptotic error bound, execution performance, serial algorithms, parallel algorithms, computational complexity, approximation algorithm, parallelizations, time complexity, systolic arrays, operations research |
46 | Peter R. Cappello |
A Processor-Time-Minimal Systolic Array for Cubical Mesh Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 3(1), pp. 4-13, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
hexagon shaped, cylinder connected, processor-time-minimal systolic array, cubical meshalgorithms, time-minimal multiprocessor schedules, processor-time-minimal scheduling, triangular shaped 2-D directed mesh, 2-D directed mesh, directedgraphs, parallel algorithms, computational complexity, topology, systolic arrays, directed acyclic graph, processing elements, matrix product |
46 | Christian Lengauer, Jingling Xue |
A systolic array for pyramidal algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 3(3), pp. 237-257, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
pyramid node linking, systolic design, image processing, image segmentation, systolic array |
42 | Sudhir Vinjamuri, Viktor K. Prasanna |
Hierarchical Dependency Graphs: Abstraction and Methodology for Mapping Systolic Array Designs to Multicore Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PaCT ![In: Parallel Computing Technologies, 10th International Conference, PaCT 2009, Novosibirsk, Russia, August 31-September 4, 2009. Proceedings, pp. 284-298, 2009, Springer, 978-3-642-03274-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
systolic array designs, parallel programming, high performance computing, multicore, dependency graphs |
42 | Chiou-Yng Lee, Che Wun Chiou |
New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2m) Under Polynomial Basis and Normal Basis Representations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(3), pp. 313-324, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
finite field, normal basis, polynomial basis, bit-parallel systolic multiplier |
42 | Kung Yao, Flavio Lorenzelli |
Systolic Algorithms and Architectures for High-Throughput Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(1-2), pp. 15-34, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
recursive least-squares estimation, Kalman filtering, systolic array, linear algebra, QR decomposition, least-squares estimation |
42 | Emina I. Milovanovic, Igor Z. Milovanovic, Michael P. Bekakos, I. N. Tselepis |
Computing all-pairs shortest paths on a linear systolic array and hardware realization on a reprogrammable FPGA platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 40(1), pp. 49-66, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA, Parallel computations, Systolic arrays, All-pairs shortest paths, Parallel iterative methods |
42 | Yunbi Chen, Jingsong He |
Using Systolic Technique to Accelerate an EHW Engine for Lossless Image Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings, pp. 433-444, 2007, Springer, 978-3-540-74625-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Image Compression, Systolic Array, Evolvable Hardware, Fitness Evaluation |
42 | Ting Qin, Haitao Zhang, Zonghai Chen, Wei Xiang |
Continuous CMAC-QRLS and Its Systolic Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Process. Lett. ![In: Neural Process. Lett. 22(1), pp. 1-16, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
CMAC-QRLS, systolic array, B-splines, QR decomposition |
42 | Amir K. Daneshbeh, M. Anwarul Hasan |
A Class of Unidirectional Bit Serial Systolic Architectures for Multiplicative Inversion and Division over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(3), pp. 370-380, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
field arithmetic, finite fields, systolic arrays, Division, inversion, extended Euclidean algorithm |
42 | Chiou-Yng Lee, Jenn-Shyong Horng, I-Chang Jou, Erl-Huei Lu |
Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(9), pp. 1061-1070, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
irreducible AOP, finite field, montgomery multiplication, irreducible trinomial, Bit-parallel systolic multiplier |
42 | A. Chorevas, Dionysios I. Reisis |
Efficient Systolic Array Mapping of FIR Filters Used in PAM-QAM Modulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 35(2), pp. 179-186, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
VLSI, FIR filter, systolic architectures, QAM |
42 | Sek M. Chai, D. Scott Wills |
Systolic Opportunities for Multidimensional Data Streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 13(4), pp. 388-398, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
area I/O, design and performance evaluation, systolic arrays, parallel computer architecture |
42 | J. H. Weston, Chang N. Zhang, Hua Li |
Some Space Considerations of VLSI Systolic Array Mappings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: Seventh International Conference on Parallel and Distributed Systems, ICPADS 2000, Iwate, Japan, July 4-7, 2000, pp. 375-381, 2000, IEEE Computer Society, 0-7695-0568-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
nested loop algorithm, systolic array, matrix, processing element, space-time mapping |
42 | Jean Frédéric Myoupo, Anne-Cécile Fabret |
A Modular Systolic Linearization of the Warshall-Floyd Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(5), pp. 449-455, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Modular linear systolic algorithms, shortest path, matrix multiplication, transitive closure |
42 | Noriaki Muranaka, Shigenobu Arai, Shigeru Imanishi, D. Michael Miller |
A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 92-97, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
neuron MOSFET, product sum computation, systolic array, Ternary logic |
42 | Yin Chan, Sun-Yuan Kung |
Bit Level Block Matching Systolic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 214-, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
bit level systolic array, video signal processing architecture, pipeline, block matching |
42 | Catherine Mongenet, Guy-René Perrin |
Synthesis of Systolic arrays for Inductive Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE (1) ![In: PARLE, Parallel Architectures and Languages Europe, Volume I: Parallel Architectures, Eindhoven, The Netherlands, June 15-19, 1987, Proceedings, pp. 260-277, 1987, Springer, 3-540-17943-7. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
synthesis, systolic arrays |
41 | I. M. Bland, Graham M. Megson |
The Systolic Array Genetic Algorithm, An Example of Systolic Arrays as a Reconfigurable Design Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, pp. 260-261, 1998, IEEE Computer Society, 0-8186-8900-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
38 | Lejla Batina, Geeke Muurling |
Montgomery in Practice: How to Do It More Efficiently in Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CT-RSA ![In: Topics in Cryptology - CT-RSA 2002, The Cryptographer's Track at the RSA Conference, 2002, San Jose, CA, USA, February 18-22, 2002, Proceedings, pp. 40-52, 2002, Springer, 3-540-43224-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
scalability, performance model, systolic array, Montgomery multiplication, modular exponentiation |
38 | Vera P. Behar, Christo A. Kabakchiev, Lyubka Doukovska |
Adaptive CFAR PI Processor for Radar Target Detection in Pulse Jamming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 26(3), pp. 383-396, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
CFAR API processor, detection in pulse jamming, target detection performance calculation, parallel algorithms, systolic architecture |
38 | J. G. Liu 0001, Francis H. Y. Chan, Francis K. Lam, Hon Fung Li |
A Novel Approach to Fast Discrete Hartley Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1999 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '99), 23-25 June 1999, Fremantle, Australia, pp. 178-183, 1999, IEEE Computer Society, 0-7695-0231-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Hartley transform, parallel processing, systolic array, moment, fast transform |
38 | Jean Frédéric Myoupo |
A Fully-Pipelined Solutions Constructor for Dynamic Programming Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCI ![In: Advances in Computing and Information - ICCI'91, International Conference on Computing and Information, Ottawa, Canada, May 27-29, 1991, Proceedings, pp. 421-430, 1991, Springer, 3-540-54029-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
Modular Arrays, Parallel Algorithms, Complexity, Dynamic Programming, Design of Algorithms, Linear Systolic Arrays |
38 | Alexandre Abellard, Patrick Abellard |
A Design Methodology of Systolic Architectures Based on a Petri Net Extension. Application to a Stereovision Hardware/Software Processing Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSEA ![In: Proceedings of the Third International Conference on Software Engineering Advances, ICSEA 2008, October 26-31, 2008, Sliema, Malta, pp. 77-82, 2008, IEEE Computer Society, 978-0-7695-3372-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | A. Neslin Ismailoglu, Murat Askar |
SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 566-571, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Laura Ruff |
Functional-Based Comparison between Two Special Classes of Uni- and Bidirectional Systolic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SYNASC ![In: Proceedings of the Ninth International Symposium on Symbolic and Numeric Algorithms for Scientific Computing, SYNASC 2007, Timisoara, Romania, September 26-29, 2007, pp. 51-58, 2007, IEEE Computer Society, 978-0-7695-3078-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
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