Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
116 | Ondrej Novák, Jiri Nosek |
On Using Deterministic Test Sets in BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 127-132, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
116 | Chen-Huan Chiang, Sandeep K. Gupta 0001 |
BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 376-383, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
113 | Chen-Huan Chiang, Sandeep K. Gupta 0001 |
BIST TPG for Combinational Cluster Interconnect Testing at Board Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 427-442, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
cluster testing, built-in self-test, BIST, boundary scan, interconnect testing |
109 | Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch |
An adjacency-based test pattern generator for low power BIST design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 459-464, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length |
106 | Dimitri Kagaris |
Built-In TPG with Designed Phaseshifts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 365-370, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Built-in Self-Test (BIST), Cellular Automata, Test Pattern Generation (TPG), Phase Shifters |
98 | Xiaowei Li 0001, Paul Y. S. Cheung, Hideo Fujiwara |
LFSR-Based Deterministic TPG for Two-Pattern Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 419-426, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
configurable LFSR, built-in self-test, path delay faults, two-pattern test |
91 | Dimitri Kagaris |
Multiple-Seed TPG Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(12), pp. 1633-1639, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Built-In Self-Test (BIST), Linear Feedback Shift Registers (LFSRs), Test Pattern Generation (TPG) |
87 | Abdessatar Abderrahman, Eduard Cerny, Bozena Kaminska |
CLP-based Multifrequency Test Generation for Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 158-165, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
72 | Emil Gizdarski, Hideo Fujiwara |
SPIRIT: a highly robust combinational test generation algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12), pp. 1446-1458, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
72 | Seongmoon Wang |
Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 834-843, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
69 | Seongmoon Wang |
A BIST TPG for Low Power Dissipation and High Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(7), pp. 777-789, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
69 | Dimitrios Kagaris, Spyros Tragoudas |
Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 42-47, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
67 | Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya |
Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 205-, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Built-in self-test, TPG, delay faults, robust testing, two-pattern tests |
64 | Sukanta Das, Anirban Kundu, Biplab K. Sikdar, Parimal Pal Chaudhuri |
Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(1), pp. 95-107, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
nonlinear CA, prohibited pattern set, TPG |
63 | Chen-Huan Chiang, Sandeep K. Gupta 0001 |
BIST TPG for SRAM cluster interconnect testing at board level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 58-65, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing |
58 | Dhiraj K. Pradhan, Chunsheng Liu |
EBIST: a novel test generator with built-in fault detection capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9), pp. 1457-1466, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
58 | Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri |
Generation of test patterns without prohibited pattern set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12), pp. 1650-1660, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
58 | Costas Laoudias, Dimitris Nikolos |
A new test pattern generator for high defect coverage in a BIST environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 417-420, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
built-in self test, stuck-at fault, path delay fault |
58 | Emil Gizdarski, Hideo Fujiwara |
Spirit: satisfiability problem implementation for redundancy identification and test generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 171-178, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Boolean satisfiability method, SPIRIT, ATPG system, logic testing, computability, automatic test pattern generation, combinational circuits, combinational circuits, test pattern generation, test sets |
58 | Karl Fuchs, Michael Pabst, Torsten Rössel |
RESIST: a recursive test pattern generation algorithm for path delay faults considering various test classes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(12), pp. 1550-1562, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
55 | Seongmoon Wang, Sandeep K. Gupta 0001 |
LT-RTPG: a new test-per-scan BIST TPG for low switching activity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8), pp. 1565-1574, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
55 | Seongmoon Wang, Sandeep K. Gupta 0001 |
DS-LFSR: a BIST TPG for low switching activity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7), pp. 842-851, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
52 | Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira 0001 |
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(2), pp. 179-187, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
fault modeling, DFT, TPG, RTL |
51 | Ehsan Atoofian, Zainalabedin Navabi |
A Test Approach for Look-Up Table Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 21(1), pp. 141-146, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
LUT testing, TPG with LE, BIST, memory testing, FPGA testing |
51 | Dimitri Kagaris |
Phase Shifter Merging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(2), pp. 161-168, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Built-in Self-Test (BIST), cellular automata, linear feedback shift registers, Test Pattern Generation (TPG), phase shifters |
51 | Dimitrios Kagaris |
A unified method for phase shifter computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(1), pp. 157-167, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
built-in self-test (BIST), cellular automata, linear feedback shift registers, Test pattern generation (TPG), linear finite state machines, phase shifters |
48 | Dimitri Kagaris, Spyros Tragoudas |
LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 233-244, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
built-in self-test (BIST), Linear Feedback Shift Registers (LFSR), test pattern generation (TPG) |
45 | M. H. Konijnenburg, Hans van der Linden, Ad J. van de Goor |
Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 185-191, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
sequential circuit TPG, back-jumping, conflict-directed backtrack, three-state (tri-state) circuit TPG, ATPG, cost estimates |
45 | Günter Kemnitz |
Synthesis of locally exhaustive test pattern generators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 440-447, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
locally exhaustive TPG, linear sum computation, TPG synthesis, logic testing, integrated circuit testing, automatic testing, test pattern generators |
43 | Bei Cao, Liyi Xiao, Yongsheng Wang |
A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 266-269, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Xiaoping Liu 0003, Hui Shi, Qiang Lu, Zhengqiang Mao |
Visual Task-driven Based on Task Precedence Graph for Collaborative Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSCWD ![In: Proceedings of the 11th International Conference on Computer Supported Cooperative Work in Design, CSCWD 2007, April 26-28, 2007, Melbourne, Australia, pp. 246-251, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Dhiraj K. Pradhan, Dimitri Kagaris, Rohit Gambhir |
A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 221-226, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Allon Adir, Eli Almog, Laurent Fournier, Eitan Marcus, Michal Rimon, Michael Vinov, Avi Ziv |
Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 21(2), pp. 84-93, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Marcelino B. Santos, José M. Fernandes, Isabel C. Teixeira, João Paulo Teixeira 0001 |
RTL Test Pattern Generation for High Quality Loosely Deterministic BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10994-10999, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
43 | Nan-Cheng Li, Sying-Jyan Wang |
A Reseeding Technique for LFSR-Based BIST Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 200-205, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Reseedling, LFST, BIST, Test Pattern Generator, Pseudo-Random Testing |
43 | Maciej Bellos, Dimitrios Kagaris, Dimitris Nikolos |
Test Set Embedding Based on Phase Shifters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Dependable Computing - EDCC-4, 4th European Dependable Computing Conference, Toulouse, France, October 23-25, 2002, Proceedings, pp. 90-101, 2002, Springer, 3-540-00012-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
43 | Dimitri Kagaris |
Built-in Generation of m -Sequences with Irreducible Characteristic Polynomials. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, pp. 158-, 2002, IEEE Computer Society, 0-7695-1641-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
43 | Biplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly |
Hierarchical Cellular Automata As An On-Chip Test Pattern Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 403-, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
43 | Abdessatar Abderrahman, Eduard Cerny, Bozena Kaminska |
Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(3), pp. 332-345, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
43 | Zohair Sahraoui, Francky Catthoor, Paul Six, Hugo De Man |
Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(3), pp. 217-238, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
supergate, prime-and-irredundant, ATPG, BDD |
43 | Hassan Ihs, Christian Dufaza |
Test synthesis for DC test of switched-capacitors circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 616, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
43 | Debesh Kumar Das, Susanta Chakraborty, Bhargab B. Bhattacharya |
New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 303-309, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
40 | Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira 0001, Marcelino B. Santos |
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 110-113, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
40 | Dimitrios Kagaris, Spyros Tragoudas |
LFSR/SR Pseudo-Exhaustive TPG in Fewer Test Cycles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 130-138, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
40 | Chih-Ang Chen, Sandeep K. Gupta |
Efficient BIST TPG design and test set compaction via input reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8), pp. 692-705, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
40 | Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia |
Pseudo-exhaustive built-in TPG for sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9), pp. 1160-1171, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
29 | Shantanu Dutt, Li Li |
Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 2(1), pp. 6:1-6:36, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
masking probability, parity groups, parity randomization, trust checking, trust-based design, FPGAs, Error-correcting codes |
29 | Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka |
Effective BIST for crosstalk faults in interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 164-169, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Martin Straka, Jiri Tobola, Zdenek Kotásek |
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 152-160, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Nan-Cheng Lai, Sying-Jyan Wang, Y.-H. Fu |
Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2586-2594, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Youbean Kim, Myung-Hoon Yang, Yong Lee 0002, Sungho Kang 0001 |
A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 230-235, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Abbas Tarhini, Hacène Fouchal, Nashat Mansour |
A Simple Approach for Testing Web Service Based Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IICS ![In: Innovative Internet Community Systems, 5th International Workshop, IICS 2005, Paris, France, June 20-22, 2005, Revised Papers, pp. 134-146, 2005, Springer, 3-540-33973-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
web service, verification, testing, web application, label transition systems |
29 | Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa |
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(1), pp. 109-122, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
test-per-clock testing, test pattern compression, zero aliasing error, built-in self test, test response compaction |
29 | Sukanta Das, Debdas Dey, Subhayan Sen, Biplab K. Sikdar, Parimal Pal Chaudhuri |
An efficient design of non-linear CA based PRPG for VLSI circuit testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 110-112, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Ehsan Atoofian, Zainalabedin Navabi |
A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 84-89, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian |
A Test Interface for Built-In Test of Non-Isolated Scanned Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 371-378, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Sukanta Das, Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri |
Design Of A Universal BIST (UBIST) Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 161-166, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Niloy Ganguly, Anindyasundar Nandi, Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri |
An Evolutionary Strategy To Design An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 260-265, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri |
Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 689-, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian |
Switching activity generation with automated BIST synthesis forperformance testing of interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9), pp. 1143-1158, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich |
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 306-311, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos |
Low Power BIST for Wallace Tree-Based Fast Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 433-438, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Testing, Low Power, BIST, Multipliers, Wallace Trees |
29 | Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou |
Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 121-129, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Modified Booth Multipliers, Low Power, Built In Self Test, VLSI Testing |
29 | Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch |
An optimized BIST test pattern generator for delay testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 94-100, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
BIST test pattern generator, robust delay fault coverage, single input change test sequence, compatible inputs, optimization, delays, built-in self-test, fault detection, delay testing, test length, area overhead, circuit under test |
29 | Karl Fuchs |
Synthesis for path delay fault testability via tautology-based untestability identification and factorization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12), pp. 1470-1479, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
29 | Shambhu J. Upadhyaya, Kewal K. Saluja |
A new approach to the design of built-in self-testing PLAs for high fault coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1), pp. 60-67, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
26 | Xiaochao Dang 0001, Wenze Ke, Zhanjun Hao 0001, Peng Jin, Han Deng, Ying Sheng 0009 |
mm-TPG: Traffic Policemen Gesture Recognition Based on Millimeter Wave Radar Point Cloud. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 23(15), pp. 6816, August 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Nicolas Sourbier, Justine Bonnot, Frédéric Majorczyk, Olivier Gesny, Thomas Guyet, Maxime Pelcat |
Imbalanced classification with tpg genetic programming: impact of problem imbalance and selection mechanisms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO Companion ![In: GECCO '22: Genetic and Evolutionary Computation Conference, Companion Volume, Boston, Massachusetts, USA, July 9 - 13, 2022, pp. 608-611, 2022, ACM, 978-1-4503-9268-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Lucas B. Zilch, Állan G. Ferreira, Marcelo Soares Lubaszewski, Tiago R. Balen |
Evaluating Fault Coverage of Structural and Specification-based Tests Obtained With a Low-Cost Analog TPG Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 23rd IEEE Latin American Test Symposium, LATS 2022, Montevideo, Uruguay, September 5-8, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-5707-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Jingxing Jiang, Zhubin Wang, Fei Fang 0002, Binqiang Zhao |
TPG-DNN: A Method for User Intent Prediction Based on Total Probability Formula and GRU Loss with Multi-task Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2008.02122, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
26 | Louis Y.-Z. Lin, Charles Chia-Hao Hsu, Charles H.-P. Wen |
P4-TPG: Accelerating Deterministic Parallel Test Pattern Generation by Preemptive, Proactive, and Preventive Schedulings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 6816-6830, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
26 | G. Naveen Balaji, S. Chenthur Pandian |
Design of test pattern generator (TPG) by an optimized low power design for testability (DFT) for scan BIST circuits using transmission gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Clust. Comput. ![In: Clust. Comput. 22(6), pp. 15231-15244, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
26 | Yuan Yuan 0007, Jingtao Sun, Miaohui Wang |
Dilated Deep Residual Network for Post-processing in TPG Based Image Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IDCS ![In: Internet and Distributed Computing Systems - 11th International Conference, IDCS 2018, Tokyo, Japan, October 11-13, 2018, Proceedings, pp. 293-297, 2018, Springer, 978-3-030-02737-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Pascal Raiola, Jan Burchard, Felix Neubauer, Dominik Erb, Bernd Becker 0001 |
Evaluating the Effectiveness of D-chains in SAT-based ATPG and Diagnostic TPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 33(6), pp. 751-767, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
26 | Haiying Yuan, Kun Guo, Xun Sun, Jiaping Mei, Hongying Song |
A Power Efficient BIST TPG Method on Don't Care Bit Based 2-D Adjusting and Hamming Distance Based 2-D Reordering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 31(1), pp. 43-52, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier |
TPG for Crosstalk Faults between On-Chip Aggressor and Victim Using Genetic Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015, pp. 3-8, 2015, IEEE Computer Society, 978-1-4799-6779-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Abdallatif S. Abu-Issa, Iyad K. Tumar, Wasel T. Ghanem |
SR-TPG: A low transition test pattern generator for test-per-clock and test-per-scan BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IDT ![In: 10th International Design & Test Symposium, IDT 2015, Dead Sea, Amman, Jordan, December 14-16, 2015, pp. 124-128, 2015, IEEE, 978-1-4673-9994-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Chun-Hao Chang, Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang |
SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015, pp. 43-48, 2015, IEEE Computer Society, 978-1-4673-9739-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
26 | N. Palermo, Valentin Tihhomirov, Thiago Santos Copetti, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Marco Gaudesi, Giovanni Squillero, Matteo Sonza Reorda, Fabian Vargas 0001, Letícia Maria Bolzani Pöhls |
Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 16th Latin-American Test Symposium, LATS 2015, Puerto Vallarta, Mexico, March 25-27, 2015, pp. 1-6, 2015, IEEE Computer Society, 978-1-4673-6710-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Ioannis Voyiatzis, Costas Efstathiou |
Accumulator-based generation for serial TPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Panhellenic Conference on Informatics ![In: Proceedings of the 19th Panhellenic Conference on Informatics, PCI 2015, Athens, Greece, October 1-3, 2015, pp. 426-430, 2015, ACM, 978-1-4503-3551-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Aiwu Ruan, Shi Kang, Yu Wang, Xiao Han, Zujian Zhu, Yongbo Liao, Peng Li |
A Built-In Self-Test (BIST) system with non-intrusive TPG and ORA for FPGA test and diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 53(3), pp. 488-498, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
26 | Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou |
Embedding test vectors in accumulator - based TPG using progressive search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2013, 26-28 March, 2013, Abu Dhabi, UAE, pp. 169-170, 2013, IEEE, 978-1-4673-6038-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
26 | Oscar Acevedo, Dimitri Kagaris |
Using the Berlekamp-Massey algorithm to obtain LFSR characteristic polynomials for TPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012, pp. 233-238, 2012, IEEE Computer Society, 978-1-4673-3043-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
26 | Karim Yehia, Mona Safar, Hassan A. Youness, Mohamed Abdelsalam, Ashraf Salem |
A novel approach for system level synthesis of multi-core system architectures from TPG models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICCSA ![In: The 9th IEEE/ACS International Conference on Computer Systems and Applications, AICCSA 2011, Sharm El-Sheikh, Egypt, December 27-30, 2011, pp. 268-275, 2011, IEEE Computer Society, 978-1-4577-0475-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Cleonilson Protásio de Souza, Francisco Marcos de Assis, Raimundo Carlos Silvério Freire |
A New Built-in TPG Based on Berlekamp-Massey Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 26(4), pp. 443-451, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
26 | Samara Sudireddy, Jayawant Kakade, Dimitri Kagaris |
Deterministic Built-in TPG with Segmented FSMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 7-9 July 2008, Rhodes, Greece, pp. 261-266, 2008, IEEE Computer Society, 978-0-7695-3264-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Dimitrios Kagaris, P. Karpodinis, Dimitris Nikolos |
On Obtaining Maximum-Length Sequences for Accumulator-Based Serial TPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2578-2586, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri |
Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 331-334, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell |
High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), 28-30 January 2004, Perth, Australia, pp. 83-88, 2004, IEEE Computer Society, 0-7695-2081-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Alessandro Fin, Franco Fummi |
Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG? ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Eighth IEEE International High-Level Design Validation and Test Workshop 2003, San Francisco, CA, USA, November 12-14, 2003, pp. 163-168, 2003, IEEE Computer Society, 0-7803-8236-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Alessandro Fin, Franco Fummi |
LAERTE++: an Object Oriented High-level TPG for SystemC Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on specification and Design Languages, FDL 2003, September 23-26, 2003, Frankfurt, Germany, Proceedings, pp. 658-668, 2003, ECSI. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
26 | Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas |
A new built-in TPG method for circuits with random patternresistant faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7), pp. 859-866, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Volker Meyer, Walter Anheier, Arne Sticht |
Non-robust delay test pattern generation based on stuck-at TPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001, pp. 1007-1010, 2001, IEEE, 0-7803-7057-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Xiaowei Li 0001, Paul Y. S. Cheung |
Exploiting Deterministic TPG for Path Delay Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 15(5), pp. 472-479, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Wenyi Feng, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi |
A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 95-100, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Silvia Chiusano, Fulvio Corno, Paolo Prinetto |
RT-level TPG Exploiting High-Level Synthesis Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 341-353, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Seongmoon Wang, Sandeep K. Gupta 0001 |
LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1999, Atlantic City, NJ, USA, 27-30 September 1999, pp. 85-94, 1999, IEEE Computer Society, 0-7803-5753-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Chen-Huan Chiang, Sandeep K. Gupta 0001 |
BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 244-252, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
26 | Chih-Ang Chen, Sandeep K. Gupta |
Efficient BIST TPG design and test set compaction for delay testing via input reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1998, Proceedings, 5-7 October, 1998, Austin, TX, USA, pp. 32-39, 1998, IEEE Computer Society, 0-8186-9099-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
26 | Chen-Huan Chiang, Sandeep K. Gupta 0001 |
BIST TPG for faults in system backplanes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 406-413, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
BIST circuit, BIST methodology, VME backplane, edge pin connections, programmable test architecture, simple test schedule, system backplanes, built-in self test, built-in self-test, system configuration |