Search results for "TPG"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
116	Ondrej Novák, Jiri Nosek	On Using Deterministic Test Sets in BIST.	IOLTW	2000	DBLP DOI BibTeX RDF
116	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPGs for Faults in Board Level Interconnect via Boundary Scan.	VTS	1997	DBLP DOI BibTeX RDF
113	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for Combinational Cluster Interconnect Testing at Board Level.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	cluster testing, built-in self-test, BIST, boundary scan, interconnect testing
109	Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	An adjacency-based test pattern generator for low power BIST design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length
106	Dimitri Kagaris	Built-In TPG with Designed Phaseshifts.	VTS	2003	DBLP DOI BibTeX RDF	Built-in Self-Test (BIST), Cellular Automata, Test Pattern Generation (TPG), Phase Shifters
98	Xiaowei Li 0001, Paul Y. S. Cheung, Hideo Fujiwara	LFSR-Based Deterministic TPG for Two-Pattern Testing.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	configurable LFSR, built-in self-test, path delay faults, two-pattern test
91	Dimitri Kagaris	Multiple-Seed TPG Structures.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Built-In Self-Test (BIST), Linear Feedback Shift Registers (LFSRs), Test Pattern Generation (TPG)
87	Abdessatar Abderrahman, Eduard Cerny, Bozena Kaminska	CLP-based Multifrequency Test Generation for Analog Circuits.	VTS	1997	DBLP DOI BibTeX RDF
72	Emil Gizdarski, Hideo Fujiwara	SPIRIT: a highly robust combinational test generation algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
72	Seongmoon Wang	Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST.	ITC	2002	DBLP DOI BibTeX RDF
69	Seongmoon Wang	A BIST TPG for Low Power Dissipation and High Fault Coverage.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
69	Dimitrios Kagaris, Spyros Tragoudas	Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds.	ICCD	2000	DBLP DOI BibTeX RDF
67	Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya	Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults.	VLSI Design	1998	DBLP DOI BibTeX RDF	Built-in self-test, TPG, delay faults, robust testing, two-pattern tests
64	Sukanta Das, Anirban Kundu, Biplab K. Sikdar, Parimal Pal Chaudhuri	Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	nonlinear CA, prohibited pattern set, TPG
63	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for SRAM cluster interconnect testing at board level.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
58	Dhiraj K. Pradhan, Chunsheng Liu	EBIST: a novel test generator with built-in fault detection capability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
58	Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri	Generation of test patterns without prohibited pattern set.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
58	Costas Laoudias, Dimitris Nikolos	A new test pattern generator for high defect coverage in a BIST environment.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	built-in self test, stuck-at fault, path delay fault
58	Emil Gizdarski, Hideo Fujiwara	Spirit: satisfiability problem implementation for redundancy identification and test generation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Boolean satisfiability method, SPIRIT, ATPG system, logic testing, computability, automatic test pattern generation, combinational circuits, combinational circuits, test pattern generation, test sets
58	Karl Fuchs, Michael Pabst, Torsten Rössel	RESIST: a recursive test pattern generation algorithm for path delay faults considering various test classes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
55	Seongmoon Wang, Sandeep K. Gupta 0001	LT-RTPG: a new test-per-scan BIST TPG for low switching activity.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
55	Seongmoon Wang, Sandeep K. Gupta 0001	DS-LFSR: a BIST TPG for low switching activity.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
52	Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira 0001	RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	fault modeling, DFT, TPG, RTL
51	Ehsan Atoofian, Zainalabedin Navabi	A Test Approach for Look-Up Table Based FPGAs.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	LUT testing, TPG with LE, BIST, memory testing, FPGA testing
51	Dimitri Kagaris	Phase Shifter Merging.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	Built-in Self-Test (BIST), cellular automata, linear feedback shift registers, Test Pattern Generation (TPG), phase shifters
51	Dimitrios Kagaris	A unified method for phase shifter computation.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	built-in self-test (BIST), cellular automata, linear feedback shift registers, Test pattern generation (TPG), linear finite state machines, phase shifters
48	Dimitri Kagaris, Spyros Tragoudas	LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	built-in self-test (BIST), Linear Feedback Shift Registers (LFSR), test pattern generation (TPG)
45	M. H. Konijnenburg, Hans van der Linden, Ad J. van de Goor	Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test Generation.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	sequential circuit TPG, back-jumping, conflict-directed backtrack, three-state (tri-state) circuit TPG, ATPG, cost estimates
45	Günter Kemnitz	Synthesis of locally exhaustive test pattern generators.	VTS	1995	DBLP DOI BibTeX RDF	locally exhaustive TPG, linear sum computation, TPG synthesis, logic testing, integrated circuit testing, automatic testing, test pattern generators
43	Bei Cao, Liyi Xiao, Yongsheng Wang	A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata.	DELTA	2008	DBLP DOI BibTeX RDF
43	Xiaoping Liu 0003, Hui Shi, Qiang Lu, Zhengqiang Mao	Visual Task-driven Based on Task Precedence Graph for Collaborative Design.	CSCWD	2007	DBLP DOI BibTeX RDF
43	Dhiraj K. Pradhan, Dimitri Kagaris, Rohit Gambhir	A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage.	IOLTS	2005	DBLP DOI BibTeX RDF
43	Allon Adir, Eli Almog, Laurent Fournier, Eitan Marcus, Michal Rimon, Michael Vinov, Avi Ziv	Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
43	Marcelino B. Santos, José M. Fernandes, Isabel C. Teixeira, João Paulo Teixeira 0001	RTL Test Pattern Generation for High Quality Loosely Deterministic BIST.	DATE	2003	DBLP DOI BibTeX RDF
43	Nan-Cheng Li, Sying-Jyan Wang	A Reseeding Technique for LFSR-Based BIST Applications.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	Reseedling, LFST, BIST, Test Pattern Generator, Pseudo-Random Testing
43	Maciej Bellos, Dimitrios Kagaris, Dimitris Nikolos	Test Set Embedding Based on Phase Shifters.	EDCC	2002	DBLP DOI BibTeX RDF
43	Dimitri Kagaris	Built-in Generation of m -Sequences with Irreducible Characteristic Polynomials.	IOLTW	2002	DBLP DOI BibTeX RDF
43	Biplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly	Hierarchical Cellular Automata As An On-Chip Test Pattern Generator.	VLSI Design	2001	DBLP DOI BibTeX RDF
43	Abdessatar Abderrahman, Eduard Cerny, Bozena Kaminska	Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
43	Zohair Sahraoui, Francky Catthoor, Paul Six, Hugo De Man	Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	supergate, prime-and-irredundant, ATPG, BDD
43	Hassan Ihs, Christian Dufaza	Test synthesis for DC test of switched-capacitors circuits.	ED&TC	1997	DBLP DOI BibTeX RDF
43	Debesh Kumar Das, Susanta Chakraborty, Bhargab B. Bhattacharya	New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults.	VLSI Design	1997	DBLP DOI BibTeX RDF
40	Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira 0001, Marcelino B. Santos	Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
40	Dimitrios Kagaris, Spyros Tragoudas	LFSR/SR Pseudo-Exhaustive TPG in Fewer Test Cycles.	DFT	1999	DBLP DOI BibTeX RDF
40	Chih-Ang Chen, Sandeep K. Gupta	Efficient BIST TPG design and test set compaction via input reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
40	Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia	Pseudo-exhaustive built-in TPG for sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
29	Shantanu Dutt, Li Li	Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	masking probability, parity groups, parity randomization, trust checking, trust-based design, FPGAs, Error-correcting codes
29	Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka	Effective BIST for crosstalk faults in interconnects.	DDECS	2009	DBLP DOI BibTeX RDF
29	Martin Straka, Jiri Tobola, Zdenek Kotásek	Checker Design for On-line Testing of Xilinx FPGA Communication Protocols.	DFT	2007	DBLP DOI BibTeX RDF
29	Nan-Cheng Lai, Sying-Jyan Wang, Y.-H. Fu	Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
29	Youbean Kim, Myung-Hoon Yang, Yong Lee 0002, Sungho Kang 0001	A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
29	Abbas Tarhini, Hacène Fouchal, Nashat Mansour	A Simple Approach for Testing Web Service Based Applications.	IICS	2005	DBLP DOI BibTeX RDF	web service, verification, testing, web application, label transition systems
29	Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa	Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	test-per-clock testing, test pattern compression, zero aliasing error, built-in self test, test response compaction
29	Sukanta Das, Debdas Dey, Subhayan Sen, Biplab K. Sikdar, Parimal Pal Chaudhuri	An efficient design of non-linear CA based PRPG for VLSI circuit testing.	ASP-DAC	2004	DBLP DOI BibTeX RDF
29	Ehsan Atoofian, Zainalabedin Navabi	A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
29	Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian	A Test Interface for Built-In Test of Non-Isolated Scanned Cores.	VTS	2003	DBLP DOI BibTeX RDF
29	Sukanta Das, Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri	Design Of A Universal BIST (UBIST) Structure.	VLSI Design	2003	DBLP DOI BibTeX RDF
29	Niloy Ganguly, Anindyasundar Nandi, Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri	An Evolutionary Strategy To Design An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS).	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
29	Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri	Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS).	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
29	Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian	Switching activity generation with automated BIST synthesis forperformance testing of interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
29	Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich	A Modified Clock Scheme for a Low Power BIST Test Pattern Generator.	VTS	2001	DBLP DOI BibTeX RDF
29	Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos	Low Power BIST for Wallace Tree-Based Fast Multipliers.	ISQED	2000	DBLP DOI BibTeX RDF	Testing, Low Power, BIST, Multipliers, Wallace Trees
29	Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou	Low Power Dissipation in BIST Schemes for Modified Booth Multipliers.	DFT	1999	DBLP DOI BibTeX RDF	Modified Booth Multipliers, Low Power, Built In Self Test, VLSI Testing
29	Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch	An optimized BIST test pattern generator for delay testing.	VTS	1997	DBLP DOI BibTeX RDF	BIST test pattern generator, robust delay fault coverage, single input change test sequence, compatible inputs, optimization, delays, built-in self-test, fault detection, delay testing, test length, area overhead, circuit under test
29	Karl Fuchs	Synthesis for path delay fault testability via tautology-based untestability identification and factorization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
29	Shambhu J. Upadhyaya, Kewal K. Saluja	A new approach to the design of built-in self-testing PLAs for high fault coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
26	Xiaochao Dang 0001, Wenze Ke, Zhanjun Hao 0001, Peng Jin, Han Deng, Ying Sheng 0009	mm-TPG: Traffic Policemen Gesture Recognition Based on Millimeter Wave Radar Point Cloud.	Sensors	2023	DBLP DOI BibTeX RDF
26	Nicolas Sourbier, Justine Bonnot, Frédéric Majorczyk, Olivier Gesny, Thomas Guyet, Maxime Pelcat	Imbalanced classification with tpg genetic programming: impact of problem imbalance and selection mechanisms.	GECCO Companion	2022	DBLP DOI BibTeX RDF
26	Lucas B. Zilch, Állan G. Ferreira, Marcelo Soares Lubaszewski, Tiago R. Balen	Evaluating Fault Coverage of Structural and Specification-based Tests Obtained With a Low-Cost Analog TPG Tool.	LATS	2022	DBLP DOI BibTeX RDF
26	Jingxing Jiang, Zhubin Wang, Fei Fang 0002, Binqiang Zhao	TPG-DNN: A Method for User Intent Prediction Based on Total Probability Formula and GRU Loss with Multi-task Learning.	CoRR	2020	DBLP BibTeX RDF
26	Louis Y.-Z. Lin, Charles Chia-Hao Hsu, Charles H.-P. Wen	P4-TPG: Accelerating Deterministic Parallel Test Pattern Generation by Preemptive, Proactive, and Preventive Schedulings.	IEEE Access	2019	DBLP DOI BibTeX RDF
26	G. Naveen Balaji, S. Chenthur Pandian	Design of test pattern generator (TPG) by an optimized low power design for testability (DFT) for scan BIST circuits using transmission gates.	Clust. Comput.	2019	DBLP DOI BibTeX RDF
26	Yuan Yuan 0007, Jingtao Sun, Miaohui Wang	Dilated Deep Residual Network for Post-processing in TPG Based Image Coding.	IDCS	2018	DBLP DOI BibTeX RDF
26	Pascal Raiola, Jan Burchard, Felix Neubauer, Dominik Erb, Bernd Becker 0001	Evaluating the Effectiveness of D-chains in SAT-based ATPG and Diagnostic TPG.	J. Electron. Test.	2017	DBLP DOI BibTeX RDF
26	Haiying Yuan, Kun Guo, Xun Sun, Jiaping Mei, Hongying Song	A Power Efficient BIST TPG Method on Don't Care Bit Based 2-D Adjusting and Hamming Distance Based 2-D Reordering.	J. Electron. Test.	2015	DBLP DOI BibTeX RDF
26	Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier	TPG for Crosstalk Faults between On-Chip Aggressor and Victim Using Genetic Algorithms.	DDECS	2015	DBLP DOI BibTeX RDF
26	Abdallatif S. Abu-Issa, Iyad K. Tumar, Wasel T. Ghanem	SR-TPG: A low transition test pattern generator for test-per-clock and test-per-scan BIST.	IDT	2015	DBLP DOI BibTeX RDF
26	Chun-Hao Chang, Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang	SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator.	ATS	2015	DBLP DOI BibTeX RDF
26	N. Palermo, Valentin Tihhomirov, Thiago Santos Copetti, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Marco Gaudesi, Giovanni Squillero, Matteo Sonza Reorda, Fabian Vargas 0001, Letícia Maria Bolzani Pöhls	Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG.	LATS	2015	DBLP DOI BibTeX RDF
26	Ioannis Voyiatzis, Costas Efstathiou	Accumulator-based generation for serial TPG.	Panhellenic Conference on Informatics	2015	DBLP DOI BibTeX RDF
26	Aiwu Ruan, Shi Kang, Yu Wang, Xiao Han, Zujian Zhu, Yongbo Liao, Peng Li	A Built-In Self-Test (BIST) system with non-intrusive TPG and ORA for FPGA test and diagnosis.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
26	Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou	Embedding test vectors in accumulator - based TPG using progressive search.	DTIS	2013	DBLP DOI BibTeX RDF
26	Oscar Acevedo, Dimitri Kagaris	Using the Berlekamp-Massey algorithm to obtain LFSR characteristic polynomials for TPG.	DFT	2012	DBLP DOI BibTeX RDF
26	Karim Yehia, Mona Safar, Hassan A. Youness, Mohamed Abdelsalam, Ashraf Salem	A novel approach for system level synthesis of multi-core system architectures from TPG models.	AICCSA	2011	DBLP DOI BibTeX RDF
26	Cleonilson Protásio de Souza, Francisco Marcos de Assis, Raimundo Carlos Silvério Freire	A New Built-in TPG Based on Berlekamp-Massey Algorithm.	J. Electron. Test.	2010	DBLP DOI BibTeX RDF
26	Samara Sudireddy, Jayawant Kakade, Dimitri Kagaris	Deterministic Built-in TPG with Segmented FSMs.	IOLTS	2008	DBLP DOI BibTeX RDF
26	Dimitrios Kagaris, P. Karpodinis, Dimitris Nikolos	On Obtaining Maximum-Length Sequences for Accumulator-Based Serial TPG.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
26	Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri	Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
26	Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	High Quality TPG for Delay Faults in Look-Up Tables of FPGAs.	DELTA	2004	DBLP DOI BibTeX RDF
26	Alessandro Fin, Franco Fummi	Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?	HLDVT	2003	DBLP DOI BibTeX RDF
26	Alessandro Fin, Franco Fummi	LAERTE++: an Object Oriented High-level TPG for SystemC Designs.	FDL	2003	DBLP BibTeX RDF
26	Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas	A new built-in TPG method for circuits with random patternresistant faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
26	Volker Meyer, Walter Anheier, Arne Sticht	Non-robust delay test pattern generation based on stuck-at TPG.	ICECS	2001	DBLP DOI BibTeX RDF
26	Xiaowei Li 0001, Paul Y. S. Cheung	Exploiting Deterministic TPG for Path Delay Testing.	J. Comput. Sci. Technol.	2000	DBLP DOI BibTeX RDF
26	Wenyi Feng, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi	A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
26	Silvia Chiusano, Fulvio Corno, Paolo Prinetto	RT-level TPG Exploiting High-Level Synthesis Information.	VTS	1999	DBLP DOI BibTeX RDF
26	Seongmoon Wang, Sandeep K. Gupta 0001	LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation.	ITC	1999	DBLP DOI BibTeX RDF
26	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
26	Chih-Ang Chen, Sandeep K. Gupta	Efficient BIST TPG design and test set compaction for delay testing via input reduction.	ICCD	1998	DBLP DOI BibTeX RDF
26	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for faults in system backplanes.	ICCAD	1997	DBLP DOI BibTeX RDF	BIST circuit, BIST methodology, VME backplane, edge pin connections, programmable test architecture, simple test schedule, system backplanes, built-in self test, built-in self-test, system configuration