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Publication years (Num. hits)
1973-1985 (16) 1986-1987 (16) 1988-1989 (21) 1990 (16) 1991-1992 (19) 1993-1994 (23) 1995 (21) 1996-1997 (33) 1998 (28) 1999 (34) 2000 (39) 2001 (44) 2002 (70) 2003 (99) 2004 (110) 2005 (136) 2006 (123) 2007 (125) 2008 (112) 2009 (72) 2010 (36) 2011 (65) 2012 (55) 2013 (45) 2014 (44) 2015 (38) 2016 (30) 2017 (43) 2018 (73) 2019 (73) 2020 (77) 2021 (54) 2022 (74) 2023 (63) 2024 (24)
Publication types (Num. hits)
article(938) incollection(5) inproceedings(1005) phdthesis(2) proceedings(1)
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Found 1954 publication records. Showing 1951 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
86Valeriu Beiu, Walid Ibrahim, Rafic Z. Makki On Wires Holding a Handful of Electrons. Search on Bibsonomy NanoNet The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Nano-electronics, interconnects (wires), noise (intrinsic), reliability, communication
77Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska Postlayout logic restructuring using alternative wires. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
70Saroj K. Nayak Carbon nanotube, graphene and atomic wires as next generation interconnects: current status and future promise. Search on Bibsonomy SLIP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF quantum simulation, performance, design, reliability
64Michal Koucký 0001, Pavel Pudlák, Denis Thérien Bounded-depth circuits: separating wires from gates. Search on Bibsonomy STOC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF communication, complexity, lower bounds, regular languages, wires, constant-depth circuits, gates
62Shih-Chieh Chang, Jung-Cheng Chuang, Zhong-Zhen Wu Synthesis for multiple input wires replacement of a gate for wiring consideration. Search on Bibsonomy ICCAD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
62Jonathan Babb, Russell Tessier, Matthew Dahl, Silvina Hanono, David M. Hoki, Anant Agarwal Logic emulation with virtual wires. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
55Edmund Lee 0002, Guy Lemieux, Shahriar Mirabbasi Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF routing design, FPGA, computer-aided design, interconnect design, FPGA interconnect
55Kenichi Shinkai, Masanori Hashimoto, Takao Onoye Future Prediction of Self-Heating in Short Intra-Block Wires. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
55Ron Ho, Jonathan Gainsley, Robert J. Drost Long Wires and Asynchronous Control. Search on Bibsonomy ASYNC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
54Avinoam Kolodny Networks on chips: keeping up with Rent's rule and Moore's law. Search on Bibsonomy SLIP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF routing, timing, interconnect, power, on-chip network, wires
53Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz Interconnect scaling implications for CAD. Search on Bibsonomy ICCAD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
47Sobeeh Almukhaizim, Yiorgos Makris Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires. Search on Bibsonomy IEEE Trans. Reliab. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
47Po-Hao Chang, Jia-Ming Chen, Chao-Ying Shen On an Efficient Closed Form Expression to Estimate the Crosstalk Noise in the Circuit with Multiple Wires. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
47Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz, Dean Copsey, Frederic T. Chong, Isaac L. Chuang, Mark Oskin Datapath and control for quantum wires. Search on Bibsonomy ACM Trans. Archit. Code Optim. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Architecture, Control, Layout
45Yung-Chih Chen, Chun-Yao Wang An Improved Approach for AlternativeWires Identi.cation. Search on Bibsonomy ICCD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
45Christian A. Duncan, Alon Efrat, Stephen G. Kobourov, Carola Wenk Drawing with Fat Edges. Search on Bibsonomy GD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
45Shinichiro Haruyama, Martin D. F. Wong, Donald S. Fussell Topological channel routing [VLSI]. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
41Sandro Carrara, Cristina Boero, Giovanni De Micheli Quantum Dots and Wires to Improve Enzymes-Based Electrochemical Bio-sensing. Search on Bibsonomy NanoNet The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Quantum Wires, Gold Nano-Particles, Oxidases, Cytochromes, Electrochemical detection, Carbon Nanotubes, Quantum Dots
40Hitoshi Kino, Toshiaki Yahiro, Fumiaki Takemura, Tetsuya Morizono Robust PD Control Using Adaptive Compensation for Completely Restrained Parallel-Wire Driven Robots: Translational Systems Using the Minimum Number of Wires Under Zero-Gravity Condition. Search on Bibsonomy IEEE Trans. Robotics The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
40Hisashi Osumi, Masayuki Saitoh Control of a Redundant Manipulator Mounted on a Base Plate Suspended by Six Wires. Search on Bibsonomy IROS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Hua Xiang 0001, I-Min Liu, Martin D. F. Wong Wire Planning with Bounded Over-the-Block Wires. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF over-the-block, wire planning, routing
40Vijaya Ramachandran On driving many long wires in a VLSI layout. Search on Bibsonomy J. ACM The full citation details ... 1986 DBLP  DOI  BibTeX  RDF
39Crispín Gómez Requena, María Engracia Gómez, Pedro López 0001, José Duato Exploiting Wiring Resources on Interconnection Network: Increasing Path Diversity. Search on Bibsonomy PDP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF SDM, Spatial Division Multiplexing, parallel links, Networks on chip, NoCs, Wiring, Wires
39Charbel J. Akl, Magdy A. Bayoumi Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater count. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF high-speed signaling, repeater, wires
38Mackenzie R. Scott, Rajeevan Amirtharajah Pulse width modulation for reduced peak power full-swing on-chip interconnect. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF low power interconnect, peak power, pulse width modulation
38Eric Rachlin, John E. Savage Analysis of Mask-Based Nanowire Decoders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Hardware, Stochastic processes, Emerging technologies, Miscellaneous
38Daniele Rossi 0001, André K. Nieuwland, Cecilia Metra Simultaneous Switching Noise: The Relation between Bus Layout and Coding. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF bus layout, switching patterns, system reliability, IC, power supply network, simultaneous switching noise, coding techniques
38Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF reliability, global routing, thermal
38Eric Rachlin, John E. Savage, Benjamin Gojman Analysis of a Mask-Based Nanowire Decoder. Search on Bibsonomy ISVLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
38Hao Yu 0001, Lei He 0001 Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
38Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar Microarchitecture-aware floorplanning using a statistical design of experiments approach. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF floorplanning, microarchitecture, wire pipelining
38Li-Da Huang, Xiaoping Tang, Hua Xiang 0001, Martin D. F. Wong, I-Min Liu A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
38Maurice Herlihy, Srikanta Tirthapura Randomized Smoothing Networks. Search on Bibsonomy IPDPS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
38Maurice Herlihy, Srikanta Tirthapura Self-Stabilizing Smoothing and Counting Maurice Herlihy, Srikanta Tirthapura. Search on Bibsonomy ICDCS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
38Li-Da Huang, Xiaoping Tang, Hua Xiang 0001, D. F. Wong 0001, I-Min Liu A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. Search on Bibsonomy DATE The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Zhan Chen, Fook-Luen Heng A Fast Minimum Layout Perturbation Algorithm for Electromigration Reliability Enhancement. Search on Bibsonomy DFT The full citation details ... 1998 DBLP  DOI  BibTeX  RDF layout compaction, design for reliability, electromigration
36Alexander Wires Complexity in Young's lattice. Search on Bibsonomy Ann. Pure Appl. Log. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
36Jake Wires, Andrew Warfield Mirador: An Active Control Plane for Datacenter Storage. Search on Bibsonomy FAST The full citation details ... 2017 DBLP  BibTeX  RDF
36Mihir Nanavati, Jake Wires, Andrew Warfield Decibel: Isolation and Sharing in Disaggregated Rack-Scale Storage. Search on Bibsonomy NSDI The full citation details ... 2017 DBLP  BibTeX  RDF
36Jake Wires, Pradeep Ganesan, Andrew Warfield Sketches of space: ownership accounting for shared storage. Search on Bibsonomy SoCC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
36Alexander Wires On finite Taylor algebras. Search on Bibsonomy Int. J. Algebra Comput. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
36Mihir Nanavati, Malte Schwarzkopf, Jake Wires, Andrew Warfield Non-volatile storage. Search on Bibsonomy Commun. ACM The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
36Jake Wires, Stephen Ingram, Zachary Drudi, Nicholas J. A. Harvey, Andrew Warfield Counter Stacks and the Elusive Working Set. Search on Bibsonomy login Usenix Mag. The full citation details ... 2015 DBLP  BibTeX  RDF
36Alexander Wires Dichotomy for finite tournaments of mixed-type. Search on Bibsonomy Discret. Math. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
36Mihir Nanavati, Malte Schwarzkopf, Jake Wires, Andrew Warfield Non-volatile Storage. Search on Bibsonomy ACM Queue The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
36Zachary Drudi, Nicholas J. A. Harvey, Stephen Ingram, Andrew Warfield, Jake Wires Approximating Hit Rate Curves using Streaming Algorithms. Search on Bibsonomy APPROX-RANDOM The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
36Brendan Cully, Jake Wires, Dutch T. Meyer, Kevin Jamieson 0002, Keir Fraser, Tim Deegan, Daniel Stodden, Geoffrey Lefebvre, Daniel Ferstay, Andrew Warfield Strata: scalable high-performance storage on virtualized non-volatile memory. Search on Bibsonomy FAST The full citation details ... 2014 DBLP  BibTeX  RDF
36Jake Wires, Stephen Ingram, Zachary Drudi, Nicholas J. A. Harvey, Andrew Warfield Characterizing Storage Workloads with Counter Stacks. Search on Bibsonomy OSDI The full citation details ... 2014 DBLP  BibTeX  RDF
36Dutch T. Meyer, Jake Wires, Norman C. Hutchinson, Andrew Warfield Namespace Management in Virtual Desktops. Search on Bibsonomy login Usenix Mag. The full citation details ... 2011 DBLP  BibTeX  RDF
36Mohammad Shamma, Dutch T. Meyer, Jake Wires, Maria Ivanova, Norman C. Hutchinson, Andrew Warfield Capo: Recapitulating Storage for Virtual Desktops. Search on Bibsonomy FAST The full citation details ... 2011 DBLP  BibTeX  RDF
36Jake Wires, Mark Spear, Andrew Warfield Exposing File System Mappings with MapFS. Search on Bibsonomy HotStorage The full citation details ... 2011 DBLP  BibTeX  RDF
36Jake Wires, Andrew Warfield Beyond Blocks and Files. Search on Bibsonomy login Usenix Mag. The full citation details ... 2010 DBLP  BibTeX  RDF
36Dutch T. Meyer, Mohammad Shamma, Jake Wires, Quan Zhang, Norman C. Hutchinson, Andrew Warfield Fast and Cautious Evolution of Cloud Storage. Search on Bibsonomy HotStorage The full citation details ... 2010 DBLP  BibTeX  RDF
36Dutch T. Meyer, Brendan Cully, Jake Wires, Norman C. Hutchinson, Andrew Warfield Block Mason. Search on Bibsonomy Workshop on I/O Virtualization The full citation details ... 2008 DBLP  BibTeX  RDF
36Jake Wires, Michael J. Feeley Secure file system versioning at the block level. Search on Bibsonomy EuroSys The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
36Kent E. Wires, Michael J. Schulte Reciprocal and Reciprocal Square Root Units with Operand Modification and Multiplication. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF reciprocal square root, Newton-Raphson iteration, computer arithmetic, function approximation, table lookup, reciprocal
36Mohammed S. Alam, Abhishek Gupta, Jake Wires, Son Thanh Vuong APHIDS++: Evolution of A Programmable Hybrid Intrusion Detection System. Search on Bibsonomy MATA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
36Kent E. Wires, Michael J. Schulte, Don McCarley FPGA Resource Reduction Through Truncated Multiplication. Search on Bibsonomy FPL The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
36Kent E. Wires, Michael J. Schulte, James E. Stine Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation. Search on Bibsonomy ICCD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
36Michael J. Schulte, Kent E. Wires High-Speed Inverse Square Roots. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1999 DBLP  DOI  BibTeX  RDF inverse square roots, truncated multiplication, squaring units, computer arithmetic, error analysis, VLSI design, Function approximation
34 Expression of Concern: Wang, C., Zhang, Q., Liu, W., Liu, Y. & Miao, L. Facial feature discovery for ethnicity recognition. WIREs Data Mining Knowl. Discov. 9 e1278 (2019). Search on Bibsonomy WIREs Data Mining Knowl. Discov. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
34Witold Pedrycz Introducing WIREs data mining and knowledge discovery. Search on Bibsonomy WIREs Data Mining Knowl. Discov. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
34Thorben Casper, Ulrich Römer, Herbert De Gersem, Sebastian Schöps Coupled simulation of transient heat flow and electric currents in thin wires: Application to bond wires in microelectronic chip packaging. Search on Bibsonomy Comput. Math. Appl. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
34Ilias Giechaskiel, Ken Eguro, Kasper Bonne Rasmussen Leakier Wires: Exploiting FPGA Long Wires for Covert- and Side-channel Attacks. Search on Bibsonomy ACM Trans. Reconfigurable Technol. Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
34Thorben Casper, Ulrich Römer, Sebastian Schöps, Herbert De Gersem Coupled Simulation of Transient Heat Flow and Electric Currents in Thin Wires: Application to Bond Wires in Microelectronic Chip Packaging. Search on Bibsonomy CoRR The full citation details ... 2018 DBLP  BibTeX  RDF
34Ilias Giechaskiel, Kasper Bonne Rasmussen, Ken Eguro Leaky Wires: Information Leakage and Covert Communication Between FPGA Long Wires. Search on Bibsonomy AsiaCCS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
34Andrew Adamatzky Physarum wires: Self-growing self-repairing smart wires made from slime mould. Search on Bibsonomy CoRR The full citation details ... 2013 DBLP  BibTeX  RDF
34Chih-Wei Jim Chang, Malgorzata Marek-Sadowska Who are the alternative wires in your neighborhood? (alternative wires identification without search). Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
32Seongmoo Heo, Krste Asanovic Replacing global wires with an on-chip network: a power analysis. Search on Bibsonomy ISLPED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF on-chip network power model, tile size, wire power model, pipelining, router, tiled architecture
32Tang Li 0004, Lijin Fang, Hongguang Wang Obstacle-navigation control for a mobile robot suspended on overhead ground wires. Search on Bibsonomy ICARCV The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Ester M. Garzón, Siham Tabik, Amelia Rubio Bretones, Inmaculada García Analysis of the Interaction of Electromagnetic Signals with Thin-Wires Structures. Multiprocessing Issues for an Iterative Method. Search on Bibsonomy VECPAR The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Hua Xiang 0001, Kai-Yuan Chao, D. F. Wong 0001 ECO algorithms for removing overlaps between power rails and signal wires. Search on Bibsonomy ICCAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
32Himanshu Kaul, Dennis Sylvester, David T. Blaauw Active shields: a new approach to shielding global wires. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
32Shih-Chii Liu, John G. Harris Dynamic wires: An alanog VLSI model for object-based processing. Search on Bibsonomy Int. J. Comput. Vis. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
32Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen Optimal Interconnect ATPG Under a Ground-Bounce Constraint. Search on Bibsonomy J. Electron. Test. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF testing, interconnect, Hamming distance, wires, ground bounce
32Ron Ho High-performance ULSI: the real limiter to interconnect scaling. Search on Bibsonomy SLIP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF VLSI, wireless, 3D, scaling, proximity, repeaters, wires
32Jelio Todorov Yantchev, C. G. Huang, Mark B. Josephs, Ivailo M. Nedelchev Low-latency asynchronous FIFO buffers. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF buffer circuits, low-latency asynchronous FIFO buffers, parallel asynchronous implementation, interface circuitry, inter-chip communication wires, acknowledge signal, high-throughput multiple-burst signalling scheme, packet switching, asynchronous circuits, pipeline processing, propagation delay
32David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska Circuit partitioning with logic perturbation. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF alternative wires, circuit partitioning
32Masahiro Nagamatu, Shakeel Ismail, Torao Yanaru Lagrangian method for wire routing of layout design. Search on Bibsonomy ANNES The full citation details ... 1995 DBLP  DOI  BibTeX  RDF wire routing, layout design, LSI layout design, continuous valued constrained optimization problem, continuous valued wires, dynamic equations, small switchbox routing problems, rip-up reroute maze router, neural nets, network routing, circuit layout CAD, circuit optimisation, integrated circuit layout, large scale integration, neurocomputing, Lagrangian method
30Rosemary M. Francis, Simon W. Moore FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF tdm wiring, fpga, routing
30Rupesh S. Shelar An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors. Search on Bibsonomy ISPD The full citation details ... 2009 DBLP  DOI  BibTeX  RDF routing, power, clock distribution
30Jin-Tai Yan, Zhi-Wei Chen Redundant wire insertion for yield improvement. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF redundant wire, routing, yield
30Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer Timing-aware power-optimal ordering of signals. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Wire ordering, wire spacing, power optimization, interconnect optimization
30Eduardo Luis Rhod, Luigi Carro An efficient test and characterization approach for nanowire-based architectures. Search on Bibsonomy SBCCI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF nanoPLA, test, yield, characterization, nanowires
30Shiyan Hu, Zhuo Li 0001, Charles J. Alpert A polynomial time approximation scheme for timing constrained minimum cost layer assignment. Search on Bibsonomy ICCAD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
30Arpita Patra, Ashish Choudhary, Kannan Srinathan, C. Pandu Rangan Perfectly Reliable and Secure Communication in Directed Networks Tolerating Mixed Adversary. Search on Bibsonomy DISC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
30Arpita Patra, Bhavani Shankar, Ashish Choudhary, K. Srinathan, C. Pandu Rangan Perfectly Secure Message Transmission in Directed Networks Tolerating Threshold and Non Threshold Adversary. Search on Bibsonomy CANS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Reliable and Secure Communication, Information Theoretic Security, Directed Networks, Communication Efficiency
30Maurice Herlihy, Srikanta Tirthapura Self-stabilizing smoothing and balancing networks. Search on Bibsonomy Distributed Comput. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Smoothing networks, Self-stabilization, Counting networks
30Jin-Tai Yan, Kuen-Ming Lin, Yen-Hsiang Chen Optimal shielding insertion for inductive noise avoidance. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
30Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter Interconnect-Aware Coherence Protocols for Chip Multiprocessors. Search on Bibsonomy ISCA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
30Krishnan Sundaresan, Nihar R. Mahapatra Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses. Search on Bibsonomy HPCA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
30Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera Return path selection for loop RL extraction. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
30Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF SPFD, collaboration of logic and physical design, global rewiring (GR), one-to-many rewiring (OMR), logic optimization
30K. Srinathan, Arvind Narayanan, C. Pandu Rangan Optimal Perfectly Secure Message Transmission. Search on Bibsonomy CRYPTO The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
30Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex Global interconnect trade-off for technology over memory modules to application level: case study. Search on Bibsonomy SLIP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Pareto-optimal energy/delay interconnect exploration, interconnect wire processing, intra/inter-memory interconnect
30Paul Wielage, Kees Goossens Networks on Silicon: Blessing or Nightmare? Search on Bibsonomy DSD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
30Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen Optimising bandwidth over deep sub-micron interconnect. Search on Bibsonomy ISCAS (4) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
30Mike Sheng, Jonathan Rose Mixing buffers and pass transistors in FPGA routing architectures. Search on Bibsonomy FPGA The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
30Phillip Christie, José Pineda de Gyvez Pre-layout prediction of interconnect manufacturability. Search on Bibsonomy SLIP The full citation details ... 2001 DBLP  DOI  BibTeX  RDF design, reliability, interconnect, theory, yield, Rent's rule, critical areas
30Yu-Liang Wu, Wangning Long, Hongbing Fan A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Alternative wiring, Graph-based pattern matching, Logic synthesis
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