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Publication years (Num. hits)
1993-1999 (20) 2000-2001 (16) 2002-2003 (22) 2004-2005 (33) 2006 (16) 2007 (17) 2008 (23) 2009-2012 (16) 2013-2017 (15) 2018-2021 (3)
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article(41) inproceedings(139) phdthesis(1)
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The graphs summarize 211 occurrences of 125 keywords

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Found 181 publication records. Showing 181 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
78David Goodwin, Darin Petkov Automatic generation of application specific processors. Search on Bibsonomy CASES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF automatic instruction-set generation, ASIPs, configurable processors, extensible processors
69Sung Dae Kim, Myung Hoon Sunwoo Low Power ASIP Architecture Optimization based on Target Application Profiling. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
62Muhammad Rashid, Ludovic Apvrille, Renaud Pacalet Evaluation of ASIPs Design with LISATek. Search on Bibsonomy SAMOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF LISATek, ASIPs, JPEG, Customized Instructions
52Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu A power-driven multiplication instruction-set design method for ASIPs. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
52Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran, Aleksandar Ignjatovic Application specific forwarding network and instruction encoding for multi-pipe ASIPs. Search on Bibsonomy CODES+ISSS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF multi-pipe ASIP, VLIW, forwarding, instruction encoding
52M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. Search on Bibsonomy ISSS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Trimaran, performance, design space exploration, VLIW, ASIP
41Ya-Shuai Lü, Li Shen 0007, Zhiying Wang 0003, Nong Xiao Dynamically utilizing computation accelerators for extensible processors in a software approach. Search on Bibsonomy CODES+ISSS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF computation accelerator, ASIP, dynamic binary translation
41Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF coarse-grained FPGA, VLIW, ASIP
41Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
41Miao Wang, Guiming Wu, Zhiying Wang 0003 Instruction Selection for Subword Level Parallelism Optimizations for Application Specific Instruction Processors. Search on Bibsonomy ISPA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
41Mehdi Modarressi, Shaahin Hessabi, Maziar Goudarzi A Reconfigurable Cache Architecture for Object-Oriented Embedded Systems. Search on Bibsonomy CCECE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
41Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre Application specific instruction-set processor generation for video processing based on loop optimization. Search on Bibsonomy ISCAS (4) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
41Bruce R. Childers, Jack W. Davidson Custom Wide Counterflow Pipelines for High-Performance Embedded Applications. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Counterflow pipelines, automatic architectural synthesis, application-specific processors
41Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. Search on Bibsonomy FPL The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
41Bruce R. Childers, Jack W. Davidson Custom Wide Counterflow Pipelines for High-Performance Embedded Applications. Search on Bibsonomy IEEE PACT The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
41Clifford Liem, Trevor C. May, Pierre G. Paulin Register assignment through resource classification for ASIP microcode generation. Search on Bibsonomy ICCAD The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
39Harold Ishebabi, Gerd Ascheid, Heinrich Meyr, Oguzhan Atak, Abdullah Atalar, Erdal Arikan An efficient parallelization technique for high throughput FFT-ASIPs. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
39Satish Pillai, Margarida F. Jacome Symbolic Binding for Clustered VLIW ASIPs. Search on Bibsonomy ICCD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
39Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors. Search on Bibsonomy ASAP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
39Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha Hierarchical test generation and design for testability methods for ASPPs and ASIPs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
39Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. Search on Bibsonomy DAC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
39Luigi Carro, G. A. Pereira, C. Alba, Altamiro Amadeu Susin System Design using ASIPs. Search on Bibsonomy ECBS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
37Hai Lin 0004, Yunsi Fei Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectives. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF asips, multi-objective design
37Rafael Peset Llopis, Ramanathan Sethuraman, Carlos A. Alba Pinto, Harm Peters, Steffen Maul, Marcel Oosterhuis A low-cost and low-power multi-standard video encoder. Search on Bibsonomy CODES+ISSS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF multi-standard, low-power, ASIPs, hardware/software partitioning, low-cost, video encoder
27Lars Bauer, Muhammad Shafique 0001, Jörg Henkel Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
27Carlo Galuzzi, Koen Bertels The Instruction-Set Extension Problem: A Survey. Search on Bibsonomy ARC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
27Muhammad Rashid, Ludovic Apvrille, Renaud Pacalet Application Specific Processors for Multimedia Applications. Search on Bibsonomy CSE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
27Steve Leibson, Grant Martin Design and verification of complex SoC with configurable, extensible processors. Search on Bibsonomy SoCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
27Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre Loop-oriented metrics for exploring an application-specific architecture design-space. Search on Bibsonomy ASAP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
27Yee Jern Chong, Sri Parameswaran Automatic application specific floating-point unit generation. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
27Hai Lin 0004, Xuan Guan, Yunsi Fei, Zhijie Jerry Shi Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors. Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
27Seng Lin Shee, Sri Parameswaran Design Methodology for Pipelined Heterogeneous Multiprocessor System. Search on Bibsonomy DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
27Rainer Leupers, Kingshuk Karuri, Stefan Kraemer, Manas Pandey A design flow for configurable embedded processors based on optimized instruction set extension synthesis. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
27Harm Peters, Ramanathan Sethuraman, Aleksandar Beric, Patrick Meuwissen, Srinivasan Balakrishnan, Carlos A. Alba Pinto, W. M. Kruijtzer, Fabian Ernst, Ghiath Alkadi, Jef L. van Meerbergen, Gerard de Haan Application Specific Instruction-Set Processor Template for Motion Estimation in Video Applications. Search on Bibsonomy IEEE Trans. Circuits Syst. Video Technol. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
27Leonardo Taglietti, José O. Carlomagno Filho, Daniel C. Casarotto, Olinto J. V. Furtado, Luiz C. V. dos Santos Automatic ADL-Based Assembler Generation for ASIP Programming Support. Search on Bibsonomy SAMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
27Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad Kia Micro embedded monitoring for security in application specific instruction-set processors. Search on Bibsonomy CASES The full citation details ... 2005 DBLP  DOI  BibTeX  RDF micro embedded monitoring, microinstructions, self-monitoring instructions, application specific instruction-set processors, security monitoring
27Bita Gorjiara, Daniel D. Gajski Custom Processor Design Using NISC: A Case-Study on DCT algorithm. Search on Bibsonomy ESTIMedia The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
27Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths. Search on Bibsonomy ICCD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
27Tilman Glökler, Andreas Hoffmann 0002, Heinrich Meyr Methodical Low-Power ASIP Design Space Exploration. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF ICORE, low power, ASIP, application-specific instruction set processor, low energy, LISA
27Chidamber Kulkarni, Matthias Gries, Christian Sauer 0001, Kurt Keutzer Programming challenges in network processor deployment. Search on Bibsonomy CASES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF IPv4 forwarding, programming heterogeneous architectures, mapping, programming model, multi-threading, resource sharing
27Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt Energy-efficient instruction set synthesis for application-specific processors. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF low power, customization, application-specific instruction set processor (ASIP), instruction encoding, energy-delay product
27Jeonghun Cho, Yunheung Paek, David B. Whalley Efficient register and memory assignment for non-orthogonal architectures via graph coloring and MST algorithms. Search on Bibsonomy LCTES-SCOPES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF dual memory, memory assignment, non-orthogonal architecture, compiler, graph coloring, maximum spanning tree
27T. Vinod Kumar Gupta, Roberto E. Ko, Rajeev Barua Compiler-directed customization of ASIP cores. Search on Bibsonomy CODES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF soft cores, embedded, customization, ASIP
27Wei Qin, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David I. August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh Design Tools for Application Specific Embedded Processors. Search on Bibsonomy EMSOFT The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
27Margarida F. Jacome, Gustavo de Veciana Lower bound on latency for VLIW ASIP datapaths. Search on Bibsonomy ICCAD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
25Shubhankar Suman Singh, Smruti R. Sarangi ISAMod: A Tool for Designing ASIPs by Comparing Different ISAs. Search on Bibsonomy VLSID The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
25Vikkitharan Gnanasambandapillai, Jorgen Peddersen, Roshan G. Ragel, Sri Parameswaran FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
25Shahriar Shahabuddin, Olli Silvén, Markku J. Juntti Programmable ASIPs for Multimode MIMO Transceiver. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
25Yosi Ben-Asher, Irina Lipov, Vladislav Tartakovsky, Dror Tiv Generating ASIPs with Reduced Number of Connections to the Register-File. Search on Bibsonomy Int. J. Parallel Program. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
25Paolo Meloni, Claudio Rubattu, Giuseppe Tuveri, Danilo Pani, Luigi Raffo, Francesca Palumbo Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs. Search on Bibsonomy J. Syst. Archit. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
25Roberto Urban, Heinrich Theodor Vierhaus, Mario Schölzel, Enrico Altmann, Horst Seelig Non-Cyclic Design Space Exploration for ASIPs - Compiler-Centered Microprocessor Design (CoMet). Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
25Jakub Podivinsky, Marcela Simková, Ondrej Cekan, Zdenek Kotásek FPGA Prototyping and Accelerated Verification of ASIPs. Search on Bibsonomy DDECS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
25Yosi Ben-Asher, Irina Lipov, Vladislav Tartakovsky, Dror Tiv Generating ASIPs with reduced number of connections to the register-file. Search on Bibsonomy SAMOS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
25Erkan Diken, Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal, Felipe Augusto Chies Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths. Search on Bibsonomy Microprocess. Microsystems The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
25Hong Chinh Doan, Haris Javaid, Sri Parameswaran Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs. Search on Bibsonomy DATE The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
25Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak, Henk Corporaal Automatic complex instruction identification for efficient application mapping onto ASIPs. Search on Bibsonomy LASCAS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
25Yosi Ben-Asher, Irina Lipov, Vladislav Tartakovsky, Dror Tiv Using Multi-op Instructions as a Way to Generate ASIPs with Optimized Pipeline Structure. Search on Bibsonomy FCCM The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
25Roel Jordans, Lech Józwiak, Henk Corporaal Instruction-set architecture exploration of VLIW ASIPs using a genetic algorithm. Search on Bibsonomy MECO The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
25Erkan Diken, Roel Jordans, Lech Józwiak, Henk Corporaal Construction and exploitation of VLIW asips with multiple vector-widths. Search on Bibsonomy MECO The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
25Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak, Henk Corporaal A framework for automatic custom instruction identification on multi-issue ASIPs. Search on Bibsonomy INDIN The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
25Hsuanchun Liao, Mochamad Asri, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing. Search on Bibsonomy J. Inf. Process. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
25Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal Instruction-set architecture exploration strategies for deeply clustered VLIW ASIPs. Search on Bibsonomy MECO The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
25Erkan Diken, Rosilde Corvino, Lech Józwiak Rapid and accurate energy estimation of vector processing in VLIW ASIPs. Search on Bibsonomy MECO The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
25Majid Nezakatolhoseini, Mohammad Amin Taherkhani A Framework For Performance Evaluation Of ASIPS In Network-Based IDS Search on Bibsonomy CoRR The full citation details ... 2012 DBLP  BibTeX  RDF
25Unmesh D. Bordoloi, Bogdan Tanasa, Mehdi Baradaran Tahoori, Petru Eles, Zebo Peng, Syed Zafar Shazli, Samarjit Chakraborty Reliability-Aware Instruction Set Customization for ASIPs with Hardened Logic. Search on Bibsonomy RTCSA The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
25David Kammler Memory architectures for ASIPs. Search on Bibsonomy 2012   RDF
25Lech Józwiak, Menno Lindwer Issues and Challenges in Development of Massively-Parallel Heterogeneous MPSoCs Based on Adaptable ASIPs. Search on Bibsonomy PDP The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
25Daniel Shapiro, Jonathan Parri, John-Marc Desmarais, Voicu Groza, Miodrag Bolic ASIPs for artificial neural networks. Search on Bibsonomy SACI The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
25Christian Brehm, Norbert Wehn, Sacha Loitz, Wolfgang Kunz Validation of channel decoding ASIPs a case study. Search on Bibsonomy International Symposium on Rapid System Prototyping The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
25David Kammler, Ernst Martin Witte, Anupam Chattopadhyay, Bastian Bauwens, Gerd Ascheid, Rainer Leupers, Heinrich Meyr Automatic Generation of Memory Interfaces for ASIPs. Search on Bibsonomy Int. J. Embed. Real Time Commun. Syst. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
25Zdenek Prikryl, Jakub Kroustek, Tomas Hruska, Dusan Kolár Fast Translated Simulation of ASIPs. Search on Bibsonomy MEMICS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
25Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran, Aleksandar Ignjatovic HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors. Search on Bibsonomy IET Comput. Digit. Tech. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
25Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro Dynamically Adapted Low Power ASIPs. Search on Bibsonomy ARC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
25Naser MohammadZadeh, Shaahin Hessabi, Maziar Goudarzi, Mahdi Malaki A Framework for Object-Oriented Embedded System Development Based on OO-ASIPs. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
25Peter Hallschmid, Resve A. Saleh Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
25Bernd Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF eFPGA, Parametrisable architecture, Arithmetic oriented, Processor-eFPGA coupling, ASIP
25Vladimír Guzma, Shuvra S. Bhattacharyya, Pertti Kellomäki, Jarmo Takala Trade-offs in mapping high-level dataflow graphs onto ASIPs. Search on Bibsonomy SoC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
25Gert Goossens, Dirk Lanneer, Werner Geurts, Johan Van Praet Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite. Search on Bibsonomy SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Mile K. Stojcev Design of Energy-Efficient Application-Specific Instruction Set Processors (ASIPs), Tilman Glokler, Heinrich Meyr, Kluwer Academic Publishers, Boston, 2004, ISBN 1-4020-7730-0, Hardcover, pp 234, plus XX. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
25Vijayakumar Kalyanaraman, Matthias Müller 0002, Sven Simon 0001, Mario Steinert, Holger Gryska A power dissipation comparison of ALU-architectures for ASIPs. Search on Bibsonomy ECCTD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
25Vijayakumar Kalyanaraman, Matthias Müller 0002, Sven Simon 0001, Mario Steinert, Holger Gryska Power reduction of ASIPs by distributing the workload on several ASIP-instances. Search on Bibsonomy ECCTD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
25Paul Morgan, Richard Taylor, Japheth Hossell, George Bruce, Barry O'Rourke Automated data cache placement for embedded VLIW ASIPs. Search on Bibsonomy CODES+ISSS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF cache, ASIP, cache optimization, embedded applications
25Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu A power-driven multiplication instruction-set design method for ASIPs. Search on Bibsonomy ISCAS (4) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
25Maziar Goudarzi, Shaahin Hessabi, Alan Mycroft Object-Oriented Embedded System Development Based on Synthesis and Reuse of OO-ASIPs. Search on Bibsonomy J. Univers. Comput. Sci. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Wilson D. Pace, Elizabeth W. Staton, Gregory S. Higgins, Deborah S. Main, David R. West, Daniel M. Harris Application of Information Technology: Database Design to Ensure Anonymous Study of Medical Errors: A Report from the ASIPS collaborative. Search on Bibsonomy J. Am. Medical Informatics Assoc. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
25Dirk Fischer 0001, Jürgen Teich, Ralph Weper, Michael Thies BUILDABONG: A Framework for Architecture/Compiler Co-Exploration for ASIPs. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
25R. Govindarajan, Erik R. Altman, Guang R. Gao A Theory for Co-Scheduling Hardware and Software Pipelines in ASIPs and Embedded Processors. Search on Bibsonomy Des. Autom. Embed. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
25Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt Efficient instruction encoding for automatic instruction set design of configurable ASIPs. Search on Bibsonomy ICCAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
25Dirk Fischer 0001, Jürgen Teich, Michael Thies, Ralph Weper Efficient architecture/compiler co-exploration for ASIPs. Search on Bibsonomy CASES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF architecture/compiler codesign, multiobjective design space exploration, ASIP, retargetable compilation
25Andreas Hoffmann 0002, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
25Ashok Sudarsanam, Sharad Malik Simultaneous reference allocation in code generation for dual data memory bank ASIPs. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF memory bank assignment, code generation, register allocation, code optimization, graph labelling
25Margarida F. Jacome, Gustavo de Veciana, Viktor S. Lapinskii Exploring Performance Tradeoffs for Clustered VLIW ASIPs. Search on Bibsonomy ICCAD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
25Jürgen Teich, Ralph Weper, Dirk Fischer 0001, Stefan Trinkert A joined architecture/compiler design environment for ASIPs. Search on Bibsonomy CASES The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
25S. Ramanathan, V. Visvanathan, S. K. Nandy 0001 Synthesis of ASIPs for DSP algorithms. Search on Bibsonomy Integr. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
25Margarida F. Jacome, Gustavo de Veciana, Cagdas Akturan Resource constrained dataflow retiming heuristics for VLIW ASIPs. Search on Bibsonomy CODES The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
25Nguyen-Ngoc Bình, Masaharu Imai, Yoshinori Takeuchi A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes. Search on Bibsonomy ASP-DAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
25Masaharu Imai, Nguyen-Ngoc Bình, Akichika Shiomi A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs. Search on Bibsonomy EURO-DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
25Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts. Search on Bibsonomy DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
25Frederick Onion, Alexandru Nicolau, Nikil D. Dutt Incorporating compiler feedback into the design of ASIPs. Search on Bibsonomy ED&TC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
25Ashok Sudarsanam, Sharad Malik Memory bank and register allocation in software synthesis for ASIPs. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
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