Search results for "bit-parallel"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
39	Junbo Wang, Fei Kang, Xinlei Xu, Jingning Chen	A Fast Single Pattern Matching Algorithm Based on the Bit-Parallel.	FCST	2010	DBLP DOI BibTeX RDF	Sunday, KMP, BNDM, bit-parallel table, bit parallel element, pattern matching, BM
36	Chiou-Yng Lee, Che Wun Chiou	New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2m) Under Polynomial Basis and Normal Basis Representations.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	finite field, normal basis, polynomial basis, bit-parallel systolic multiplier
35	Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee	Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	AOP, finite field, Bit-parallel systolic multiplier, ESP
34	Sun-Mi Park, Ku-Young Chang, Dowon Hong	Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	shifted polynomial basis, irreducible pentanomial, finite field arithmetic, Bit-parallel multiplier
34	Ku-Young Chang, Dowon Hong, Hyun Sook Cho	Low Complexity Bit-Parallel Multiplier for GF(2^m) Defined by All-One Polynomials Using Redundant Representation.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Karatsuba method, AOP, finite field arithmetic, redundant representation, Bit-parallel multiplier
33	Chiou-Yng Lee, Jenn-Shyong Horng, I-Chang Jou	Low-Complexity Bit-Parallel Multiplier over GF(2m) Using Dual Basis Representation.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	Galois field GF(2m), inner product, dual basis, bit-parallel systolic multiplier
32	Pablo San Segundo, Cristóbal Tapia, Julio Puente, Diego Rodríguez-Losada	A New Exact Bit-Parallel Algorithm for SAT.	ICTAI (2)	2008	DBLP DOI BibTeX RDF
32	Guomin Zhang, En Zhu, Ling Mao, Ming Yin	A Bit-Parallel Exact String Matching Algorithm for Small Alphabet.	FAW	2009	DBLP DOI BibTeX RDF	matching table, matching matrix, String matching, bit-parallel
32	Chiou-Yng Lee, Jenn-Shyong Horng, I-Chang Jou, Erl-Huei Lu	Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2m).	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	irreducible AOP, finite field, montgomery multiplication, irreducible trinomial, Bit-parallel systolic multiplier
32	Paul Pritchard	A Fast Bit-Parallel Algorithm for Computing the Subset Partial Order.	Algorithmica	1999	DBLP DOI BibTeX RDF	Subset graph, Subset partial order, Bit-parallel operation, Set-theoretic algorithms, Combinatorial set theory, Analysis of algorithms, Bit vector
31	M. Oguzhan Külekci	A Method to Overcome Computer Word Size Limitation in Bit-Parallel Pattern Matching.	ISAAC	2008	DBLP DOI BibTeX RDF
29	Heikki Hyyrö, Gonzalo Navarro 0001	Bit-Parallel Witnesses and Their Applications to Approximate String Matching.	Algorithmica	2005	DBLP DOI BibTeX RDF	Backward DAWG matching, Myers bit-parallel algorithm, Average-optimal string matching allowing errors, Bit-parallelism
29	S. M. Mortazavi Zanjani, Somayyeh Rahimian Omam, Seid Mehdi Fakhraie, Omid Shoaei	Experimental Evaluation of Different Realizations of Recursive CIC Filters.	CCECE	2006	DBLP DOI BibTeX RDF
29	Isaac D. Scherson, David A. Kramer, Brian D. Alleyne	Bit-Parallel Arithmetic in a Massively-Parallel Associative Processor.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	bit-parallel arithmetic, massively-parallel associative processor, storage cells, floating point data, VLSI, VLSI, parallel architectures, fast Fourier transform, fast Fourier transforms, digital arithmetic, matrix multiplication, multiplication, division
27	Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong	A systolic multiplier with LSB first algorithm over GF(2m) which is as efficient as the one with MSB first algorithm.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
27	Kimmo Fredriksson	Row-wise Tiling for the Myers' Bit-Parallel Approximate String Matching Algorithm.	SPIRE	2003	DBLP DOI BibTeX RDF
25	Robert D. Cameron	A case study in SIMD text processing with parallel bit streams: UTF-8 to UTF-16 transcoding.	PPoPP	2008	DBLP DOI BibTeX RDF	UTF-16, UTF-8, parallel bit streams, simd text processing, transcoding
25	Hannu Peltola, Jorma Tarhio	Alternative Algorithms for Bit-Parallel String Matching.	SPIRE	2003	DBLP DOI BibTeX RDF
25	Huapeng Wu	Low Complexity Bit-Parallel Finite Field Arithmetic Using Polynomial Basis.	CHES	1999	DBLP DOI BibTeX RDF
25	Yun Sik Lee, Peter M. Maurer	Bit-parallel multidelay simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
25	Huapeng Wu, M. Anwarul Hasan	Low Complexity Bit-Parallel Multipliers for a Class of Finite Fields.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	Galois or finite fields, equally spaced polynomial, dual basis, bit-parallel multiplier, all one polynomial
24	Florent de Dinechin	Libraries of schedule-free operators in Alpha.	ASAP	1997	DBLP DOI BibTeX RDF	schedule-free operators, digital circuits synthesis, bit-level, binary implementation, bit-level dependency analysis, bit-parallel array, parallelism, digital circuits, arithmetic operators, affine recurrence equations, matrix-vector product
24	Chuanhuan Yin, Shengfeng Tian, Shaomin Mu	A Fast Bit-Parallel Algorithm for Gapped String Kernels.	ICONIP (1)	2006	DBLP DOI BibTeX RDF
24	Huapeng Wu	Bit-Parallel Finite Field Multiplier and Squarer Using Polynomial Basis.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	hardware architecture, Finite fields arithmetic, polynomial basis
23	Zhiyuan Yan, Dilip V. Sarwate, Zhongzhi Liu	Area-efficient systolic architectures for inversions over GF(2m).	ISCAS (6)	2005	DBLP DOI BibTeX RDF
22	Heikki Hyyrö, Jun Takaba, Ayumi Shinohara, Masayuki Takeda	On Bit-Parallel Processing of Multi-byte Text.	AIRS	2004	DBLP DOI BibTeX RDF
22	Ocean Y. H. Cheung, Kuen Hung Tsoi, Philip Heng Wai Leong, Monk-Ping Leong	Tradeoffs in Parallel and Serial Implementations of the International Data Encryption Algorithm IDEA.	CHES	2001	DBLP DOI BibTeX RDF	performance-tradeoffs, reconfigurable-computing, digital-design, Cryptographic hardware
22	Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert Felber, Matthias Braendli	Multi-gigabit GCM-AES Architecture Optimized for FPGAs.	CHES	2007	DBLP DOI BibTeX RDF	Galois/Counter Mode (GCM), hybrid multiplier, Field Programmable Gate Array (FPGA), Very Large Scale Integration (VLSI), Advanced Encryption Standard (AES), high throughput, digit-serial multiplier, bit-parallel multiplier
22	A. S. Nepomniaschaya, Zbigniew Kokosinski	Associative Graph Processor and Its Properties.	PARELEC	2004	DBLP DOI BibTeX RDF	associative parallel processor, bit-parallel processing, associative graph processing, multiple-search
21	Ciaran Toal, Sakir Sezer	The Implementation of Scalable ATM Frame Delineation Circuits.	ICT	2004	DBLP DOI BibTeX RDF
21	Pablo San Segundo, Diego Rodríguez-Losada, Ramón Galán, Fernando Matía, Agustín Jiménez	Exploiting CPU Bit Parallel Operations to Improve Efficiency in Search.	ICTAI (1)	2007	DBLP DOI BibTeX RDF
20	José Luis Imaña, Román Hermida, Francisco Tirado	Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
20	Chiou-Yng Lee, Yu-Hsin Chiu, Che Wun Chiou	New Bit-Parallel Systolic Multiplier over GF(2m) Using The Modified Booth's Algorithm.	APCCAS	2006	DBLP DOI BibTeX RDF
20	Arash Reyhani-Masoleh, M. Anwar Hasan	Low Complexity Bit Parallel Architectures for Polynomial Basis Multiplication over GF(2^{m}).	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
19	José Luis Imaña, Juan Manuel Sánchez	Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF(2m) Generated by AOPs.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	Galois field GF(2m), canonical basis, reconfigurable hardware, normal basis, bit-parallel multiplier
19	Sangho Oh, Chang Han Kim, Jongin Lim 0001, Dong Hyeon Cheon	Efficient Normal Basis Multipliers in Composite Fields.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Finite field, composite field, optimal normal basis, bit-parallel multiplier
19	Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man	Synthesis of pipelined DSP accelerators with dynamic scheduling.	ISSS	1995	DBLP DOI BibTeX RDF	DSP algorithms, FFT butterfly accelerator block, application specific DSP accelerators, highly pipelined data paths, pipelined DSP accelerator synthesis, pipelined bit-parallel hardware, silicon, scheduling, parallel architectures, application specific integrated circuits, dynamic scheduling, pipeline processing, circuit CAD, digital signal processing chips, datapath, controller architecture, network synthesis, run-time schedules
19	Michael Bolotski, Thomas Simon, Carlin Vieri, Rajeevan Amirtharajah, Thomas F. Knight Jr.	Abacus: a 1024 processor 8 ns SIMD array.	ARVLSI	1995	DBLP DOI BibTeX RDF	bit-slice computers, Abacus, SIMD array, reconfigurable bit-parallel array, system-level design issues, real-time early vision processing, bit-slice processing element, 8 ns, real-time systems, computer vision, VLSI, parallel architectures, reconfigurable architectures, microarchitecture, VLSI implementation, communication primitives
19	Francisco Rodríguez-Henríquez, Guillermo Morales-Luna, Julio César López-Hernández	Low-Complexity Bit-Parallel Square Root Computation over GF(2^{m}) for All Trinomials.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Computations in finite fields, Algorithms, Computer arithmetic
18	Dan Cyca, Laurence E. Turner	Bit-Serial Digital Filter Implementation using a Custom C Compiler.	APCCAS	2006	DBLP DOI BibTeX RDF
18	Isaac D. Scherson, David A. Kramer, Brian D. Alleyne	A Fine-Grain Bit-Parallel, Word-Parallel, Massively-Parallel Associative Processor.	ICPP (1)	1990	DBLP BibTeX RDF
18	Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan	Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m).	VLSI Design	2007	DBLP DOI BibTeX RDF
18	Shiann Shiun Jeng, Hsing-Chen Lin, Shu-Ming Chang	FPGA implementation of FIR filter using M-bit parallel distributed arithmetic.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Heikki Hyyrö, Yoan J. Pinzón, Ayumi Shinohara	New Bit-Parallel Indel-Distance Algorithm.	WEA	2005	DBLP DOI BibTeX RDF
17	Heikki Hyyrö, Kimmo Fredriksson, Gonzalo Navarro 0001	Increased bit-parallelism for approximate and multiple string matching.	ACM J. Exp. Algorithmics	2005	DBLP DOI BibTeX RDF	multiple string matching, Approximate string matching, bit-parallelism
17	Takahiro Kawaguchi, Naofumi Takagi	32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor.	IEICE Trans. Electron.	2022	DBLP DOI BibTeX RDF
17	Alok Parmar, Kailash Prasad, Nanditha P. Rao, Joycee Mekie	An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory Computing for DNNs.	ISCAS	2022	DBLP DOI BibTeX RDF
17	Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park 0001	Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision.	CoRR	2020	DBLP BibTeX RDF
17	Khalid Al-Hawaj, Olalekan Afuye, Shady Agwa, Alyssa B. Apsel, Christopher Batten	Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM.	ISCAS	2020	DBLP DOI BibTeX RDF
17	Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park 0001	Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision.	DAC	2020	DBLP DOI BibTeX RDF
17	Kazuya Tanigawa, Ken'ichi Umeda, Tetsuo Hironaka	Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor.	ARC	2010	DBLP DOI BibTeX RDF
17	Arash Hariri, Arash Reyhani-Masoleh	Bit-Serial and Bit-Parallel Montgomery Multiplication and Squaring over GF(2^m).	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
17	Krishna M. Sivalingam	A Comparison of Bit-Parallel and Bit-Serial Architectures for WDM Networks.	Photonic Netw. Commun.	1999	DBLP DOI BibTeX RDF
17	David Crook, John Fulcher	A Comparison of Bit Serial and Bit Parallel DCT Designs.	VLSI Design	1995	DBLP DOI BibTeX RDF
16	Daniel Jiménez-González, Juan J. Navarro, Josep Lluís Larriba-Pey	Fast parallel in-memory 64-bit sorting.	ICS	2001	DBLP DOI BibTeX RDF	avoid unncessary sorting, reduction of communication, load balance, parallel sorting, Radix sort
16	Luigi Dadda, Vincenzo Piuri, Renato Stefanelli	Multi-parallel convolvers.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
16	Peter M. Maurer	Two new techniques for unit-delay compiled simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
16	Akihisa Ohta, Tsuyoshi Isshiki, Hiroaki Kunieda	New FPGA Architecture for Bit-Serial Pipeline Datapath.	FCCM	1998	DBLP DOI BibTeX RDF
15	J. Gonzalez-Torres, P. A. Mateos, J. M. Hernandez	Full custom chip set for high speed serial communications up to 2.48 Gbit/s.	ED&TC	1997	DBLP DOI BibTeX RDF
15	Leilei Song, Keshab K. Parhi	Efficient Finite Field Serial/Parallel Multiplication.	ASAP	1996	DBLP DOI BibTeX RDF	finite field serial/parallel multiplication, finite field arithmetic architectures, bit-serial/parallel finite field multiplier, standard basis representation, optimal primitive polynomials, minimum hardware complexity, semi-systolic architecture, computational complexity, cryptography, cryptography, encoding, digital arithmetic, polynomials, multiplying circuits, VLSI implementation, coding theory
15	Rajesh Prasad, Suneeta Agarwal, Ishadutta Yadav, Bharat Singh	Efficient bit-parallel multi-patterns string matching algorithms for limited expression.	Bangalore Compute Conf.	2010	DBLP DOI BibTeX RDF	BNDM, multiple patterns, shift-or, algorithm, bit-parallelism
15	Hiroaki Yamamoto, Daichi Takenouchi	Bit-Parallel Tree Pattern Matching Algorithms for Unordered Labeled Trees.	WADS	2009	DBLP DOI BibTeX RDF
15	Huapeng Wu	Bit-Parallel Polynomial Basis Multiplier for New Classes of Finite Fields.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
15	Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir	Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m).	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
15	Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir	C-testable bit parallel multipliers over GF(2m).	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	testing, cryptography, built-in self-test, digital signal processing, polynomials, VLSI design, stuck-at fault, TPG, fault, multiplier, Galois field, error control code, C-testable
15	Chiou-Yng Lee, Pramod Kumar Meher	Efficient Bit-Parallel Multipliers in Composite Fields.	APSCC	2008	DBLP DOI BibTeX RDF
15	Gang Zhou, Li Li 0027, Harald Michalik	Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
15	Dong-Yu Zheng, Yan Sun, Shao-Qing Li, Liang Fang	A 485ps 64-Bit Parallel Adder in 0.18mum CMOS.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	semi-dynamic, sparse-tree, parallel prefix adder
15	Jimson Mathew, Hafizur Rahaman 0001, Dhiraj K. Pradhan	Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set.	IOLTS	2007	DBLP DOI BibTeX RDF
15	Hafizur Rahaman 0001, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan	Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}).	VTS	2007	DBLP DOI BibTeX RDF	cryptography, polynomials, Multipliers, Galois field, error control code, Transition fault, C-testable
15	José Luis Imaña, Juan Manuel Sánchez, Francisco Tirado	Bit-Parallel Finite Field Multipliers for Irreducible Trinomials.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Finite (or Galois) fields, canonical basis, triangular basis, complexity, permutation, multiplication, cycles, matrix decomposition, transpositions, irreducible trinomials
15	Heikki Hyyrö	Tighter Packed Bit-Parallel NFA for Approximate String Matching.	CIAA	2006	DBLP DOI BibTeX RDF
15	Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin	Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2m).	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	cryptography, fault-tolerant computing, fault detection, finite fields, multiplier, single stuck-at fault
15	Hisashi Tsuji, Akira Ishino, Masayuki Takeda	A Bit-Parallel Tree Matching Algorithm for Patterns with Horizontal VLDC's.	SPIRE	2005	DBLP DOI BibTeX RDF
15	Soonhak Kwon	A Low Complexity and a Low Latency Bit Parallel Systolic Multiplier over GF(2m) Using an Optimal Normal Basis of Type II.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
15	Hiroaki Yamamoto, Takashi Miyazaki	A Fast Bit-Parallel Algorithm for Matching Extended Regular Expressions.	COCOON	2003	DBLP DOI BibTeX RDF
15	Arash Reyhani-Masoleh, M. Anwarul Hasan	On Low Complexity Bit Parallel Polynomial Basis Multipliers.	CHES	2003	DBLP DOI BibTeX RDF	Finite or Galois field, Mastrovito multiplier, pentanomial, trinomial and equally-spaced polynomial, polynomial basis
15	Heikki Hyyrö, Gonzalo Navarro 0001	Faster Bit-Parallel Approximate String Matching.	CPM	2002	DBLP DOI BibTeX RDF
15	Gunok Jung, V. A. Sundarajan, Gerald E. Sobelman	A robust self-resetting CMOS 32-bit parallel adder.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
15	Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee	New bit-parallel systolic multipliers for a class of GF(2m).	ISCAS (4)	2001	DBLP DOI BibTeX RDF
15	Henrik Ohlsson, Oscar Gustafsson, Lars Wanhammar	Arithmetic transformations for increased maximal sample rate of bit-parallel bireciprocal lattice wave digital filters.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
15	Jyh-Huei Guo, Chin-Liang Wang	A low time-complexity, hardware-efficient bit-parallel power-sum circuit for finite fields GF(2M).	ISCAS (1)	1999	DBLP DOI BibTeX RDF
15	Ahmed Louri	An Optical Content-Adressable Parallel Processor for Fast Searching and Retrieving.	PARLE (1)	1991	DBLP DOI BibTeX RDF
15	Rafal Karakiewicz, Roman Genov	Minimal activity mixed-signal VLSI architecture for real-time linear transforms in video.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
15	Kamlesh Rath, Sirisha Tangirala, Patrick Friel, Poras T. Balsara, Jose Flores, John P. Wadley	Reconfigurable Array Media Processor (RAMP).	FCCM	2000	DBLP DOI BibTeX RDF
15	J. Living, Bashir M. Al-Hashimi	Mixed arithmetic architecture: a solution to the iteration bound for resource efficient FPGA and CPLD recursive digital filters.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
15	M. Yan, John V. McCanny, Yi Hu	VLSI architectures for vector quantization.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
14	Chin-Chin Chen, Chiou-Yng Lee, Erl-Huei Lu	Combined circuit architecture for computing normal basis and montgomery multiplications over GF(2m).	Mobility Conference	2008	DBLP DOI BibTeX RDF	hankel matrix-vector, normal bases, montgomery, bit-parallel systolic multiplier
14	Chiou-Yng Lee, Yung-Hui Chen, Che Wun Chiou, Jim-Min Lin	Unified Parallel Systolic Multiplier Over GF(2m).	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	Hankel matrix-vector multiplication, Galois field, bit-parallel systolic multiplier
14	Christof Paar, Peter Fleischmann, Peter Roelse	Efficient Multiplier Architectures for Galois Fields GF(2 4n).	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	Karatsuba Ofman, modulo reduction, multiplication, VLSI architecture, Galois fields, bit parallel, composite fields
14	Jie-Yong Juang, Benjamin W. Wah	A Contention-Based Bus-Control Scheme for Multiprocessor Systems.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	bus-control schemes, scheduling processors, scheduling, computational complexity, multiprocessor interconnection networks, multiprocessing systems, contention-based, bit-parallel, shared bus
14	V. B. Fyodorov	Bit-Parallel Selfrouting Optoelectronic Switching Fabrics for Massively Parallel Wide-Format Data Processing: Principle and Optical Architecture.	ISPAN	1997	DBLP DOI BibTeX RDF	Free space optical interconnections, Completely connected networks, Smart pixel arrays, VCSEL technology
14	Ching-Long Su, Yin-Tsung Hwang	Distributed arithmetic-based architectures for high speed IIR filter design.	ICPADS	1996	DBLP DOI BibTeX RDF	high speed IIR filter, pipelining techniques, SPDM technology, parallel processing, parallel architectures, digital arithmetic, recursion, recursive filters, Distributed Arithmetic, IIR filters, DSP applications
13	Siavash Bayat Sarmadi, M. Anwar Hasan	On Concurrent Detection of Errors in Polynomial Basis Multiplication.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
13	Siavash Bayat Sarmadi, M. Anwar Hasan	Concurrent Error Detection of Polynomial Basis Multiplication over Extension Fields using a Multiple-bit Parity Scheme.	DFT	2005	DBLP DOI BibTeX RDF
12	Siavash Bayat Sarmadi, M. Anwar Hasan	Detecting errors in a polynomial basis multiplier using multiple parity bits for both inputs.	ICCD	2007	DBLP DOI BibTeX RDF
12	Arash Reyhani-Masoleh, M. Anwar Hasan	Fault Detection Architectures for Field Multiplication Using Polynomial Bases.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	polynomial basis multiplier, Finite fields, error detection
12	Hosahalli R. Srinivas, Keshab K. Parhi	High-speed VLSI arithmetic processor architectures using hybrid number representation.	J. VLSI Signal Process.	1992	DBLP DOI BibTeX RDF
11	Peng Yin Choo, Abram Detofsky, Ahmed Louri	The Equivalency Processing Parallel Photonic Integrated Circuit (EP3IC), a Parallel Digital Equivalence Search Module.	AIPR	2000	DBLP DOI BibTeX RDF
11	Zbigniew Kokosinski, Bartlomiej Malus	FPGA Implementations of a Parallel Associative Processor with Multi-Comparand Multi-Search Operations.	ISPDC	2008	DBLP DOI BibTeX RDF