Search results for "bit-serial"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
82	Arash Reyhani-Masoleh	A New Bit-Serial Architecture for Field Multiplication Using Polynomial Bases.	CHES	2008	DBLP DOI BibTeX RDF	Finite or Galois field, Mastrovito multiplier, polynomial basis, bit-serial multiplier
67	Soonhak Kwon, Heuisu Ryu	Efficient Bit Serial Multiplication Using Optimal Normal Bases of Type II in GF (2m).	ISC	2002	DBLP DOI BibTeX RDF	bit serial multiplication, optimal normal basis of type II, Finite field, dual basis
64	Dan Cyca, Laurence E. Turner	Bit-Serial Digital Filter Implementation using a Custom C Compiler.	APCCAS	2006	DBLP DOI BibTeX RDF
62	Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor	FPGA-Based Structures for On-Line FFT and DCT.	FCCM	1999	DBLP DOI BibTeX RDF	FPGA, interconnect, MAC, FFT, signal processing, DCT, online, on-line, distributed arithmetic, bit-serial, xilinx, on-line arithmetic
62	Leilei Song, Keshab K. Parhi	Efficient Finite Field Serial/Parallel Multiplication.	ASAP	1996	DBLP DOI BibTeX RDF	finite field serial/parallel multiplication, finite field arithmetic architectures, bit-serial/parallel finite field multiplier, standard basis representation, optimal primitive polynomials, minimum hardware complexity, semi-systolic architecture, computational complexity, cryptography, cryptography, encoding, digital arithmetic, polynomials, multiplying circuits, VLSI implementation, coding theory
58	Yong Ho Hwang, Sang Gyoo Sim, Pil Joong Lee	Bit-Serial Multipliers for Exponentiation and Division in GF(2m) Using Irreducible AOP.	ICCSA (1)	2004	DBLP DOI BibTeX RDF	Irreducible AOP, Finite field, Exponentiation, Bit-serial multiplier
58	Johann Großschädl	A Bit-Serial Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m).	CHES	2001	DBLP DOI BibTeX RDF	iterative modulo multiplication, polynomial basis representation, bit-serial multiplier architecture, smart card crypto-coprocessor, Elliptic curve cryptography, finite field arithmetic
58	S. A. Rahim, Laurence E. Turner	A Field Programmable Bit-Serial Digital Signal Processor.	IWSOC	2004	DBLP DOI BibTeX RDF
56	Priyadarsan Patra, Donald S. Fussell	Fully asynchronous, robust, high-throughput arithmetic structures.	VLSI Design	1995	DBLP DOI BibTeX RDF	fully asynchronous structures, high-throughput arithmetic structures, bit serial adders, scaleability, VLSI, digital arithmetic, asynchronous circuits, adders, integrated logic circuits, multiplying circuits, RSA cryptosystems, delay-insensitive, bit serial multipliers
55	Akihisa Ohta, Tsuyoshi Isshiki, Hiroaki Kunieda	New FPGA Architecture for Bit-Serial Pipeline Datapath.	FCCM	1998	DBLP DOI BibTeX RDF
52	Gert Cauwenberghs	Bit-serial bidirectional A/D/A conversio.	ARVLSI	1995	DBLP DOI BibTeX RDF	digital-analogue conversion, bidirectional bit-serial convertor, algorithmic DAC conversion, successive approximation ADC, D/A conversion, fault-tolerant VLSI architecture, matched monotonic characteristics, 200 muW, 20 mus, VLSI, CMOS integrated circuits, analogue-digital conversion, integrated circuit reliability, A/D conversion, 2 micron, CMOS process
52	S. M. Mortazavi Zanjani, Somayyeh Rahimian Omam, Seid Mehdi Fakhraie, Omid Shoaei	Experimental Evaluation of Different Realizations of Recursive CIC Filters.	CCECE	2006	DBLP DOI BibTeX RDF
52	Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang	A bit-serial approximate min-sum LDPC decoder and FPGA implementation.	ISCAS	2006	DBLP DOI BibTeX RDF
52	Alex Carreira, Trevor W. Fox, Laurence E. Turner	A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBitsTM.	FPL	2002	DBLP DOI BibTeX RDF
50	Florian Dittmann 0001, Achim Rettberg, Raphael Weber	Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture.	SBCCI	2007	DBLP DOI BibTeX RDF	optimization, high-level synthesis, bit-serial architecture
50	Soonhak Kwon, Heuisu Ryu	Efficient Bit Serial Multiplication in GF(2m) for a Class of Finite Fields.	ICOIN	2003	DBLP DOI BibTeX RDF	bit serial multiplication, optimal normal basis of type II, Finite field, dual basis, all one polynomial
49	Richard C. North, Walter H. Ku	beta-bit serial/parallel multipliers.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF
46	Makoto Motegi, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi 0001	Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis.	PPSN	2002	DBLP DOI BibTeX RDF
44	Brian M. H. Li, Philip Heng Wai Leong	Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	FPGA, motion estimation, video compression, bit serial, systolic
44	Jae-Jin Lee, Gi-Yong Song	Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier.	FPGA	2004	DBLP DOI BibTeX RDF
43	Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann 0001, Christophe Bobda	A New Approach of a Self-Timed Bit-Serial Synchronous Pipeline Architecture.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
43	Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis	Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register.	IOLTW	2002	DBLP DOI BibTeX RDF
43	Tsuyoshi Isshiki, Akihisa Ohta, T. Watanabe, T. Nakada, K. Akahane, I. Sisla, Dongju Li, Hiroaki Kunieda	High density bit-serial FPGA with LUT embedding shift register function.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
43	Richard I. Hartley, Jeffrey R. Jasica	Behavioral to structural translation in a bit-serial silicon compiler.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
41	R. S. Hogg, W. I. Hughes, David W. Lloyd	A Novel Asynchronous ALU for Massively Parallel Architectures.	PDP	1996	DBLP DOI BibTeX RDF	novel asynchronous ALU, self timed asynchronous bit serial massively parallel architecture, fixed word length, small magnitude data, self timed communication techniques, self timed single instruction systolic array, ST-SISA, self timed delay insensitive techniques, parallel architectures, systolic arrays, asynchronous circuits, clock skew, massively parallel architectures, clocked control, arithmetic logic unit
41	Mohammad Reza Hosseiny Fatemi, Hasan F. Ates, Rosli Salleh	A Cost-Efficient Bit-Serial Architecture for Sub-pixel Motion Estimation of H.264/AVC.	IIH-MSP	2008	DBLP DOI BibTeX RDF	Sub-pixel Motion estimation, VLSI, Video Compression, Bit-serial Architecture
41	Heiner Giefers, Achim Rettberg	Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture.	SBCCI	2006	DBLP DOI BibTeX RDF	high-level synthesis, low power design, voltage scaling, bit-serial architecture
41	Bing Bing Zhou	A New Bit-Serial Systolic Multiplier Over GF(2m).	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	bit-serial systolic multiplier, VLSI, logic design, cellular arrays, linear systolic array
41	In-Shek Hsu, Irving S. Reed, Trieu-Kien Truong, Ke Wang, Chiunn-Shyong Ye, Leslie J. Deutsch	The VLSI Implementation of a Reed-Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	Berlekamp's bit-serial multiplier, VLSI, trace, Reed-Solomon code, dual basis
41	Kenneth E. Batcher	Bit-Serial Parallel Processing Systems.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	radar processing, Airborne processors, bit-serial processors, custom VLSI chips, multidimensional access, image processing, parallel processors
41	Yun-Chen Lo, Ren-Shuo Liu	Bit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference.	DAC	2023	DBLP DOI BibTeX RDF
40	Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong	A systolic multiplier with LSB first algorithm over GF(2m) which is as efficient as the one with MSB first algorithm.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
37	Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny	High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link.	ASYNC	2007	DBLP DOI BibTeX RDF
35	Ocean Y. H. Cheung, Kuen Hung Tsoi, Philip Heng Wai Leong, Monk-Ping Leong	Tradeoffs in Parallel and Serial Implementations of the International Data Encryption Algorithm IDEA.	CHES	2001	DBLP DOI BibTeX RDF	performance-tradeoffs, reconfigurable-computing, digital-design, Cryptographic hardware
35	Florian Dittmann 0001, Achim Rettberg, Raphael Weber	Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture.	EUC	2005	DBLP DOI BibTeX RDF
35	Kiyoshi Oguri, Yuichiro Shibata, Akira Nagoya	Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
35	Chang Hoon Kim, Soonhak Kwon, Chun Pyo Hong, In-Gil Nam	Efficient bit-serial systolic array for division over GF(2m).	ISCAS (2)	2003	DBLP DOI BibTeX RDF
35	Soonhak Kwon	Low Complexity Bit Serial Systolic Multipliers over GF(2m) for Three Classes of Finite Fields.	ICICS	2002	DBLP DOI BibTeX RDF	systolic multiplier, finite field, basis, all one polynomial
35	Johann Großschädl	A low-power bit-serial multiplier for finite fields GF(2m).	ISCAS (4)	2001	DBLP DOI BibTeX RDF
35	Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos	On Accumulator-Based Bit-Serial Test Response Compaction Schemes.	ISQED	2001	DBLP DOI BibTeX RDF
35	Monk-Ping Leong, Ocean Y. H. Cheung, Kuen Hung Tsoi, Philip Heng Wai Leong	A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA.	FCCM	2000	DBLP DOI BibTeX RDF
35	Katsuharu Suzuki, Michael X. Wang, Zhao Fang, Wayne Wei-Ming Dai	Design of C++ Class Library and Bit-Serial Compiler for Variable-Precision Datapath Synthesis on Adaptive Computing Systems.	FCCM	2000	DBLP DOI BibTeX RDF
34	Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny	Fast Asynchronous Shift Register for Bit-Serial Communication.	ASYNC	2006	DBLP DOI BibTeX RDF
34	Sorin Cotofana, Stamatis Vassiliadis	delta-Bit serial binary addition with linear threshold networks.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
34	R. Gnanasekaran	On a Bit-Serial Input and Bit-Serial Output Multiplier.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	two's complement number representation, Add-shift multiplier, bit-sequential multiplier, on-line multiplication, carry-save addition
33	Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama	High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph.	ISVLSI	2002	DBLP DOI BibTeX RDF	FPGA, Reconfigurable processor, Two-dimensional array, Bit-serial architecture
33	Ross Smith, Karl Fant, Dave Parker, Rick Stephani, Ching-Yi Wang	An Asynchronous 2-D Discrete Cosine Transform Chip.	ASYNC	1998	DBLP DOI BibTeX RDF	DCT, asynchronous, threshold logic, bit-serial
33	R. S. Hogg, David W. Lloyd, W. I. Hughes	Self-Timed Communication Strategies for Massively Parallel Systolic Architectures.	CONPAR	1994	DBLP DOI BibTeX RDF	Scalable, Elastic, Massively-Parallel, Self-timing, Bit-serial
33	Hussein M. Alnuweiri, Viktor K. Prasanna	Fast Image Labeling Using Local Operators on Mesh-Connected Computers.	IEEE Trans. Pattern Anal. Mach. Intell.	1991	DBLP DOI BibTeX RDF	bit-serial processors, local operators, asymptotic time complexity, very fast shift registers, parallel algorithm, parallel algorithms, computational complexity, computational complexity, parallel architectures, parallel architectures, computerised picture processing, computerised picture processing, stacks, communication links, mesh-connected computers, image labeling
30	Siqi He, Hongyi Zhang, Mengjie Li, Haozhe Zhu, Chixiao Chen, Qi Liu 0010, Xiaoyang Zeng	Bit-Offsetter: A Bit-serial DNN Accelerator with Weight-offset MAC for Bit-wise Sparsity Exploitation.	AICAS	2023	DBLP DOI BibTeX RDF
30	Sora Isobe, Yoichi Tomioka	Low-bit Quantized CNN Acceleration based on Bit-serial Dot Product Unit with Zero-bit Skip.	CANDAR	2020	DBLP DOI BibTeX RDF
29	Victor Y. Pan, John H. Reif	On the Bit-Complexity of Discrete Solutions of PDEs: Compact Multigrid.	ICALP	1990	DBLP DOI BibTeX RDF
29	Zih-Heng Chen, Ming-Haw Jing, Jian-Hong Chen, Yaotsu Chang	New viewpoint of bit-serial/parallel normal basis multipliers using irreducible all-one polynomial.	ISCAS	2006	DBLP DOI BibTeX RDF
27	Miguel Morales-Sandoval, Claudia Feregrino Uribe, Paraskevas Kitsos	Bit-serial and digit-serial GF(2m)Montgomery multipliers using linear feedback shift registers.	IET Comput. Digit. Tech.	2011	DBLP DOI BibTeX RDF
27	Paraskevas Kalivas, Kiamal Z. Pekmestzi, Paul Bougas, Andreas Tsirikos, Kostas Gotsis	Low-latency and high-efficiency bit serial-serial multipliers.	EUSIPCO	2004	DBLP BibTeX RDF
26	Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann 0001, Ulrich Dierkes, Carsten Rustemeier	Control Development for Mechatronic Systems with a Fully Reconfigurable Pipeline Architecture.	SBCCI	2003	DBLP DOI BibTeX RDF
26	Oscar Gustafsson, Lars Wanhammar	Implementation of maximally fast ladder wave digital filters using a numerically equivalent state-space representation.	ISCAS (3)	1999	DBLP DOI BibTeX RDF
26	Raphael Weber, Achim Rettberg	Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture.	ARC	2009	DBLP DOI BibTeX RDF
26	Tim Kaulmann, Deniz Dikmen, Ulrich Rückert 0001	A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation.	HIS	2007	DBLP DOI BibTeX RDF
26	Pawel Garstecki, Adam Luczak, Marta Stepniewska	A bit-serial implementation of mode decision algorithm for AVC encoders.	ISCAS	2006	DBLP DOI BibTeX RDF
26	Amir K. Daneshbeh, M. Anwarul Hasan	A Class of Unidirectional Bit Serial Systolic Architectures for Multiplicative Inversion and Division over GF(2m).	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	field arithmetic, finite fields, systolic arrays, Division, inversion, extended Euclidean algorithm
26	E. Chaniotakis, Paraskevas Kalivas, Kiamal Z. Pekmestzi	Long Number Bit-Serial Squarers.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
26	Kenny Johansson, Oscar Gustafsson, Lars Wanhammar	Low-complexity bit-serial constant-coefficient multipliers.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
26	Florian Dittmann 0001, Achim Rettberg, Thomas Lehmann 0001, Mauro Cesar Zanella	Invariants for Distributed Local Control Elements of a New Synchronous Bit-Serial Architecture.	DELTA	2004	DBLP DOI BibTeX RDF
26	Achim Rettberg, Florian Dittmann 0001, Mauro Cesar Zanella, Thomas Lehmann 0001	Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures.	SBCCI	2003	DBLP DOI BibTeX RDF
26	Amir K. Daneshbeh, M. Anwarul Hasan	A Unidirectional Bit Serial Systolic Architecture for Double-Basis Division over GF(2m).	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
26	Hyun-Sung Kim 0001, Kee-Young Yoo	Bit-Serial AOP Arithmetic Architectures over GF (2m).	InfraSec	2002	DBLP DOI BibTeX RDF
26	Shoji Kawahito, Tatsuya Eki, Yoshiaki Tadokoro	A bit-serial column parallel processing architecture for on-sensor discrete Fourier transform.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
26	Sebastian T. J. Fenn, Michael Gössel, Mohammed Benaissa, David Taylor	On-Line Error Detection for Bit-Serial Multipliers in GF(2m).	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	finite fields, multipliers, parity checking, on-line error detection
25	Ciaran Toal, Sakir Sezer	The Implementation of Scalable ATM Frame Delineation Circuits.	ICT	2004	DBLP DOI BibTeX RDF
24	Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet	Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing
24	Johann Großschädl, Erkay Savas, Kazim Yumbul	Realizing Arbitrary-Precision Modular Multiplication with a Fixed-Precision Multiplier Datapath.	ReConFig	2009	DBLP DOI BibTeX RDF	Bit-serial multiplier architecture, Scalability, Montgomery modular multiplication
24	Nobuaki Okada, Michitaka Kameyama	Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells.	ISMVL	2008	DBLP DOI BibTeX RDF	Field-programmable VLSI, Multiple-valued source-coupled logic, Differential-Pair circuit, Bit-serial architecture
24	Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck	A self-organizing defect tolerant SIMD architecture.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	Self-organizing, SIMD, data parallel, DNA, defect tolerance, nanocomputing, bit-serial
24	Sandeep S. Kumar, Thomas J. Wollinger, Christof Paar	Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	least significant digit multiplier, elliptic/hyperelliptic curve cryptography, public key cryptography, digit serial multiplier, Bit serial multiplier
24	Jaidev P. Patwardhan, Vijeta Johri, Chris Dwyer, Alvin R. Lebeck	A defect tolerant self-organizing nanoscale SIMD architecture.	ASPLOS	2006	DBLP DOI BibTeX RDF	self-organizing, SIMD, data parallel, DNA, defect tolerance, nanocomputing, bit-serial
24	A. S. Nepomniaschaya	An Associative Parallel Algorithm for Finding a Critical Cycle in Directed Graphs.	ICPADS	2000	DBLP DOI BibTeX RDF	Directed weighted graph, critical cycle, optimum branching, bit-serial processing, associative parallel processor, time complexity
24	Adger E. Harvin III, José G. Delgado-Frias	A Dictionary Machine Emulation on a VLSI Computing Tree System.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	tree architectures, VLSI, data structure, pipeline computing, bit-serial, Dictionary machines
24	Alain Mérigot	Associative Nets: A Graph-Based Parallel Computing Net.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF	bit-serial arithmetic, graph processing, parallel algorithms, SIMD, fine grain parallelism, Parallel programming models, asynchronous logic
24	M. Anwarul Hasan, Vijay K. Bhargava	Architecture for a Low Complexity Rate-Adaptive Reed-Solomon Encoder.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	Bit-serial structure, rate-adaptive Reed-Solomon encoder, triangular basis, finite field multiplication, generator polynomial
24	Jean Vuillemin	On Circuits and Numbers.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	PROM, 2-adic integers, synchronous decision diagrams, BDD constructs, bit-serial circuits, reset signals, 2Z, arithmetic synthesis f, periodic binary constants, deeply binding synchronous enable, combinational circuit semantics, arbitrary precision, programmable active memories, specification languages, sequential circuits, combinational circuits, digital arithmetic, logic CAD, adders, digital circuits, arithmetic, combinatorial circuits, synchronous circuits, continuous functions, rational numbers
24	Veljko M. Milutinovic, Mark Bettinger, Walter A. Helbig	Multiplier/Shifter Design Tradeoffs in a 32-bit Microprocessor.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	full barrel shifter, large register file, GaAs microprocessor, logic design, microprocessors, microprocessor chips, design tradeoffs, 32 bits, single chip, bit-serial multiplier
24	Alok Parmar, Kailash Prasad, Nanditha P. Rao, Joycee Mekie	An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory Computing for DNNs.	ISCAS	2022	DBLP DOI BibTeX RDF
24	Khalid Al-Hawaj, Olalekan Afuye, Shady Agwa, Alyssa B. Apsel, Christopher Batten	Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM.	ISCAS	2020	DBLP DOI BibTeX RDF
24	Mojtaba Gholamnia Roshan, Mohammad Gholami	4-Bit serial shift register with reset ability and 4-bit LFSR in QCA technology using minimum number of cells and delay.	Comput. Electr. Eng.	2019	DBLP DOI BibTeX RDF
24	Jérémy Jean, Amir Moradi 0001, Thomas Peyrin, Pascal Sasdrich	Bit-Sliding: A Generic Technique for Bit-Serial Implementations of SPN-based Primitives - Applications to AES, PRESENT and SKINNY.	IACR Cryptol. ePrint Arch.	2017	DBLP BibTeX RDF
24	Jérémy Jean, Amir Moradi 0001, Thomas Peyrin, Pascal Sasdrich	Bit-Sliding: A Generic Technique for Bit-Serial Implementations of SPN-based Primitives - Applications to AES, PRESENT and SKINNY.	CHES	2017	DBLP DOI BibTeX RDF
24	Kazuya Tanigawa, Ken'ichi Umeda, Tetsuo Hironaka	Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor.	ARC	2010	DBLP DOI BibTeX RDF
24	Arash Hariri, Arash Reyhani-Masoleh	Bit-Serial and Bit-Parallel Montgomery Multiplication and Squaring over GF(2^m).	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
24	Krishna M. Sivalingam	A Comparison of Bit-Parallel and Bit-Serial Architectures for WDM Networks.	Photonic Netw. Commun.	1999	DBLP DOI BibTeX RDF
24	Anders Åström, Michael Hall, Anders Edman	A comparison of bit-serial and multi-bit processor elements in a real-time signal processing SIMD architecture.	HiPC	1996	DBLP DOI BibTeX RDF
24	David Crook, John Fulcher	A Comparison of Bit Serial and Bit Parallel DCT Designs.	VLSI Design	1995	DBLP DOI BibTeX RDF
23	Vijay Sundararajan, Keshab K. Parhi	Reducing bus transition activity by limited weight coding with codeword slimming.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
23	Huy T. Nguyen, Abhijit Chatterjee, Rabindra K. Roy	Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
23	Siavash Bayat Sarmadi, M. Anwar Hasan	On Concurrent Detection of Errors in Polynomial Basis Multiplication.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
23	Tamás Szabó, Lörinc Antoni, Gábor Horváth 0001, Béla Fehér	A Full-Parallel Digital Implementation for Pre-Trained NNs.	IJCNN (2)	2000	DBLP DOI BibTeX RDF
23	M. Yan, John V. McCanny, Yi Hu	VLSI architectures for vector quantization.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
23	Alex Fit-Florea, Lun Li, Mitchell A. Thornton, David W. Matula	A Discrete Logarithm Number System for Integer Arithmetic Modulo 2k: Algorithms and Lookup Structures.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
21	Junfeng Fan, Lejla Batina, Ingrid Verbauwhede	Light-weight implementation options for curve-based cryptography: HECC is also ready for RFID.	ICITST	2009	DBLP DOI BibTeX RDF
21	Magnus Karlsson, Mark Vesterbacka	Digit-serial/parallel multipliers with improved throughput and latency.	ISCAS	2006	DBLP DOI BibTeX RDF