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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 240 occurrences of 159 keywords
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Results
Found 418 publication records. Showing 418 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
82 | Arash Reyhani-Masoleh |
A New Bit-Serial Architecture for Field Multiplication Using Polynomial Bases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2008, 10th International Workshop, Washington, D.C., USA, August 10-13, 2008. Proceedings, pp. 300-314, 2008, Springer, 978-3-540-85052-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Finite or Galois field, Mastrovito multiplier, polynomial basis, bit-serial multiplier |
67 | Soonhak Kwon, Heuisu Ryu |
Efficient Bit Serial Multiplication Using Optimal Normal Bases of Type II in GF (2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISC ![In: Information Security, 5th International Conference, ISC 2002 Sao Paulo, Brazil, September 30 - October 2, 2002, Proceedings, pp. 300-308, 2002, Springer, 3-540-44270-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
bit serial multiplication, optimal normal basis of type II, Finite field, dual basis |
64 | Dan Cyca, Laurence E. Turner |
Bit-Serial Digital Filter Implementation using a Custom C Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 534-537, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
62 | Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor |
FPGA-Based Structures for On-Line FFT and DCT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 310-311, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
FPGA, interconnect, MAC, FFT, signal processing, DCT, online, on-line, distributed arithmetic, bit-serial, xilinx, on-line arithmetic |
62 | Leilei Song, Keshab K. Parhi |
Efficient Finite Field Serial/Parallel Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 72-, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
finite field serial/parallel multiplication, finite field arithmetic architectures, bit-serial/parallel finite field multiplier, standard basis representation, optimal primitive polynomials, minimum hardware complexity, semi-systolic architecture, computational complexity, cryptography, cryptography, encoding, digital arithmetic, polynomials, multiplying circuits, VLSI implementation, coding theory |
58 | Yong Ho Hwang, Sang Gyoo Sim, Pil Joong Lee |
Bit-Serial Multipliers for Exponentiation and Division in GF(2m) Using Irreducible AOP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (1) ![In: Computational Science and Its Applications - ICCSA 2004, International Conference, Assisi, Italy, May 14-17, 2004, Proceedings, Part I, pp. 442-450, 2004, Springer, 3-540-22054-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Irreducible AOP, Finite field, Exponentiation, Bit-serial multiplier |
58 | Johann Großschädl |
A Bit-Serial Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2001, Third International Workshop, Paris, France, May 14-16, 2001, Proceedings, pp. 202-219, 2001, Springer, 3-540-42521-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
iterative modulo multiplication, polynomial basis representation, bit-serial multiplier architecture, smart card crypto-coprocessor, Elliptic curve cryptography, finite field arithmetic |
58 | S. A. Rahim, Laurence E. Turner |
A Field Programmable Bit-Serial Digital Signal Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 19-21 July 2004, Banff, Alberta, Canada, pp. 295-298, 2004, IEEE Computer Society, 0-7695-2182-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
56 | Priyadarsan Patra, Donald S. Fussell |
Fully asynchronous, robust, high-throughput arithmetic structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 141-145, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
fully asynchronous structures, high-throughput arithmetic structures, bit serial adders, scaleability, VLSI, digital arithmetic, asynchronous circuits, adders, integrated logic circuits, multiplying circuits, RSA cryptosystems, delay-insensitive, bit serial multipliers |
55 | Akihisa Ohta, Tsuyoshi Isshiki, Hiroaki Kunieda |
New FPGA Architecture for Bit-Serial Pipeline Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, pp. 58-67, 1998, IEEE Computer Society, 0-8186-8900-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
52 | Gert Cauwenberghs |
Bit-serial bidirectional A/D/A conversio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 108-120, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
digital-analogue conversion, bidirectional bit-serial convertor, algorithmic DAC conversion, successive approximation ADC, D/A conversion, fault-tolerant VLSI architecture, matched monotonic characteristics, 200 muW, 20 mus, VLSI, CMOS integrated circuits, analogue-digital conversion, integrated circuit reliability, A/D conversion, 2 micron, CMOS process |
52 | S. M. Mortazavi Zanjani, Somayyeh Rahimian Omam, Seid Mehdi Fakhraie, Omid Shoaei |
Experimental Evaluation of Different Realizations of Recursive CIC Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1056-1059, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
52 | Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang |
A bit-serial approximate min-sum LDPC decoder and FPGA implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
52 | Alex Carreira, Trevor W. Fox, Laurence E. Turner |
A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBitsTM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 222-231, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
50 | Florian Dittmann 0001, Achim Rettberg, Raphael Weber |
Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 153-158, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
optimization, high-level synthesis, bit-serial architecture |
50 | Soonhak Kwon, Heuisu Ryu |
Efficient Bit Serial Multiplication in GF(2m) for a Class of Finite Fields. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICOIN ![In: Information Networking, Networking Technologies for Enhanced Internet Services International Conference, ICOIN 2003, Cheju Island, Korea, February 12-14, 2003, Revised Selected Papers, pp. 762-771, 2003, Springer, 3-540-40827-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
bit serial multiplication, optimal normal basis of type II, Finite field, dual basis, all one polynomial |
49 | Richard C. North, Walter H. Ku |
beta-bit serial/parallel multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 2(4), pp. 219-233, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
46 | Makoto Motegi, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi 0001 |
Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPSN ![In: Parallel Problem Solving from Nature - PPSN VII, 7th International Conference, Granada, Spain, September 7-11, 2002, Proceedings, pp. 831-840, 2002, Springer, 3-540-44139-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
44 | Brian M. H. Li, Philip Heng Wai Leong |
Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 51(1), pp. 77-98, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, motion estimation, video compression, bit serial, systolic |
44 | Jae-Jin Lee, Gi-Yong Song |
Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 249, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann 0001, Christophe Bobda |
A New Approach of a Self-Timed Bit-Serial Synchronous Pipeline Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 9-11 June 2003, San Diego, CA, USA, pp. 71-77, 2003, IEEE Computer Society, 0-7695-1943-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
43 | Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis |
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, pp. 152-157, 2002, IEEE Computer Society, 0-7695-1641-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
43 | Tsuyoshi Isshiki, Akihisa Ohta, T. Watanabe, T. Nakada, K. Akahane, I. Sisla, Dongju Li, Hiroaki Kunieda |
High density bit-serial FPGA with LUT embedding shift register function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (1) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 475-480, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
43 | Richard I. Hartley, Jeffrey R. Jasica |
Behavioral to structural translation in a bit-serial silicon compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8), pp. 877-886, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
41 | R. S. Hogg, W. I. Hughes, David W. Lloyd |
A Novel Asynchronous ALU for Massively Parallel Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), January 24-26, 1996, Portugal, pp. 282-289, 1996, IEEE Computer Society, 0-8186-7376-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
novel asynchronous ALU, self timed asynchronous bit serial massively parallel architecture, fixed word length, small magnitude data, self timed communication techniques, self timed single instruction systolic array, ST-SISA, self timed delay insensitive techniques, parallel architectures, systolic arrays, asynchronous circuits, clock skew, massively parallel architectures, clocked control, arithmetic logic unit |
41 | Mohammad Reza Hosseiny Fatemi, Hasan F. Ates, Rosli Salleh |
A Cost-Efficient Bit-Serial Architecture for Sub-pixel Motion Estimation of H.264/AVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IIH-MSP ![In: 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2008), Harbin, China, 15-17 August 2008, Proceedings, pp. 818-821, 2008, IEEE Computer Society, 978-0-7695-3278-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Sub-pixel Motion estimation, VLSI, Video Compression, Bit-serial Architecture |
41 | Heiner Giefers, Achim Rettberg |
Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 113-118, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
high-level synthesis, low power design, voltage scaling, bit-serial architecture |
41 | Bing Bing Zhou |
A New Bit-Serial Systolic Multiplier Over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(6), pp. 749-751, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
bit-serial systolic multiplier, VLSI, logic design, cellular arrays, linear systolic array |
41 | In-Shek Hsu, Irving S. Reed, Trieu-Kien Truong, Ke Wang, Chiunn-Shyong Ye, Leslie J. Deutsch |
The VLSI Implementation of a Reed-Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(10), pp. 906-911, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
Berlekamp's bit-serial multiplier, VLSI, trace, Reed-Solomon code, dual basis |
41 | Kenneth E. Batcher |
Bit-Serial Parallel Processing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(5), pp. 377-384, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
radar processing, Airborne processors, bit-serial processors, custom VLSI chips, multidimensional access, image processing, parallel processors |
41 | Yun-Chen Lo, Ren-Shuo Liu |
Bit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2348-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
40 | Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong |
A systolic multiplier with LSB first algorithm over GF(2m) which is as efficient as the one with MSB first algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 633-636, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny |
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 12-14 March 2006, Berkeley, California, USA, pp. 3-14, 2007, IEEE Computer Society, 978-0-7695-2771-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Ocean Y. H. Cheung, Kuen Hung Tsoi, Philip Heng Wai Leong, Monk-Ping Leong |
Tradeoffs in Parallel and Serial Implementations of the International Data Encryption Algorithm IDEA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2001, Third International Workshop, Paris, France, May 14-16, 2001, Proceedings, pp. 333-347, 2001, Springer, 3-540-42521-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
performance-tradeoffs, reconfigurable-computing, digital-design, Cryptographic hardware |
35 | Florian Dittmann 0001, Achim Rettberg, Raphael Weber |
Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing - EUC 2005, International Conference EUC 2005, Nagasaki, Japan, December 6-9, 2005, Proceedings, pp. 448-457, 2005, Springer, 3-540-30807-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Kiyoshi Oguri, Yuichiro Shibata, Akira Nagoya |
Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings, pp. 54-68, 2003, Springer, 3-540-20122-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Chang Hoon Kim, Soonhak Kwon, Chun Pyo Hong, In-Gil Nam |
Efficient bit-serial systolic array for division over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 252-255, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Soonhak Kwon |
Low Complexity Bit Serial Systolic Multipliers over GF(2m) for Three Classes of Finite Fields. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICS ![In: Information and Communications Security, 4th International Conference, ICICS 2002, Singapore, December 9-12, 2002, Proceedings, pp. 209-216, 2002, Springer, 3-540-00164-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
systolic multiplier, finite field, basis, all one polynomial |
35 | Johann Großschädl |
A low-power bit-serial multiplier for finite fields GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 37-40, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
35 | Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos |
On Accumulator-Based Bit-Serial Test Response Compaction Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 350-355, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
35 | Monk-Ping Leong, Ocean Y. H. Cheung, Kuen Hung Tsoi, Philip Heng Wai Leong |
A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 122-131, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
35 | Katsuharu Suzuki, Michael X. Wang, Zhao Fang, Wayne Wei-Ming Dai |
Design of C++ Class Library and Bit-Serial Compiler for Variable-Precision Datapath Synthesis on Adaptive Computing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 339-340, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny |
Fast Asynchronous Shift Register for Bit-Serial Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 117-127, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Sorin Cotofana, Stamatis Vassiliadis |
delta-Bit serial binary addition with linear threshold networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 14(3), pp. 249-264, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
34 | R. Gnanasekaran |
On a Bit-Serial Input and Bit-Serial Output Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(9), pp. 878-880, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
two's complement number representation, Add-shift multiplier, bit-sequential multiplier, on-line multiplication, carry-save addition |
33 | Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama |
High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 25-26 April 2002, Pittsburgh, PA, USA, pp. 95-100, 2002, IEEE Computer Society, 0-7695-1486-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FPGA, Reconfigurable processor, Two-dimensional array, Bit-serial architecture |
33 | Ross Smith, Karl Fant, Dave Parker, Rick Stephani, Ching-Yi Wang |
An Asynchronous 2-D Discrete Cosine Transform Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 224-, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
DCT, asynchronous, threshold logic, bit-serial |
33 | R. S. Hogg, David W. Lloyd, W. I. Hughes |
Self-Timed Communication Strategies for Massively Parallel Systolic Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 94 - VAPP VI, Third Joint International Conference on Vector and Parallel Processing, Linz, Austria, September 6-8, 1994, Proceedings, pp. 557-567, 1994, Springer, 3-540-58430-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
Scalable, Elastic, Massively-Parallel, Self-timing, Bit-serial |
33 | Hussein M. Alnuweiri, Viktor K. Prasanna |
Fast Image Labeling Using Local Operators on Mesh-Connected Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 13(2), pp. 202-207, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
bit-serial processors, local operators, asymptotic time complexity, very fast shift registers, parallel algorithm, parallel algorithms, computational complexity, computational complexity, parallel architectures, parallel architectures, computerised picture processing, computerised picture processing, stacks, communication links, mesh-connected computers, image labeling |
30 | Siqi He, Hongyi Zhang, Mengjie Li, Haozhe Zhu, Chixiao Chen, Qi Liu 0010, Xiaoyang Zeng |
Bit-Offsetter: A Bit-serial DNN Accelerator with Weight-offset MAC for Bit-wise Sparsity Exploitation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICAS ![In: 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2023, Hangzhou, China, June 11-13, 2023, pp. 1-5, 2023, IEEE, 979-8-3503-3267-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
30 | Sora Isobe, Yoichi Tomioka |
Low-bit Quantized CNN Acceleration based on Bit-serial Dot Product Unit with Zero-bit Skip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CANDAR ![In: Eighth International Symposium on Computing and Networking, CANDAR 2020, Naha, Japan, November 24-27, 2020, pp. 141-145, 2020, IEEE, 978-1-7281-8221-6. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
29 | Victor Y. Pan, John H. Reif |
On the Bit-Complexity of Discrete Solutions of PDEs: Compact Multigrid. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP ![In: Automata, Languages and Programming, 17th International Colloquium, ICALP90, Warwick University, England, UK, July 16-20, 1990, Proceedings, pp. 612-625, 1990, Springer, 3-540-52826-1. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
29 | Zih-Heng Chen, Ming-Haw Jing, Jian-Hong Chen, Yaotsu Chang |
New viewpoint of bit-serial/parallel normal basis multipliers using irreducible all-one polynomial. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Miguel Morales-Sandoval, Claudia Feregrino Uribe, Paraskevas Kitsos |
Bit-serial and digit-serial GF(2m)Montgomery multipliers using linear feedback shift registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 5(2), pp. 86-94, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
27 | Paraskevas Kalivas, Kiamal Z. Pekmestzi, Paul Bougas, Andreas Tsirikos, Kostas Gotsis |
Low-latency and high-efficiency bit serial-serial multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUSIPCO ![In: 2004 12th European Signal Processing Conference, Vienna, Austria, September 6-10, 2004, pp. 1345-1348, 2004, IEEE, 978-320-0001-65-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
26 | Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann 0001, Ulrich Dierkes, Carsten Rustemeier |
Control Development for Mechatronic Systems with a Fully Reconfigurable Pipeline Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pp. 231-236, 2003, IEEE Computer Society, 0-7695-2009-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Oscar Gustafsson, Lars Wanhammar |
Implementation of maximally fast ladder wave digital filters using a numerically equivalent state-space representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 419-422, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Raphael Weber, Achim Rettberg |
Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 330-335, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Tim Kaulmann, Deniz Dikmen, Ulrich Rückert 0001 |
A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HIS ![In: 7th International Conference on Hybrid Intelligent Systems, HIS 2007, Kaiserslautern, Germany, September 17-19, 2007, pp. 302-307, 2007, IEEE Computer Society, 0-7695-2946-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Pawel Garstecki, Adam Luczak, Marta Stepniewska |
A bit-serial implementation of mode decision algorithm for AVC encoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Amir K. Daneshbeh, M. Anwarul Hasan |
A Class of Unidirectional Bit Serial Systolic Architectures for Multiplicative Inversion and Division over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(3), pp. 370-380, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
field arithmetic, finite fields, systolic arrays, Division, inversion, extended Euclidean algorithm |
26 | E. Chaniotakis, Paraskevas Kalivas, Kiamal Z. Pekmestzi |
Long Number Bit-Serial Squarers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA, pp. 29-36, 2005, IEEE Computer Society, 0-7695-2366-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Kenny Johansson, Oscar Gustafsson, Lars Wanhammar |
Low-complexity bit-serial constant-coefficient multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 649-652, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Florian Dittmann 0001, Achim Rettberg, Thomas Lehmann 0001, Mauro Cesar Zanella |
Invariants for Distributed Local Control Elements of a New Synchronous Bit-Serial Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), 28-30 January 2004, Perth, Australia, pp. 245-250, 2004, IEEE Computer Society, 0-7695-2081-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Achim Rettberg, Florian Dittmann 0001, Mauro Cesar Zanella, Thomas Lehmann 0001 |
Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pp. 79-84, 2003, IEEE Computer Society, 0-7695-2009-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Amir K. Daneshbeh, M. Anwarul Hasan |
A Unidirectional Bit Serial Systolic Architecture for Double-Basis Division over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 15-18 June 2003, Santiago de Compostela, Spain, pp. 174-180, 2003, IEEE Computer Society, 0-7695-1894-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Hyun-Sung Kim 0001, Kee-Young Yoo |
Bit-Serial AOP Arithmetic Architectures over GF (2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
InfraSec ![In: Infrastructure Security, International Conference, InfraSec 2002 Bristol, UK, October 1-3, 2002, Proceedings, pp. 303-313, 2002, Springer, 3-540-44309-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Shoji Kawahito, Tatsuya Eki, Yoshiaki Tadokoro |
A bit-serial column parallel processing architecture for on-sensor discrete Fourier transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 738-741, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Sebastian T. J. Fenn, Michael Gössel, Mohammed Benaissa, David Taylor |
On-Line Error Detection for Bit-Serial Multipliers in GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(1), pp. 29-40, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
finite fields, multipliers, parity checking, on-line error detection |
25 | Ciaran Toal, Sakir Sezer |
The Implementation of Scalable ATM Frame Delineation Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICT ![In: Telecommunications and Networking - ICT 2004, 11th International Conference on Telecommunications, Fortaleza, Brazil, August 1-6, 2004, Proceedings, pp. 1047-1056, 2004, Springer, 3-540-22571-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet |
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 43-52, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing |
24 | Johann Großschädl, Erkay Savas, Kazim Yumbul |
Realizing Arbitrary-Precision Modular Multiplication with a Fixed-Precision Multiplier Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pp. 261-266, 2009, IEEE Computer Society, 978-0-7695-3917-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Bit-serial multiplier architecture, Scalability, Montgomery modular multiplication |
24 | Nobuaki Okada, Michitaka Kameyama |
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 180-185, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Field-programmable VLSI, Multiple-valued source-coupled logic, Differential-Pair circuit, Bit-serial architecture |
24 | Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck |
A self-organizing defect tolerant SIMD architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 3(2), pp. 10, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Self-organizing, SIMD, data parallel, DNA, defect tolerance, nanocomputing, bit-serial |
24 | Sandeep S. Kumar, Thomas J. Wollinger, Christof Paar |
Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(10), pp. 1306-1311, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
least significant digit multiplier, elliptic/hyperelliptic curve cryptography, public key cryptography, digit serial multiplier, Bit serial multiplier |
24 | Jaidev P. Patwardhan, Vijeta Johri, Chris Dwyer, Alvin R. Lebeck |
A defect tolerant self-organizing nanoscale SIMD architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 241-251, 2006, ACM, 1-59593-451-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
self-organizing, SIMD, data parallel, DNA, defect tolerance, nanocomputing, bit-serial |
24 | A. S. Nepomniaschaya |
An Associative Parallel Algorithm for Finding a Critical Cycle in Directed Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: Seventh International Conference on Parallel and Distributed Systems, ICPADS 2000, Iwate, Japan, July 4-7, 2000, pp. 455-462, 2000, IEEE Computer Society, 0-7695-0568-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Directed weighted graph, critical cycle, optimum branching, bit-serial processing, associative parallel processor, time complexity |
24 | Adger E. Harvin III, José G. Delgado-Frias |
A Dictionary Machine Emulation on a VLSI Computing Tree System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 134-139, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
tree architectures, VLSI, data structure, pipeline computing, bit-serial, Dictionary machines |
24 | Alain Mérigot |
Associative Nets: A Graph-Based Parallel Computing Net. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 46(5), pp. 558-571, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
bit-serial arithmetic, graph processing, parallel algorithms, SIMD, fine grain parallelism, Parallel programming models, asynchronous logic |
24 | M. Anwarul Hasan, Vijay K. Bhargava |
Architecture for a Low Complexity Rate-Adaptive Reed-Solomon Encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(7), pp. 938-942, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Bit-serial structure, rate-adaptive Reed-Solomon encoder, triangular basis, finite field multiplication, generator polynomial |
24 | Jean Vuillemin |
On Circuits and Numbers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(8), pp. 868-879, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
PROM, 2-adic integers, synchronous decision diagrams, BDD constructs, bit-serial circuits, reset signals, 2Z, arithmetic synthesis f, periodic binary constants, deeply binding synchronous enable, combinational circuit semantics, arbitrary precision, programmable active memories, specification languages, sequential circuits, combinational circuits, digital arithmetic, logic CAD, adders, digital circuits, arithmetic, combinatorial circuits, synchronous circuits, continuous functions, rational numbers |
24 | Veljko M. Milutinovic, Mark Bettinger, Walter A. Helbig |
Multiplier/Shifter Design Tradeoffs in a 32-bit Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(6), pp. 874-881, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
full barrel shifter, large register file, GaAs microprocessor, logic design, microprocessors, microprocessor chips, design tradeoffs, 32 bits, single chip, bit-serial multiplier |
24 | Alok Parmar, Kailash Prasad, Nanditha P. Rao, Joycee Mekie |
An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory Computing for DNNs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 2948-2952, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Khalid Al-Hawaj, Olalekan Afuye, Shady Agwa, Alyssa B. Apsel, Christopher Batten |
Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-3320-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Mojtaba Gholamnia Roshan, Mohammad Gholami |
4-Bit serial shift register with reset ability and 4-bit LFSR in QCA technology using minimum number of cells and delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 78, pp. 449-462, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Jérémy Jean, Amir Moradi 0001, Thomas Peyrin, Pascal Sasdrich |
Bit-Sliding: A Generic Technique for Bit-Serial Implementations of SPN-based Primitives - Applications to AES, PRESENT and SKINNY. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2017, pp. 600, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
24 | Jérémy Jean, Amir Moradi 0001, Thomas Peyrin, Pascal Sasdrich |
Bit-Sliding: A Generic Technique for Bit-Serial Implementations of SPN-based Primitives - Applications to AES, PRESENT and SKINNY. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2017 - 19th International Conference, Taipei, Taiwan, September 25-28, 2017, Proceedings, pp. 687-707, 2017, Springer, 978-3-319-66786-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Kazuya Tanigawa, Ken'ichi Umeda, Tetsuo Hironaka |
Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010. Proceedings, pp. 388-393, 2010, Springer, 978-3-642-12132-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Arash Hariri, Arash Reyhani-Masoleh |
Bit-Serial and Bit-Parallel Montgomery Multiplication and Squaring over GF(2^m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 58(10), pp. 1332-1345, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Krishna M. Sivalingam |
A Comparison of Bit-Parallel and Bit-Serial Architectures for WDM Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Photonic Netw. Commun. ![In: Photonic Netw. Commun. 1(1), pp. 89-103, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Anders Åström, Michael Hall, Anders Edman |
A comparison of bit-serial and multi-bit processor elements in a real-time signal processing SIMD architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: 3rd International Conference on High Performance Computing, HIPC 1996, Proceedings, Trivandrum, India, 19-22 December, 1996, pp. 245-250, 1996, IEEE Computer Society, 0-8186-7557-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
24 | David Crook, John Fulcher |
A Comparison of Bit Serial and Bit Parallel DCT Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 3(1), pp. 59-65, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
23 | Vijay Sundararajan, Keshab K. Parhi |
Reducing bus transition activity by limited weight coding with codeword slimming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000, pp. 13-16, 2000, ACM, 1-58113-251-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
23 | Huy T. Nguyen, Abhijit Chatterjee, Rabindra K. Roy |
Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 18(1), pp. 25-38, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
23 | Siavash Bayat Sarmadi, M. Anwar Hasan |
On Concurrent Detection of Errors in Polynomial Basis Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(4), pp. 413-426, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Tamás Szabó, Lörinc Antoni, Gábor Horváth 0001, Béla Fehér |
A Full-Parallel Digital Implementation for Pre-Trained NNs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN (2) ![In: Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, IJCNN 2000, Neural Computing: New Challenges and Perspectives for the New Millennium, Como, Italy, July 24-27, 2000, Volume 2, pp. 49-54, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
23 | M. Yan, John V. McCanny, Yi Hu |
VLSI architectures for vector quantization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 10(1), pp. 5-23, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
23 | Alex Fit-Florea, Lun Li, Mitchell A. Thornton, David W. Matula |
A Discrete Logarithm Number System for Integer Arithmetic Modulo 2k: Algorithms and Lookup Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 58(2), pp. 163-174, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Junfeng Fan, Lejla Batina, Ingrid Verbauwhede |
Light-weight implementation options for curve-based cryptography: HECC is also ready for RFID. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICITST ![In: Proceedings of the 4th International Conference for Internet Technology and Secured Transactions, ICITST 2009, London, UK, November 9-12, 2009, pp. 1-6, 2009, IEEE, 978-1-4244-5648-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Magnus Karlsson, Mark Vesterbacka |
Digit-serial/parallel multipliers with improved throughput and latency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
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