Search results for "carry-chain"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
50	Andrea Lodi 0002, Carlo Chiesa, Fabio Campi, Mario Toma	A flexible LUT-based carry chain for FPGAs.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
49	Michael T. Frederick, Arun K. Somani	Multi-Bit Carry Chains for High-Performance Reconfigurable Fabrics.	FPL	2006	DBLP DOI BibTeX RDF
46	Scott Hauck, Matthew M. Hosler, Thomas W. Fry	High-performance carry chains for FPGA's.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
46	Scott Hauck, Matthew M. Hosler, Thomas W. Fry	High-Performance Carry Chains for FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
44	Michael T. Frederick, Arun K. Somani	Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	carry chain, depth optimal mapping, logic chain
41	Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne	A novel FPGA logic block for improved arithmetic performance.	FPGA	2008	DBLP DOI BibTeX RDF	6.2 compressor, carry-chain, compressor tree, multi-operand addition, FPGA, arithmetic circuits
40	Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris	Fast adders in modern FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF
36	Michael J. Schulte, Kai Chirca, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis	A Low-Power Carry Skip Adder with Fast Saturation.	ASAP	2004	DBLP DOI BibTeX RDF
36	Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner	Variable delay ripple carry adder with carry chain interrupt detection.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
36	Tomás Lang, Javier D. Bruguera	Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition.	ICCD	1999	DBLP DOI BibTeX RDF	Most significant carry, prefix tree, carry look-ahead adder
31	Kai Chirca, Michael J. Schulte, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis	A Static Low-Power, High-Performance 32-bit Carry Skip Adder.	DSD	2004	DBLP DOI BibTeX RDF
31	Javier D. Bruguera, Tomás Lang	Multilevel reverse most-significant carry computation.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
23	Hong Diep Nguyen, Bogdan Pasca 0001, Thomas B. Preußer	FPGA-Specific Arithmetic Optimizations of Short-Latency Adders.	FPL	2011	DBLP DOI BibTeX RDF	carry-chain, carry-select, carry-increment, FPGA, addition
23	Akhilesh Tyagi	A Reduced-Area Scheme for Carry-Select Adders.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	reduced-area, conditional-sum adders, carry-chain evaluations, gate-count, carry-ripple, classical carry-select, logic design, adders, logic circuits, gate-delay, parallel-prefix adders, analytic evaluation, area-efficient, carry-skip adders, carry-select adders
22	Michael T. Frederick, Arun K. Somani	Non-arithmetic carry chains for reconfigurable fabrics.	ICCD	2007	DBLP DOI BibTeX RDF
22	Radhika S. Grover, Weijia Shang, Qiang Li	A faster distributed arithmetic architecture for FPGAs.	FPGA	2002	DBLP DOI BibTeX RDF	DALUT, XC4000, carry propagation, cost-performance analysis, distributed arithmetic
21	Ayan Palchaudhuri, Anindya Sundar Dhar	FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation.	VLSID	2024	DBLP DOI BibTeX RDF
21	Robert B. Kent, Marios S. Pattichis	Use of Carry Chain Logic and Design System Extensions to Construct Significantly Faster and Larger Single-Stage N-Sorters and N-Filters.	IEEE Access	2022	DBLP DOI BibTeX RDF
21	Dam Minh Tung, Nguyen Van Toan, Jeong-Gun Lee	A Carry Chain-Based ADMFC Design on an FPGA for EMI Reduction and Noise Compensation.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
21	Ayan Palchaudhuri, Anindya Sundar Dhar	Fast Carry Chain Based Architectures for Two's Complement to CSD Recoding on FPGAs.	ARC	2018	DBLP DOI BibTeX RDF
21	Takashi Imagawa, Koki Honda, Hiroyuki Ochi	Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain.	SoCC	2017	DBLP DOI BibTeX RDF
21	Ana Petkovska, Grace Zgheib, David Novo, Muhsen Owaida, Alan Mishchenko, Paolo Ienne	Improved carry chain mapping for the VTR flow.	FPT	2015	DBLP DOI BibTeX RDF
21	Laurent-Stéphane Didier, Luc Jaulmes	Fast modulo 2n-1 and 2n;1 adder using carry-chain on FPGA.	ACSSC	2013	DBLP DOI BibTeX RDF
21	Zhidong Mao, Liguang Chen, Yuan Wang, Jinmei Lai	A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain.	ASICON	2011	DBLP DOI BibTeX RDF
21	Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne	An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF
21	Thomas B. Preußer, Rainer G. Spallek	Mapping basic prefix computations to fast carry-chain structures.	FPL	2009	DBLP DOI BibTeX RDF
21	Reza Hashemian	Design of a 54-bit adder using a modified Manchester carry chain.	Great Lakes Symposium on VLSI	1994	DBLP DOI BibTeX RDF
17	Varun Jindal, Alpana Agarwal	Carry Circuitry for LUT-Based FPGA.	VLSI Design	2004	DBLP DOI BibTeX RDF
13	Albert Danysh, Dimitri Tan	Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	data-path design, multiply-accumulate, Booth, Wallace, unsigned, multimedia, VLSI, Parallel, MAC, SIMD, vector, fixed-point, multiplier, high-speed arithmetic, signed, integer
13	Dimitri Tan, Albert Danysh, Michael J. Liebelt	Multiple-Precision Fixed-Point Vector Multiply-Accumulator Using Shared Segmentation.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
9	Feng Gang	Design of Modular Multiplier Based on Improved Montgomery Algorithm and Systolic Array.	IMSCCS (2)	2006	DBLP DOI BibTeX RDF
9	Alan Daly, William P. Marnane	Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic.	FPGA	2002	DBLP DOI BibTeX RDF	FPGA, encryption, RSA, public key, exponentiation, modular multiplication, montgomery
9	Atul Garg, Y. L. Le Coz, Hans J. Greub, R. B. Iverson, Robert F. Philhower, Pete M. Campbell, Cliff A. Maier, Sam A. Steidl, Matthew W. Ernest, Russell P. Kraft, Steven R. Carlough, J. W. Perry, Thomas W. Krawczyk Jr., John F. McDonald 0001	Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF