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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 34 occurrences of 32 keywords
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Results
Found 33 publication records. Showing 33 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
50 | Andrea Lodi 0002, Carlo Chiesa, Fabio Campi, Mario Toma |
A flexible LUT-based carry chain for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 133-136, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
49 | Michael T. Frederick, Arun K. Somani |
Multi-Bit Carry Chains for High-Performance Reconfigurable Fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-6, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Scott Hauck, Matthew M. Hosler, Thomas W. Fry |
High-performance carry chains for FPGA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(2), pp. 138-147, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
46 | Scott Hauck, Matthew M. Hosler, Thomas W. Fry |
High-Performance Carry Chains for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998, pp. 223-233, 1998, ACM, 0-89791-978-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
44 | Michael T. Frederick, Arun K. Somani |
Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 37-46, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
carry chain, depth optimal mapping, logic chain |
41 | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
A novel FPGA logic block for improved arithmetic performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 171-180, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
6.2 compressor, carry-chain, compressor tree, multi-operand addition, FPGA, arithmetic circuits |
40 | Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris |
Fast adders in modern FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 250, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Michael J. Schulte, Kai Chirca, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis |
A Low-Power Carry Skip Adder with Fast Saturation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2004), 27-29 September 2004, Galveston, TX, USA, pp. 269-279, 2004, IEEE Computer Society, 0-7695-2226-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner |
Variable delay ripple carry adder with carry chain interrupt detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 113-116, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Tomás Lang, Javier D. Bruguera |
Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 73-79, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Most significant carry, prefix tree, carry look-ahead adder |
31 | Kai Chirca, Michael J. Schulte, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis |
A Static Low-Power, High-Performance 32-bit Carry Skip Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France, pp. 615-619, 2004, IEEE Computer Society, 0-7695-2203-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Javier D. Bruguera, Tomás Lang |
Multilevel reverse most-significant carry computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(6), pp. 959-962, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
23 | Hong Diep Nguyen, Bogdan Pasca 0001, Thomas B. Preußer |
FPGA-Specific Arithmetic Optimizations of Short-Latency Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece, pp. 232-237, 2011, IEEE Computer Society, 978-1-4577-1484-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
carry-chain, carry-select, carry-increment, FPGA, addition |
23 | Akhilesh Tyagi |
A Reduced-Area Scheme for Carry-Select Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(10), pp. 1163-1170, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
reduced-area, conditional-sum adders, carry-chain evaluations, gate-count, carry-ripple, classical carry-select, logic design, adders, logic circuits, gate-delay, parallel-prefix adders, analytic evaluation, area-efficient, carry-skip adders, carry-select adders |
22 | Michael T. Frederick, Arun K. Somani |
Non-arithmetic carry chains for reconfigurable fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 137-143, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Radhika S. Grover, Weijia Shang, Qiang Li |
A faster distributed arithmetic architecture for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002, pp. 31-39, 2002, ACM, 1-58113-452-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
DALUT, XC4000, carry propagation, cost-performance analysis, distributed arithmetic |
21 | Ayan Palchaudhuri, Anindya Sundar Dhar |
FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, VLSID 2024, Kolkata, India, January 6-10, 2024, pp. 617-622, 2024, IEEE, 979-8-3503-8440-6. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
21 | Robert B. Kent, Marios S. Pattichis |
Use of Carry Chain Logic and Design System Extensions to Construct Significantly Faster and Larger Single-Stage N-Sorters and N-Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 79689-79702, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Dam Minh Tung, Nguyen Van Toan, Jeong-Gun Lee |
A Carry Chain-Based ADMFC Design on an FPGA for EMI Reduction and Noise Compensation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 28(1), pp. 1950018:1-1950018:23, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Ayan Palchaudhuri, Anindya Sundar Dhar |
Fast Carry Chain Based Architectures for Two's Complement to CSD Recoding on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Applied Reconfigurable Computing. Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings, pp. 537-550, 2018, Springer, 978-3-319-78889-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Takashi Imagawa, Koki Honda, Hiroyuki Ochi |
Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017, pp. 80-85, 2017, IEEE, 978-1-5386-4034-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Ana Petkovska, Grace Zgheib, David Novo, Muhsen Owaida, Alan Mishchenko, Paolo Ienne |
Improved carry chain mapping for the VTR flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2015 International Conference on Field Programmable Technology, FPT 2015, Queenstown, New Zealand, December 7-9, 2015, pp. 80-87, 2015, IEEE, 978-1-4673-9091-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Laurent-Stéphane Didier, Luc Jaulmes |
Fast modulo 2n-1 and 2n;1 adder using carry-chain on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSSC ![In: 2013 Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, November 3-6, 2013, pp. 1155-1159, 2013, IEEE, 978-1-4799-2390-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
21 | Zhidong Mao, Liguang Chen, Yuan Wang, Jinmei Lai |
A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October 25-28, 2011, pp. 67-70, 2011, IEEE, 978-1-61284-192-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
21 | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 2(3), pp. 19:1-19:42, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Thomas B. Preußer, Rainer G. Spallek |
Mapping basic prefix computations to fast carry-chain structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 19th International Conference on Field Programmable Logic and Applications, FPL 2009, August 31 - September 2, 2009, Prague, Czech Republic, pp. 604-608, 2009, IEEE, 978-1-4244-3892-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Reza Hashemian |
Design of a 54-bit adder using a modified Manchester carry chain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, GLSV '94, Notre Dame, IN, USA, March 4-5, 1994, pp. 204-207, 1994, IEEE, 0-8186-5610-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
17 | Varun Jindal, Alpana Agarwal |
Carry Circuitry for LUT-Based FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 731-734, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Albert Danysh, Dimitri Tan |
Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(3), pp. 284-293, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
data-path design, multiply-accumulate, Booth, Wallace, unsigned, multimedia, VLSI, Parallel, MAC, SIMD, vector, fixed-point, multiplier, high-speed arithmetic, signed, integer |
13 | Dimitri Tan, Albert Danysh, Michael J. Liebelt |
Multiple-Precision Fixed-Point Vector Multiply-Accumulator Using Shared Segmentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 15-18 June 2003, Santiago de Compostela, Spain, pp. 12-19, 2003, IEEE Computer Society, 0-7695-1894-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Feng Gang |
Design of Modular Multiplier Based on Improved Montgomery Algorithm and Systolic Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMSCCS (2) ![In: Interdisciplinary and Multidisciplinary Research in Computer Science, IEEE CS Proceeding of the First International Multi-Symposium of Computer and Computational Sciences (IMSCCS|06), June 20-24, 2006, Zhejiang University, Hangzhou, China, Vol. 2, pp. 356-359, 2006, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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9 | Alan Daly, William P. Marnane |
Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002, pp. 40-49, 2002, ACM, 1-58113-452-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FPGA, encryption, RSA, public key, exponentiation, modular multiplication, montgomery |
9 | Atul Garg, Y. L. Le Coz, Hans J. Greub, R. B. Iverson, Robert F. Philhower, Pete M. Campbell, Cliff A. Maier, Sam A. Steidl, Matthew W. Ernest, Russell P. Kraft, Steven R. Carlough, J. W. Perry, Thomas W. Krawczyk Jr., John F. McDonald 0001 |
Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(2), pp. 212-219, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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