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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 397 occurrences of 299 keywords
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Results
Found 1969 publication records. Showing 1969 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
60 | Kuang Yung Liu |
Architecture for VLSI Design of Reed-Solomon Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(2), pp. 178-189, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
BCH decoders, finite field processors, Reed?Solomon decoders, parallel processing, VLSI, error-correcting codes, pipeline processing |
59 | Ahmad A. Hiasat |
VLSI implementation of new arithmetic residue to binary decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(1), pp. 153-158, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
56 | Marco Mattavelli, Sylvain Brunetton, Daniel Mlynek |
Computational Graceful Degradation for Video Sequence Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (1) ![In: Proceedings 1997 International Conference on Image Processing, ICIP '97, Santa Barbara, California, USA, October 26-29, 1997, pp. 330-333, 1997, IEEE Computer Society, 0-8186-8183-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
computational graceful degradation, video sequence decoding, software based video decoders, dedicated hardware real time systems, video/audio decoders, video compression standards, video/audio bitstreams processing, multimedia processors, compressed video sequences, H.263 video compression standard, video processor platform, interfaces, video coding, simulation results, real-time performance, main memory, IDCT, hardware platform |
55 | Aggelos Kiayias, Moti Yung |
On Crafty Pirates and Foxy Tracers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Digital Rights Management Workshop ![In: Security and Privacy in Digital Rights Management, ACM CCS-8 Workshop DRM 2001, Philadelphia, PA, USA, November 5, 2001, Revised Papers, pp. 22-39, 2001, Springer, 3-540-43677-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
50 | Alina Maor, Neri Merhav |
On Successive Refinement With Causal Side Information at the Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 54(1), pp. 332-343, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
50 | Matthew Collin Jordan, Ramachandran Vaidyanathan |
Configurable decoders with application in fast partial reconfiguration of FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 259, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, decoder, look-up table, configurable logic |
50 | Duong Hieu Phan |
Traitor Tracing for Stateful Pirate Decoders with Constant Ciphertext Rate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VIETCRYPT ![In: Progressin Cryptology - VIETCRYPT 2006, First International Conference on Cryptology in Vietnam, Hanoi, Vietnam, September 25-28, 2006, Revised Selected Papers, pp. 354-365, 2006, Springer, 3-540-68799-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
50 | Wei Qin, Sharad Malik |
Automated synthesis of efficient binary decoders for retargetable software toolkits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 764-769, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
binary decoder, decoding tree, decision tree, instruction set simulator |
50 | Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu 0002 |
Memory arrangements in turbo decoders using sliding-window BCJR algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 557-560, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
50 | Zhongfeng Wang, Hiroshi Suzuki, Keshab K. Parhi |
Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 29(3), pp. 209-221, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
adaptive decoding, MAP algorithm, VLSI implementation, turbo codes |
50 | Emil Gizdarski |
Detection of Delay Faults in Memory Address Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(4), pp. 381-387, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Built-In Self-Test, delay testing, stuck-open faults, RAM testing |
46 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan |
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(3), pp. 287-296, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
address decoders, memory testing, dynamic faults |
46 | Ming Su, Lili Zhou, C.-J. Richard Shi |
Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 636-643, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Min Li 0001, David Novo, Bruno Bougard, Frederik Naessens, Liesbet Van der Perre, Francky Catthoor |
An implementation friendly low complexity multiplierless LLR generator for soft MIMO sphere decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2008, October 8-10, 2008, Washington, D.C. Metro Area, USA, pp. 118-123, 2008, IEEE, 978-1-4244-2924-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Zhihang Yi, Il-Min Kim |
Joint optimization of relay-precoders and decoders with partial channel side information in cooperative networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Sel. Areas Commun. ![In: IEEE J. Sel. Areas Commun. 25(2), pp. 447-458, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Torben Brack, Matthias Alles, Timo Lehnigk-Emden, Frank Kienle, Norbert Wehn, Friedbert Berens, Andreas Ruegg |
A Survey on LDPC Codes and Decoders for OFDM-based UWB Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 65th IEEE Vehicular Technology Conference, VTC Spring 2007, 22-25 April 2007, Dublin, Ireland, pp. 1549-1553, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Ying Zhao, Yang Xiao |
A design of orthogonal interleavers for multimodes turbo en-decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3171-3174, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Mohammad M. Mansour, Naresh R. Shanbhag |
VLSI architectures for SISO-APP decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(4), pp. 627-650, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Felix Lustenberger, Hans-Andrea Loeliger |
On mismatch errors in analog-VLSI error correcting decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 198-201, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
37 | Khalid A. Darabkh, Backer N. Abu-Jaradeh |
Bounded Fano Decoders over Intermediate Hops Excluding Packet Retransmission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA ![In: 24th IEEE International Conference on Advanced Information Networking and Applications, AINA 2010, Perth, Australia, 20-13 April 2010, pp. 299-303, 2010, IEEE Computer Society, 978-0-7695-4018-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Fano decoders, upper and lower threshold limits, Pareto distribution and average queue size |
37 | Warren J. Gross, Frank R. Kschischang, Ralf Koetter, P. Glenn Gulak |
Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 39(1-2), pp. 93-111, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Reed-Solomon decoders, Sudan's algorithm, Guruswami-Sudan algorithm, Koetter-Vardy algorithm, Hasse derivative, VLSI architectures, list decoding, polynomial interpolation, soft-decision decoding |
37 | Matthias Klaus, Ad J. van de Goor |
Tests for Resistive and Capacitive Defects in Address Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 31-36, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
address decoders, test conditions, Defects, opens, dynamic faults, capacitive coupling |
36 | Narayan Prasad, Inaki Berenguer, Xiaodong Wang 0001 |
Design of Spherical Lattice Space-Time Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 54(11), pp. 4847-4865, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
36 | Arul D. Murugan, Hesham El Gamal, Mohamed Oussama Damen, Giuseppe Caire |
A unified framework for tree search decoding: rediscovering the sequential decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 52(3), pp. 933-953, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer |
Area-efficient high-throughput MAP decoder architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(8), pp. 921-933, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Haruhiko Kaneko |
Error Control Coding for Semiconductor Memory Systems in the Space Radiation Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 93-101, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Juan A. Garay, Jessica Staddon, Avishai Wool |
Long-Lived Broadcast Encryption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CRYPTO ![In: Advances in Cryptology - CRYPTO 2000, 20th Annual International Cryptology Conference, Santa Barbara, California, USA, August 20-24, 2000, Proceedings, pp. 333-352, 2000, Springer, 3-540-67907-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Moni Naor, Benny Pinkas |
Threshold Traitor Tracing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CRYPTO ![In: Advances in Cryptology - CRYPTO '98, 18th Annual International Cryptology Conference, Santa Barbara, California, USA, August 23-27, 1998, Proceedings, pp. 502-517, 1998, Springer, 3-540-64892-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
33 | Liang-Jin Lin, Antonio Ortega |
Perceptually Based Video Rate Control Using Pre-Filtering and Predicted Rate-Distortion Characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (2) ![In: Proceedings 1997 International Conference on Image Processing, ICIP '97, Santa Barbara, California, USA, October 26-29, 1997, pp. 57-60, 1997, IEEE Computer Society, 0-8186-8183-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
perceptually based video rate control, predicted rate-distortion characteristics, digital video coding, output data rate, output quality, MPEG Test Model 5, channel rates, video sources, block classification, rate control optimization process, MPEG decoders, H.263 encoders, MPEG-4 encoders, blockiness, rate distortion theory, pre-filtering, MPEG-1, computational overhead |
33 | Daby M. Sow, Alexandros Eleftheriadis |
Algorithmic Representation of Visual Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (2) ![In: Proceedings 1997 International Conference on Image Processing, ICIP '97, Santa Barbara, California, USA, October 26-29, 1997, pp. 250-253, 1997, IEEE Computer Society, 0-8186-8183-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
algorithmic representation, complexity distortion theory, programmable communication systems design, programmable decoders, intelligent encoders design, tools downloading, audio-visual information, video coding, MPEG-4, rate distortion theory, visual information, algorithm selection |
33 | Heng Liao, Andrew Wolfe |
Available Parallelism in Video Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 321-329, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
MPEG1, MPEG2, SPEC benchmarks, audio applications, general-purpose applications, linear complexity global scheduling algorithm, video coding, encoders, instruction-level parallelism, decoders, optimization techniques, MPEG4, H.263, media processors, video applications, graphics applications |
31 | M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli |
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11), pp. 2053-2067, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Daesun Oh, Keshab K. Parhi |
Area efficient controller design of barrel shifters for reconfigurable LDPC decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 240-243, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Michael A. Turi, José G. Delgado-Frias |
High-performance low-power AND and Sense-Amp address decoders with selective precharging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1464-1467, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Zhongfeng Wang 0001 |
High-Speed Recursion Architectures for MAP-Based Turbo Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(4), pp. 470-474, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Frédéric Guilloud, Emmanuel Boutillon, Jacky Tousch, Jean-Luc Danger |
Generic Description and Synthesis of LDPC Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 55(11), pp. 2084-2091, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Yi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang, Bin-Da Liu |
Combined Decoding and Flexible Transform Designs for Effective H.264/AVC Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3135-3138, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Jia Wang 0003, Ming-Yang Kao, Hai Zhou 0001 |
Address generation for nanowire decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 525-528, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
testing, decoder, nanowire |
31 | Khalid A. Darabkh, W. David Pan |
Stationary queue-size distribution for variable complexity sequential decoders with large timeout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference ![In: Proceedings of the 44st Annual Southeast Regional Conference, 2006, Melbourne, Florida, USA, March 10-12, 2006, pp. 331-336, 2006, ACM, 1-59593-315-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Fano decoder, queue size distribution, timeout |
31 | Shantanu Chakrabartty |
CMOS analog iterative decoders using margin propagation circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu 0002, Yin-Tsung Hwang, Jun-Hong Chen |
VLSI architectural design tradeoffs for sliding-window log-MAP decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(4), pp. 439-447, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Michael J. Thul, Frank Gilbert, Timo Vogt, Gerd Kreiselmaier, Norbert Wehn |
A Scalable System Architecture for High-Throughput Turbo-Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 39(1-2), pp. 63-77, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
wireless, VLSI architectures, interleaving, high-throughput, Turbo-Decoder, parallel decoding |
31 | Mimi Yiu, Chris Winstead, Vincent C. Gaudet, Christian Schlegel |
Digital built-in self-test of CMOS analog iterative decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2204-2207, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Christian Neeb, Michael J. Thul, Norbert Wehn |
Network-on-chip-centric approach to interleaving in high throughput channel decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1766-1769, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Jun Jin Kong, Keshab K. Parhi |
Low-latency architectures for high-throughput rate Viterbi decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(6), pp. 642-651, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Mohamed Azimane, Ananta K. Majhi |
New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 123-128, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Mohammad M. Mansour, Naresh R. Shanbhag |
High-throughput LDPC decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(6), pp. 976-996, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri |
Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 250-255, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Jie Dai, Chris Winstead, Chris J. Myers, Reid R. Harrison, Christian Schlegel |
Cell library for automatic synthesis of analog error control decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 481-484, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu 0002, Ming-Hwa Sheu |
VLSI architecture of extended in-place path metric update for Viterbi decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 206-209, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Chaitali Chakrabarti, Clint Mumford |
Efficient realizations of encoders and decoders based on the 2-D discrete wavelet transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(3), pp. 289-298, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Mariana-Eugenia Petre, Guido Masera |
A Parametrical Architecture for Reed-Solomon Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA, pp. 81-, 1996, IEEE Computer Society, 0-8186-7502-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
27 | Eirik Rosnes |
Stopping Set Analysis of Iterative Row-Column Decoding of Product Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 54(4), pp. 1551-1560, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Soheil Mohajer, Chao Tian 0002, Suhas N. Diggavi |
Asymmetric Multi-level Diversity Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DCC ![In: 2008 Data Compression Conference (DCC 2008), 25-27 March 2008, Snowbird, UT, USA, pp. 412-421, 2008, IEEE Computer Society, 978-0-7695-3121-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Yuanliang Huang, Jiangzhou Wang, Kenichi Higuchi |
A Novel Layered Space-Time-Frequency Architecture with Convolutional Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 65th IEEE Vehicular Technology Conference, VTC Spring 2007, 22-25 April 2007, Dublin, Ireland, pp. 1816-1820, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli |
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 765-772, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Aggelos Kiayias, Serdar Pehlivanoglu |
Pirate Evolution: How to Make the Most of Your Traitor Keys. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CRYPTO ![In: Advances in Cryptology - CRYPTO 2007, 27th Annual International Cryptology Conference, Santa Barbara, CA, USA, August 19-23, 2007, Proceedings, pp. 448-465, 2007, Springer, 978-3-540-74142-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Nima Sadeghi, Sheryl L. Howard, Soraya Kasnavi, Kris Iniewski, Vincent C. Gaudet, Christian Schlegel |
Analysis of error control code use in ultra-low-power wireless sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Fei Sun, Tong Zhang 0002 |
Parallel high-throughput limited search trellis decoder VLSI design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(9), pp. 1013-1022, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Todd P. Coleman, Muriel Médard, Michelle Effros |
Towards Practical Minimum-Entropy Universal Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DCC ![In: 2005 Data Compression Conference (DCC 2005), 29-31 March 2005, Snowbird, UT, USA, pp. 33-42, 2005, IEEE Computer Society, 0-7695-2309-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Michael J. Thul, Norbert Wehn, L. P. Rao |
Enabling high-speed turbo-decoding through concurrent interleaving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 897-900, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Gerald W. Neufeld, Yueli Yang |
The Design and Implementation of an ASN.1-C Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 16(10), pp. 1209-1220, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
abstract syntax notation one, ASN.1-C compiler, international standard specification, transfer-syntax, basic encoding rules, external data representation, ED library, CASN1, design, user interface, protocol, protocols, standards, C, implementation, encoding, program compilers, decoding, decoding |
26 | Aleksander Kubica, Nicolas Delfosse |
Efficient color code decoders in d≥2 dimensions from toric code decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Quantum ![In: Quantum 7, pp. 929, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Alexios Balatsoukas-Stimming, Pascal Giard, Andreas Burg |
Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1702.04707, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
26 | Alexios Balatsoukas-Stimming, Pascal Giard, Andreas Burg |
Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCNC Workshops ![In: 2017 IEEE Wireless Communications and Networking Conference Workshops, WCNC Workshops 2017, San Francisco, CA, USA, March 19-22, 2017, pp. 1-6, 2017, IEEE, 978-1-5090-5908-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
26 | Alexios Balatsoukas-Stimming |
Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2016 |
DOI RDF |
|
26 | Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross |
Unrolled Polar Decoders, Part II: Fast List Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1505.01466, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
26 | Matthew Collin Jordan, Ramachandran Vaidyanathan |
MU-decoders: A class of fast and efficient configurable decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 24th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010, Atlanta, Georgia, USA, 19-23 April 2010 - Workshop Proceedings, pp. 1-4, 2010, IEEE. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
23 | Simone Borri, Magali Hage-Hassan, Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel |
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(2), pp. 169-179, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
address decoders, core-cells, memory testing, dynamic faults |
23 | Ziad Al Kachouh, Maurice G. Bellanger |
Exact DCT-Based Spatial Domain Interpolation of Blocks in Images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (1) ![In: Proceedings 1997 International Conference on Image Processing, ICIP '97, Santa Barbara, California, USA, October 26-29, 1997, pp. 897-900, 1997, IEEE Computer Society, 0-8186-8183-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
exact DCT-based spatial domain interpolation, image blocks, image decoders, simulations, image processing, image coding, image coding, image restoration, pixels, computation cost |
23 | Manoj Franklin, Kewal K. Saluja |
Hypergraph Coloring and Reconfigured RAM Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(6), pp. 725-736, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
hypergraph coloring, reconfigured RAM testing, RAM decoders, critical path lengths, memory chips, physical neighborhood pattern sensitive faults, reconfigured DRAMs, decoder faults, computational complexity, logic testing, redundancy, reconfigurable architectures, stuck-at faults, graph colouring, random-access storage, integrated memory circuits, test lengths, test algorithms, DRAM chips, silicon area |
23 | Tsutomu Sasao |
On the Optimal Design of Multiple-Valued PLA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(4), pp. 582-592, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
multiple-valued PLAs, literal functions, 2-bit decoders, logic design, programmable logic arrays, many-valued logics, optimal design, logic arrays, permutation network |
22 | Osamu Shimada, Toshiyuki Nomura, Akihiko Sugiyama, Masahiro Serizawa |
Tradeoff Between Complexity and Memory Size in the 3GPP Enhanced aacPlus Decoder: Speed-Conscious and Memory-Conscious Decoders on a 16-Bit Fixed-Point DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(3), pp. 297-303, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Audio codec, 3GPP enhanced aacPlus, DSP implementation, Memory size, Computational complexity, Tradeoff |
22 | Cor Meenderinck, Arnaldo Azevedo, Ben H. H. Juurlink, Mauricio Alvarez 0001, Alex Ramírez |
Parallel Scalability of Video Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(2), pp. 173-194, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Scalability, Parallel processing, Chip multiprocessors, H.264, Video codecs |
22 | Xinming Huang 0001, Cao Liang, Jing Ma 0006 |
System Architecture and Implementation of MIMO Sphere Decoders on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(2), pp. 188-197, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Chuanjun Zhang |
Reducing cache misses through programmable decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(4), pp. 5:1-5:31, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
low power, Cache, dynamic optimization |
22 | Egas Henes Neto, Gilson I. Wirth, Fernanda Lima Kastensmidt |
Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(5), pp. 425-437, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Fault-tolerance, Reliability, Testing, Built-in tests, Error-checking |
22 | Maximilien Gadouleau, Zhiyuan Yan 0001 |
On the Decoder Error Probability of Bounded Rank-Distance Decoders for Maximum RankDistance Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 54(7), pp. 3202-3206, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Narayan Prasad, Mahesh K. Varanasi, Luca Venturino, Xiaodong Wang 0001 |
An Analysis of the MIMO-SDMA Channel With Space-Time Orthogonal and Quasi-Orthogonal User Transmissions and Efficient Successive Cancellation Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 54(12), pp. 5427-5446, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gross |
Fully Parallel Stochastic LDPC Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 56(11), pp. 5692-5703, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Renfei Liu, Keshab K. Parhi |
Minimal complexity low-latency architectures for Viterbi decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2008, October 8-10, 2008, Washington, D.C. Metro Area, USA, pp. 140-145, 2008, IEEE, 978-1-4244-2924-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Rafal Dlugosz, Vincent C. Gaudet |
Current-mode memory cell with power down phase for discrete time analog iterative decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 748-751, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Mahdi Shabany, P. Glenn Gulak |
Scalable VLSI architecture for K-best lattice decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 940-943, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Vijay Nagarajan, Stefan Laendner, Nikhil Jayakumar, Olgica Milenkovic, Sunil P. Khatri |
High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 49(1), pp. 185-206, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
code construction, fully-parallel VLSI implementation, network of PLAs, iterative decoding, low-density parity-check codes |
22 | Saied Hemati, Amir H. Banihashemi |
Convergence Speed and Throughput of Analog Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 55(5), pp. 833-836, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Torben Brack, Matthias Alles, Timo Lehnigk-Emden, Frank Kienle, Norbert Wehn, Nicola E. L'Insalata, Francesco Rossi, Massimo Rovini, Luca Fanucci |
Low complexity LDPC code decoders for next generation standards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 331-336, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Zhengya Zhang, Lara Dolecek, Martin J. Wainwright, Venkat Anantharam, Borivoje Nikolic |
Quantization Effects in Low-Density Parity-Check Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: Proceedings of IEEE International Conference on Communications, ICC 2007, Glasgow, Scotland, UK, 24-28 June 2007, pp. 6231-6237, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Soo-Woong Lee, B. V. K. Vijaya Kumar |
Application of Soft-Decision Decoders to Non Narrow-Sense Reed-Solomon Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: Proceedings of IEEE International Conference on Communications, ICC 2007, Glasgow, Scotland, UK, 24-28 June 2007, pp. 6226-6230, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Christian Spagnol, William P. Marnane, Emanuel M. Popovici |
FPGA Implementations of LDPC over GF(2m) Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China, pp. 273-278, 2007, IEEE, 1-4244-1222-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Rachit Agarwal 0001, Emanuel M. Popovici, Brendan O'Flynn, Michael E. O'Sullivan |
A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1405-1408, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Seungbeom Lee, Hanho Lee, Jongyoon Shin, Je-Soo Ko |
A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 901-904, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Yang Liu 0016, Tong Zhang 0002, Jiang Hu |
Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 749-754, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Benjamin Farber, Kenneth Zeger |
Quantizers with uniform decoders and channel-optimized encoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 52(2), pp. 640-661, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel |
A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 430-431, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Chen Sun, Makoto Taromaru, Nemai Chandra Karmakar |
On the Combination of Receive Beamforming with Alamouti Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 63rd IEEE Vehicular Technology Conference, VTC Spring 2006, 7-10 May 2006, Melbourne, Australia, pp. 2798-2802, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Federico Quaglio, Fabrizio Vacca, Cristiano Castellano, Alberto Tarable, Guido Masera |
Interconnection framework for high-throughput, flexible LDPC decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE Designers' Forum ![In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 124-129, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-0-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Yuping Zhang, Jun Tang, Keshab K. Parhi |
Low Complexity List Updating Circuits for List Sphere Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, pp. 28-33, 2006, IEEE, 1-4244-0382-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Eric Rachlin, John E. Savage |
Nanowire addressing with randomized-contact decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 735-742, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Ming-Der Shieh, Tai-Ping Wang, Chien-Ming Wu, Chun-Ming Huang |
Efficient path metric access for reducing interconnect overhead in Viterbi decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Catherine Dezan, Christophe Jégo, Bernard Pottier, Christophe Gouyen, Loïc Lagadec |
The Case Study of Block Turbo Decoders on a Framework for Portable Synthesis on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 39th Hawaii International International Conference on Systems Science (HICSS-39 2006), CD-ROM / Abstracts Proceedings, 4-7 January 2006, Kauai, HI, USA, 2006, IEEE Computer Society, 0-7695-2507-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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